Signal channel self-diagnosis circuit of ultrasonic radar chip and ultrasonic radar chip

Abstract

The embodiment of the utility model provides a signal path self-diagnosis circuit of an ultrasonic radar chip and the ultrasonic radar chip, and the circuit comprises a first test path which is used for detecting a measurement system; and the second test channel comprises a first sub-test channel and a second sub-test channel, the first sub-test channel is used for detecting the digital signal generation unit and the driving stage unit, and the second sub-test channel is used for detecting the analog input circuit and the digital input circuit. According to the invention, independent detection and accurate fault positioning of each module can be realized, and the function safety, the self-test capability and the reliability of the ultrasonic radar chip are improved.

Description

Technical Field

[0001] This application relates to the field of image forming technology, and more specifically to a signal path self-diagnostic circuit for an ultrasonic radar chip and an ultrasonic radar chip. Background Technology

[0002] In modern automotive electronic systems, especially in autonomous driving and advanced driver assistance systems (ADAS), ultrasonic sensors are used not only for automatic parking but also for functions such as blind spot detection, lane keeping assist, and collision warning. To ensure these systems meet relevant functional safety requirements while maintaining high reliability and safety, self-testing and diagnostic capabilities are crucial; that is, the system must be able to detect potential faults or errors. However, traditional ultrasonic sensor testing methods often fail to meet these high requirements, particularly in the complex automotive electronic environment where signal interference and environmental changes can lead to inaccurate test results.

[0003] Traditional ultrasonic sensor testing methods rely on feedback from the overall circuit, which can only diagnose whether the results derived from the loop path meet the requirements. However, when the results are abnormal, they can only locate the loop error, but cannot locate which core module is faulty. There are limitations to targeted testing of individual modules and the core modules composed of their signal-related circuits, making it impossible to accurately locate the problem. Utility Model Content

[0004] In view of this, this application provides a signal path self-diagnostic circuit for an ultrasonic radar chip and an ultrasonic radar chip to solve the problem of inaccurate fault location in the prior art.

[0005] In a first aspect, embodiments of this application provide a signal path self-diagnostic circuit for an ultrasonic radar chip, the circuit comprising:

[0006] The first test path has an input terminal electrically connected to the first output terminal of the control unit and an output terminal electrically connected to the second input terminal of the control unit. The first test path is used to receive a first test signal output by the control unit and to detect the measurement system based on the first test signal. The measurement system is an ultrasonic radar measurement system.

[0007] The second test path includes a first sub-test path and a second sub-test path. The input terminal of the first sub-test path is electrically connected to the first output terminal of the control unit, and the output terminal of the first sub-test path is electrically connected to the first input terminal of the control unit. The first sub-test path is used to receive a first detection signal output by the control unit and to test the digital signal generation unit and the driver stage unit according to the first detection signal. The input terminal of the second sub-test path is electrically connected to the second output terminal of the control unit, and the output terminal of the second sub-test path is electrically connected to the second input terminal of the control unit. The second sub-test path is used to receive a second detection signal output by the control unit and to test the analog input circuit and the digital input circuit according to the second detection signal.

[0008] In one possible implementation, the first sub-test path includes a digital signal generation unit, a driver level unit, and a driver level monitoring unit; wherein...

[0009] The input terminal of the digital signal generation unit is electrically connected to the first output terminal of the control unit. The digital signal generation unit is used to receive the first detection signal output by the control unit and output a first digital signal according to the first detection signal. The input terminal of the drive stage unit is electrically connected to the first output terminal of the digital signal generation unit. The drive stage unit is used to receive the first digital signal and output a first drive output signal according to the first digital signal. The input terminal of the drive stage monitoring unit is electrically connected to the second output terminal of the drive stage unit. The drive stage monitoring unit is used to receive the first drive output signal and output a first response signal according to the first drive output signal.

[0010] In one possible implementation, the second sub-test path includes an analog test unit, an analog multiplexer, an analog input circuit, a first digital multiplexer, and a digital input circuit; wherein...

[0011] The input terminal of the analog test unit is electrically connected to the second output terminal of the control unit. The analog test unit is used to receive the second detection signal and output an analog test signal according to the second detection signal. The second input terminal of the analog multiplexer is electrically connected to the output terminal of the analog test unit. The analog multiplexer is used to receive the analog test signal and output a first analog input signal according to the analog test signal. The input terminal of the analog input circuit is electrically connected to the output terminal of the analog multiplexer. The analog input circuit is used to receive the first analog input signal and output a first analog output signal according to the first analog input signal. The first input terminal of the first digital multiplexer is electrically connected to the output terminal of the analog input circuit. The first digital multiplexer is used to receive the first analog output signal and output a first digital input signal according to the first analog output signal. The input terminal of the digital input circuit is electrically connected to the output terminal of the first digital multiplexer. The output terminal of the digital input circuit is electrically connected to the second input terminal of the control unit. The digital input circuit is used to receive the first digital input signal and output a second response signal according to the first digital input signal.

[0012] In one possible implementation, the circuit further includes:

[0013] The third test path includes a third sub-test path and a fourth sub-test path. The input terminal of the third sub-test path is electrically connected to the first output terminal of the control unit, and the output terminal of the third sub-test path is electrically connected to the third input terminal of the control unit. The third sub-test path is used to receive a third detection signal output by the control unit and to detect the digital signal generation unit based on the third detection signal. The input terminal of the fourth sub-test path is electrically connected to the third output terminal of the control unit, and the output terminal of the fourth sub-test path is electrically connected to the second input terminal of the control unit. The fourth sub-test path is used to receive a fourth detection signal output by the control unit and to detect the digital input circuit based on the fourth detection signal.

[0014] In one possible implementation, the third sub-test path includes a digital signal generation unit and a signal generation monitoring unit; wherein,

[0015] The input terminal of the digital signal generating unit is electrically connected to the first output terminal of the control unit. The digital signal generating unit is used to receive the third detection signal and output a second digital signal according to the third detection signal. The input terminal of the signal generating monitoring unit is electrically connected to the second output terminal of the digital signal generating unit. The output terminal of the signal generating monitoring unit is electrically connected to the third input terminal of the control unit. The signal generating monitoring unit is used to receive the second digital signal and output a third response signal according to the second digital signal.

[0016] In one possible implementation, the fourth sub-test path includes a digital test unit, a first digital multiplexer, and a digital input circuit; wherein,

[0017] The input terminal of the digital test unit is electrically connected to the third output terminal of the control unit. The digital test unit is used to receive the fourth detection signal and output a first digital test signal according to the fourth detection signal. The second input terminal of the first digital multiplexer is electrically connected to the output terminal of the digital test unit. The first digital multiplexer is used to receive the first digital test signal and output a second digital input signal according to the first digital test signal. The input terminal of the digital input circuit is electrically connected to the output terminal of the first digital multiplexer. The output terminal of the digital input circuit is electrically connected to the second input terminal of the control unit. The digital input circuit is used to receive the second digital input signal and output a fourth response signal according to the second digital input signal.

[0018] In one possible implementation, the first test path includes a digital signal generation unit, a driver stage unit, a measurement system, an analog multiplexer, an analog input circuit, a second digital multiplexer, and a digital input circuit; wherein...

[0019] The input terminal of the digital signal generation unit is electrically connected to the first output terminal of the control unit. The digital signal generation unit is used to receive the first test signal and output a third digital signal according to the first test signal. The input terminal of the drive stage unit is electrically connected to the first output terminal of the digital signal generation unit. The drive stage unit is used to receive the third digital signal and output a second drive output signal according to the third digital signal. The input terminal of the measurement system is electrically connected to the first output terminal of the drive stage unit. The measurement system is used to receive the second drive output signal and output a measurement signal according to the second drive output signal. The first input terminal of the analog multiplexer is connected to the first output terminal of the measurement system. The output terminal of the system is electrically connected. The analog multiplexer is used to receive the measurement signal and output a second analog input signal according to the measurement signal. The input terminal of the analog input circuit is electrically connected to the output terminal of the analog multiplexer. The analog input circuit is used to receive the second analog input signal and output a second analog output signal according to the second analog input signal. The first input terminal of the second digital multiplexer is electrically connected to the output terminal of the analog input circuit. The analog input circuit is used to output a third digital input signal according to the second analog output signal. The digital input circuit is used to output a fifth response signal according to the third digital input signal.

[0020] In one possible implementation, the first test path includes a digital test unit, a driver stage unit, a measurement system, an analog multiplexer, an analog input circuit, a first digital multiplexer, and a digital input circuit; wherein...

[0021] The digital test unit is used to output a second digital test signal based on the first test signal. The drive stage unit is used to output a second drive output signal based on the second digital test signal. The measurement system is used to output a measurement signal based on the second drive output signal. The analog multiplexer is used to output a second analog input signal based on the measurement signal. The analog input circuit is used to output a second analog output signal based on the second analog input signal. The first digital multiplexer is used to output a third digital input signal based on the second analog output signal. The input terminal of the digital input circuit is electrically connected to the output terminal of the first digital multiplexer. The output terminal of the digital input circuit is electrically connected to the second input terminal of the control unit. The digital input circuit is used to receive the third digital input signal and output a fifth response signal based on the third digital input signal.

[0022] In one possible implementation, the measurement system includes a transformer and an ultrasonic transducer, wherein the input terminal of the transformer is electrically connected to the output terminal of the drive stage unit, the first output terminal of the transformer is electrically connected to the first input terminal of the ultrasonic transducer, the first output terminal of the ultrasonic transducer is electrically connected to the second output terminal of the transformer, the ultrasonic transducer is used to receive the transformer signal output by the transformer, and output an ultrasonic measurement signal to the measurement channel through the second output terminal according to the transformer signal, the ultrasonic transducer is also used to receive the ultrasonic reflection signal returned from the measurement channel through the second input terminal, and output a received signal through the first output terminal according to the ultrasonic reflection signal;

[0023] The second output terminal of the transformer is also electrically connected to the first input terminal of the analog multiplexer for outputting the transformer signal and the received signal to the analog multiplexer.

[0024] In one possible implementation, the first sub-test path further includes a second digital multiplexer, and the driver-level monitoring unit is electrically connected to the signal generation and monitoring unit through the second digital multiplexer. In this case, the driver-level monitoring unit outputs a driver monitoring signal based on the first driver output signal. The first input terminal of the second digital multiplexer is electrically connected to the output terminal of the driver-level monitoring unit. The second digital multiplexer receives the driver monitoring signal and outputs a first monitoring input signal based on the driver monitoring signal. The input terminal of the signal generation and monitoring unit is electrically connected to the output terminal of the second digital multiplexer, and the output terminal of the signal generation and monitoring unit is electrically connected to the third input terminal of the control unit. The signal generation and monitoring unit receives the first monitoring input signal and outputs a first response signal based on the first monitoring input signal.

[0025] In one possible implementation, the third sub-test path further includes a second digital multiplexer, and the digital signal generation unit is electrically connected to the signal generation and monitoring unit through the second digital multiplexer. In this case, the digital signal generation unit is used to output a second digital signal according to the third detection signal. The second input terminal of the second digital multiplexer is electrically connected to the second output terminal of the digital signal generation unit. The second digital multiplexer is used to receive the second digital signal and output a second monitoring input signal according to the second digital signal. The input terminal of the signal generation and monitoring unit is electrically connected to the output terminal of the second digital multiplexer. The output terminal of the signal generation and monitoring unit is electrically connected to the third input terminal of the control unit. The signal generation and monitoring unit is used to receive the second monitoring input signal and output a third response signal according to the second monitoring input digital signal.

[0026] In one possible implementation, the second sub-test path further includes a digital test unit, which is located at the input of the analog test unit. In this case, the analog test unit is a digital-to-analog converter.

[0027] The input terminal of the simulation test unit is electrically connected to the second output terminal of the control unit. The simulation test unit is used to receive the second detection signal and output a simulation test signal according to the second detection signal, including:

[0028] The input terminal of the digital test unit is electrically connected to the third output terminal of the control unit. The digital test unit is used to receive the second detection signal and output a third digital test signal according to the second detection signal. The input terminal of the analog test unit is electrically connected to the output terminal of the digital test unit. The analog test unit is used to receive the third digital test signal and output an analog test signal according to the third digital test signal.

[0029] In one possible implementation, the digital test unit has the same circuit function as the digital signal generation unit.

[0030] In one possible implementation, the digital test unit and the digital signal generation unit share some circuit structures, wherein the digital signal generation unit includes a first register configuration module and a first logic unit connected in sequence, and the digital test unit includes a second register configuration module and a first logic unit connected in sequence.

[0031] In one possible implementation, the digital test unit is electrically connected to the digital channel simulation unit, and outputs the first digital test signal, the second digital test signal, or the third digital test signal through the digital channel simulation unit.

[0032] In one possible implementation, the circuit function of the analog test unit is consistent with that of the digital signal generation unit and the drive stage unit after they are electrically connected.

[0033] In one possible implementation, the analog test unit shares a portion of the circuit structure with the circuit after the digital signal generation unit and the driver stage unit are electrically connected. The circuit after the digital signal generation unit and the driver stage unit are electrically connected includes a first register configuration module, a first logic unit, and a second logic unit connected in sequence. The analog test unit includes a third register configuration module, a first logic unit, and a second logic unit connected in sequence.

[0034] In one possible implementation, the simulation test unit has the same circuit function as the drive stage unit.

[0035] In one possible implementation, the simulation test unit and the driver level unit share some circuit structures, wherein the driver level unit includes a second logic unit, and the simulation test unit includes a second logic unit.

[0036] In one possible implementation, the simulation test unit is electrically connected to the simulation channel simulation unit, and the simulation test signal is output through the simulation channel simulation unit.

[0037] Secondly, embodiments of this application provide an ultrasonic radar chip, including a signal path self-diagnostic circuit as described in any one of the first aspects. Attached Figure Description

[0038] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 This is a schematic diagram of an application scenario provided by an embodiment of this application;

[0040] Figure 2 A schematic diagram of the module structure of a signal path self-diagnostic circuit for an ultrasonic radar chip provided in an embodiment of this application;

[0041] Figure 3 A schematic diagram of the module structure of a signal path self-diagnostic circuit for another ultrasonic radar chip provided in an embodiment of this application;

[0042] Figure 4 A schematic diagram of the module structure of a signal path self-diagnostic circuit for another ultrasonic radar chip provided in an embodiment of this application;

[0043] Figure 5 A schematic diagram of the module structure of a signal path self-diagnostic circuit for another ultrasonic radar chip provided in an embodiment of this application;

[0044] Figure 6 A schematic diagram of the module structure of a signal path self-diagnostic circuit for another ultrasonic radar chip provided in an embodiment of this application;

[0045] Figure 7 A schematic diagram of the module structure of a signal path self-diagnostic circuit for another ultrasonic radar chip provided in an embodiment of this application;

[0046] Figure 8A schematic diagram of the module structure of the signal path self-diagnostic circuit of another ultrasonic radar chip provided in this application embodiment.

[0047] Figure 9 This is a schematic diagram of the normal operation path of the signal path self-diagnostic circuit of an ultrasonic radar chip provided in an embodiment of this application;

[0048] Figure 10 This application provides a schematic diagram of the structure of the first test path of the signal path self-diagnostic circuit of an ultrasonic radar chip.

[0049] Figure 11 A schematic diagram of the first test path of the signal path self-diagnostic circuit of another ultrasonic radar chip provided in an embodiment of this application;

[0050] Figure 12 This application provides a schematic diagram of the second test path of a signal path self-diagnostic circuit for an ultrasonic radar chip.

[0051] Figure 13 A schematic diagram of the second test path of the signal path self-diagnostic circuit of another ultrasonic radar chip provided in an embodiment of this application;

[0052] Figure 14 A schematic diagram of the second test path of the signal path self-diagnostic circuit of another ultrasonic radar chip provided in an embodiment of this application;

[0053] Figure 15 This application provides a schematic diagram of the third test path of a signal path self-diagnostic circuit for an ultrasonic radar chip.

[0054] Figure 16 This application provides a schematic diagram of the third test path of a signal path self-diagnostic circuit for an ultrasonic radar chip.

[0055] Figure 17 This is a schematic diagram of the structure of an ultrasonic radar chip provided in an embodiment of this application. Detailed Implementation

[0056] To better understand the technical solution of this application, the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0057] It should be understood that the described embodiments are merely some, not all, of the embodiments in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0058] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The singular forms “a,” “the,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0059] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0060] In modern automotive electronic systems, especially in autonomous driving and ADAS, ultrasonic sensors are used not only for automatic parking, but also for functions such as blind spot detection, lane keeping assist, and collision warning.

[0061] See Figure 1 This is a schematic diagram illustrating an application scenario provided in an embodiment of this application. Figure 1 The image shows a vehicle 100 and an obstacle 200. The rear of the vehicle 100 is equipped with multiple ultrasonic transducers 101. When the user (or in the case of autonomous driving) controls the vehicle 100 to reverse (or in any scenario such as parallel parking or obstacle recognition), the ultrasonic transducers 101 can emit ultrasonic waves and receive echo signals. (The ultrasonic transducer can be two independent devices including an ultrasonic emitting transducer and an ultrasonic receiving transducer, or it can be a single device that can both emit and receive ultrasonic waves.) The distance between the ultrasonic transducers 101 (i.e., the vehicle 100) and the obstacle 200 can be calculated, and corresponding prompts can be provided to the user (e.g., a warning sound is output through a buzzer or the distance to the obstacle is displayed on a screen) to assist the user in driving safely.

[0062] It should be pointed out that, Figure 1 The examples provided in this application are merely one possible application scenario and should not be construed as limiting the scope of protection of this application. For instance, in addition to being used for obstacle detection in vehicles to assist in automatic parking, blind spot detection, and collision warning, ultrasonic ranging may also be used in applications such as lane keeping while the vehicle is in motion. In other application scenarios, obstacles may also be referred to as "the objects being detected." Besides being located at the rear of the vehicle, ultrasonic transducers can also be located at the side or front of the vehicle to detect obstacles on the side or front of the vehicle. In addition to four ultrasonic transducers, more or fewer ultrasonic transducers can be used, etc. This application does not impose specific limitations on these aspects.

[0063] To ensure these systems not only meet relevant functional safety requirements but also possess high reliability and safety, self-testing and diagnostic capabilities become particularly important; that is, the system must be able to detect potential faults or errors. Traditional ultrasonic sensor testing methods often fail to meet these high requirements, especially in the complex automotive electronic environment where signal interference and environmental changes can lead to inaccurate test results.

[0064] Existing ultrasonic sensor testing relies on feedback from the overall circuit, which can only diagnose whether the results derived from the loop path meet the requirements. However, when the results are abnormal, it can only locate the loop error, but cannot locate which core module is faulty. There are limitations to targeted testing of individual modules and the core modules composed of their signal-related circuits, making it impossible to accurately locate problems and perform individual module debugging.

[0065] To address the aforementioned issues, this application provides a signal path self-diagnostic circuit for an ultrasonic radar chip and an ultrasonic radar chip itself. By establishing a first test path, a second test path, and a third test path, this application enables targeted testing of the core module. When a fault occurs in the signal path of the ultrasonic radar chip, the faulty module can be accurately located, and individual debugging of the faulty module can be achieved. This improves the system's functional safety, self-testing capability, and reliability, meeting the high requirements of the automotive electronics field for ultrasonic sensors.

[0066] The following is a detailed description with reference to the accompanying drawings.

[0067] See Figure 2 This is a schematic diagram of the module structure of a signal path self-diagnostic circuit for an ultrasonic radar chip provided in an embodiment of this application. Figure 2As shown, the self-diagnostic circuit includes a first test path 100, a second test path 200, and a third test path 300. The input terminal of the first test path 100 is electrically connected to the first output terminal of the control unit, and the output terminal of the first test path 100 is electrically connected to the second input terminal of the control unit. The first test path 100 is used to receive a first test signal SOTa and to test the measurement system 120 based on the first test signal SOTa. The measurement system 120 is an ultrasonic radar measurement system. The second test path 200 includes a first sub-test path 210 and a second sub-test path 220. The input terminal of the first sub-test path 210 is electrically connected to the first output terminal of the control unit, and the output terminal of the first sub-test path 210 is electrically connected to the third input terminal of the control unit. The first sub-test path 210 is used to receive a first detection signal SOTb1 and to test the digital signal generation unit and the driver unit based on the first detection signal SOTb1. The second sub-test path 220 is used to detect the analog input circuit (AS) and digital input circuit (DSI). The input terminal of the second sub-test path 220 is electrically connected to the second output terminal of the control unit, and the output terminal of the second sub-test path 220 is electrically connected to the second input terminal of the control unit. The second sub-test path 220 is used to receive the second detection signal S0Tb2 and to detect the analog input circuit (AS) and digital input circuit (DSI) according to the second detection signal S0Tb1.

[0068] The embodiments of this application can test the measurement system through the first test path and test DSO, DR, AS and DSI through the second test path, so as to accurately locate the fault when the signal path of the ultrasonic chip fails.

[0069] In one possible implementation, the signal path self-diagnostic circuit of the ultrasonic radar chip also includes a third test path 300, such as... Figure 3 As shown. Specifically, the third test path 300 includes a third sub-test path 310 and a fourth sub-test path 320. The input terminal of the third sub-test path 310 is electrically connected to the first output terminal of the control unit, and the output terminal of the third sub-test path 310 is electrically connected to the third input terminal of the control unit. The third sub-test path 310 is used to receive the third detection signal S0Tc1 and to test the digital signal generator (DSO) according to the third detection signal S0Tc1. The input terminal of the fourth sub-test path 320 is electrically connected to the third output terminal of the control unit, and the output terminal of the fourth sub-test path 320 is electrically connected to the second input terminal of the control unit. The fourth sub-test path 320 is used to receive the fourth detection signal S0Tc2 and to test the digital input circuit DSI according to the fourth detection signal S0Tc1.

[0070] The embodiments of this application can detect DSO and DSI through a third test path, so as to accurately locate the faults of DSO and DSI when the signal path of the ultrasonic chip fails.

[0071] The first test path, the second test path, and the third test path will be further described below with reference to the accompanying drawings.

[0072] See Figure 4 This is an embodiment of the present application. Figure 3 Based on this, a schematic diagram of the module structure of the signal path self-diagnostic circuit of another ultrasonic radar chip is provided. (See diagram below.) Figure 4 As shown, the self-diagnostic circuit includes a control unit (CTR) 110. The first output terminal of CTR 110 is electrically connected to the input terminal of DSO 111. The first output terminal of DSO 111 is electrically connected to the input terminal of DR 112. The first output terminal of DR 112 is electrically connected to the input terminal of measurement system 120. The output terminal of measurement system 120 is electrically connected to the first input terminal of AMX 114. The output terminal of AMX 114 is electrically connected to the input terminal of AS115. The output terminal of AS115 is electrically connected to the first input terminal of first DMX (Digital Multiplier, DMX) 116. The output terminal of first DMX 116 is electrically connected to the input terminal of DSI 117. The output terminal of DSI 117 is electrically connected to the second input terminal of CTR 110. The second output terminal of CTR 110 is electrically connected to the input terminal of analog test unit 221. The output terminal of analog test unit 221 is electrically connected to the second input terminal of AMX 114. The third output terminal of 110 is electrically connected to the input terminal of digital test unit 113. The output terminal of digital test unit 113 is electrically connected to the second input terminal of first DMX 116. The second output terminal of DR 112 is electrically connected to the input terminal of DR monitoring unit 212. The output terminal of DR monitoring unit 212 is electrically connected to the first input terminal of CTR 110. The second output terminal of DSO 111 is electrically connected to the input terminal of signal monitoring unit 214. The output terminal of signal monitoring unit 214 is electrically connected to the third input terminal of CTR 110.

[0073] In its implementation, the control unit (CTR) 110 is responsible for the operation and coordination of various parts of the system, ensuring the correct generation and processing of signals. Specifically, the CTR 110 can obtain control programs or control instructions from the host computer or upper-level computer it is connected to, or it can control the signal path self-diagnostic circuit of the ultrasonic radar chip according to the control programs or control instructions stored in the CTR 110 beforehand. At the same time, the CTR 110 also receives the detection signals or detection results output by the self-diagnostic circuit, processes the detection signals, or sends the detection signals or detection results to the host computer or upper-level computer.

[0074] DSO 111 receives control signals from CTR 110 and generates various digital signals based on these signals. These generated digital signals are used for signal testing and drive control of the self-diagnostic circuit. Specifically, when the signal path of the ultrasonic radar chip is fault-free, the self-diagnostic circuit operates in normal mode. In this mode, the digital signals generated by DSO 111 are used for drive control of DR112. When a fault occurs in the signal path of the ultrasonic radar chip, the self-diagnostic circuit enters test mode. In this mode, the digital signals generated by DSO 111 are used for signal testing of the first sub-test path 210 and the third sub-test path 310.

[0075] DR 112 is used to amplify and shape the input signal to drive subsequent circuits or devices, ensuring sufficient signal strength. Specifically, DR 112 can output the amplified and shaped signal to different modules in different circuit operating modes. For example, in the normal operating mode of the self-diagnostic circuit, it outputs the signal to the measurement system 120; in the test mode of the self-diagnostic circuit, it outputs the signal to the measurement system 120 in the first test path and to the DR monitoring unit 212 in the second test path.

[0076] AMX 114 is used to select and send one of multiple analog signals to the output for signal processing. Specifically, AMX 114 can send an analog signal sent by measurement system 120 or analog signal sent by analog test unit 221 to AS115.

[0077] The AS115 is used to receive and process input signals from sensors or other analog signal sources, and typically includes signal amplification and filtering functions. Specifically, the AS115 receives analog signals sent by the AMX 114, processes the analog signals, and then converts the analog signals into digital signals for output.

[0078] The first DMX 116 is used to output the digital signal sent by the digital test unit 111 or the digital signal sent by AS115 to the DSI 117.

[0079] The DS I 117 is used to receive and process digital signals. Specifically, after receiving a digital signal, the DS I 117 can perform different processing on different digital signals and send the processing results (detection results) to the CTR 110.

[0080] The digital test unit 113 receives control signals sent by the CTR 110 and generates various digital signals based on these control signals. These generated digital signals are used for signal testing of the self-diagnostic circuit. Specifically, when a signal path of the ultrasonic radar chip malfunctions, the digital test unit 113 sends different digital signals depending on the received control signals, for signal testing of the first test path, the second test path, or the third test path (signal testing of the first and second test paths will be described in detail below).

[0081] The analog test unit 221 is used to output an analog test signal based on the input signal to perform circuit signal testing. Specifically, the analog test unit 221 can simulate the output signal of the measurement system 120 based on the input signal so as to perform signal testing on AS115 and DSI 117 in the second test path.

[0082] The DR monitoring unit 212 is used to monitor the signal output by the DR 112 and send the monitoring results to the CTR 110.

[0083] The signal generation and monitoring unit 214 is used to receive and process digital signals. Specifically, after receiving a digital signal, the signal generation and monitoring unit 214 can perform different processing on different digital signals and send the processing results (detection results) to the CTR 110. Of course, in practical applications, the signal generation and monitoring unit 214 can also be set up in the CTR 110 as a module within the CTR 110.

[0084] The measurement system 120 includes a transformer (UEB) 121 and an ultrasonic transducer (TR) 122. The UEB 121 is used to boost or reduce voltage during signal transmission, while the TR 122 outputs an ultrasonic measurement signal based on the input signal and receives the reflected ultrasonic signal. Specifically, after receiving an analog signal, the UEB 121 boosts the analog signal and sends the boosted analog signal (transformed signal) to the TR 122. Excited by the boosted analog signal, the TR 122 sends an ultrasonic measurement signal to the Measurement Channel (CN), receives the reflected ultrasonic signal returned through the CN, and outputs a received signal based on the reflected ultrasonic signal. When the signal path of the ultrasonic radar chip is fault-free, the measurement signal output by the measurement system 120 is the received signal. When the signal path of the ultrasonic radar chip is faulty, the measurement signal output by the measurement system 120 includes both the boosted analog signal and the received signal.

[0085] In one possible implementation, such as Figure 5 As shown, it can also be found in Figure 4 Based on this, a second DMX 213 is set up. At this time, the output terminal of the DR monitoring unit 212 is electrically connected to the first input terminal of the second DMX 213, the output terminal of the second DMX 213 is electrically connected to the input terminal of the signal generation monitoring unit 214, the output terminal of the signal generation monitoring unit 214 is electrically connected to the third input terminal of the CTR 110, and the second output terminal of the DSO 111 is electrically connected to the second input terminal of the second DMX 213.

[0086] In one possible implementation, it is also possible to... Figure 4 or Figure 5 Based on this, the output terminals of the digital test unit 113 are adjusted to be a first output terminal and a second output terminal. The first output terminal is electrically connected to the input terminal of the DR 112, and the second output terminal is electrically connected to the second input terminal of the first DMX 116. This allows the digital test unit 113 to provide drive control signals to the DR 112 during self-diagnosis. Figure 5 For example, the adjusted structure is as follows: Figure 6 As shown.

[0087] Or in another possible implementation, it can also be in Figure 4 or Figure 5Based on this, the output terminals of the digital test unit 113 are adjusted to a first output terminal, a second output terminal, and a third output terminal. The first output terminal is electrically connected to the input terminal of the DR 112, the second output terminal is electrically connected to the second input terminal of the first DMX 116, and the third output terminal is electrically connected to the input terminal of the analog test unit 221. That is, the input terminal of the analog test unit 221 is electrically connected to the third output terminal of the CTR 110 through the digital test unit 113. This allows the digital test unit 113 to provide drive control signals to the DR 112 and test signals to the analog test unit 221 during the self-diagnosis process. Figure 5 For example, the adjusted structure is as follows: Figure 7 As shown.

[0088] When the first output terminal of the digital test unit 113 is electrically connected to the input terminal of DR 112, to ensure accurate signal flow, a third DMX 118 can be set at the input terminal of DR 112, such as... Figure 8 As shown, the first input terminal of the third DMX 118 is electrically connected to the output terminal of the DSO 111 (at this time, the DSO 111 only needs one output terminal), the second input terminal of the third DMX 118 is electrically connected to the first output terminal of the digital test unit 113, the first output terminal of the third DMX 118 is electrically connected to the input terminal of the DR 112, and the second output terminal of the third DMX 118 is electrically connected to the second input terminal of the second DMX 213 (when the second DMX 213 is not present, the second output terminal of the third DMX 118 is electrically connected to the input terminal of the signal generation and monitoring unit 214). This allows for control of the signal output from the DSO 111 to flow to the second DMX 213 (signal generation and monitoring unit 214) or DR 112 during the self-diagnostic process, and control of the signal output from the digital test unit 113 to flow to DR 112. It should be noted that the third DMX 118 only plays a role in controlling signal flow in the self-diagnostic circuit and does not change the signal.

[0089] Of course, in practical applications, it can also be used in Figure 4 or Figure 5 Based on this, the output terminals of the digital test unit 113 are adjusted to be a second output terminal and a third output terminal. The second output terminal is electrically connected to the second input terminal of the first DMX 116, and the third output terminal is electrically connected to the input terminal of the analog test unit 221. That is, the input terminal of the analog test unit 221 is electrically connected to the third output terminal of the CTR 110 through the digital test unit 113, so that test signals can also be provided to the analog test unit 221 through the digital test unit 113 during the self-diagnosis process.

[0090] In practice, when the signal path of the ultrasonic radar chip is fault-free, the self-diagnostic circuit is in normal operating mode. At this time, the operating path of the self-diagnostic circuit is as follows: Figure 9 The bolded lines shown include DSO 111, DR 112, UEB121, TR 122, AMX 114, AS115, first DMX116, and DSI 117. Specifically, the input terminal of DSO 111 is electrically connected to the first output terminal of CTR 110 to receive the working signal S0 output by CTR 110 and output a digital signal S1 based on the working signal S0; the input terminal of DR 112 is electrically connected to the first output terminal of DSO 111 to receive the digital signal S1 and output an analog signal S2 based on the digital signal S1; the input terminal of UEB 121 is electrically connected to the first output terminal of DR 112 to receive the analog signal S2 and output a transformer signal based on the analog signal S2; the first input terminal of TR 122 is electrically connected to the first output terminal of UEB 121 to receive the transformer signal and output an ultrasonic measurement signal MS to CN through the second output terminal based on the transformer signal, and receive the ultrasonic reflection signal ES returned through CN through the second input terminal, and output a received signal based on ES through the first output terminal. At this time, the received signal is the measurement signal S3 output by the measurement system 120. It should be noted that the received signal can be output to the outside of the measurement system from the first output terminal of TR 122. At this time, AMX The first input terminal of AMX 114 is electrically connected to the second output terminal of UEB 121 and the first output terminal of TR 122 to receive the measurement signal S3. Alternatively, the signal can be sent from TR 122 to UEB 121 and then output to the outside of the measurement system via the second output terminal of UEB 121. In this case, the first input terminal of AMX 114 is electrically connected to the second output terminal of UEB 121 to receive the measurement signal S3. After receiving the measurement signal S3, AMX 114 outputs an analog signal S4 based on the measurement signal S3. The input terminal of AS115 is electrically connected to the output terminal of AMX 114 to receive the analog signal S4 and output a digital signal S5 based on the analog signal S4. The first input terminal of the first DMX 116 is electrically connected to the output terminal of AS115 to receive the digital signal S5 and output a digital signal S6 based on the digital signal S5. The input terminal of DMX 117 is electrically connected to the output terminal of the first DMX 116 to receive the digital signal S6 and output a response signal S7 based on the digital signal S6.

[0091] After receiving the response signal S7 at the first input terminal of CTR 110, it can determine whether there is a fault in the signal path of the ultrasonic radar chip based on the response signal S7. When the response signal S7 meets the expectations, it is confirmed that there is no fault in the signal path of the ultrasonic radar chip, and the self-diagnostic path continues to operate in normal working mode. When the response signal S7 does not meet the expectations, it is confirmed that there is a fault in the signal path of the ultrasonic radar chip, and the self-diagnostic path enters the test mode.

[0092] See Figure 10 This is a schematic diagram of the first test path of a signal path self-diagnostic circuit for an ultrasonic radar chip provided in an embodiment of this application. The first test path is as follows: Figure 10 As shown by the bold black line, when the first test path is working, the CTR 110 outputs the first test signal SOTa to the first test path.

[0093] Specifically, the first test path includes DSO 111, DR 112, UEB 121, TR 122, AMX 114, AS115, first DMX 116, and DSI 117. Specifically, the input of DSO 111 is electrically connected to the first output of CTR 110, used to receive the first test signal S0Ta output by CTR 110, and output a third digital signal S1Ta based on the first test signal S0Ta; the input of DR 112 is electrically connected to the first output of DSO 111, used to receive the third digital signal S1Ta, and output a second drive output signal S2Ta based on the third digital signal S1Ta; the input of UEB 121 is electrically connected to the first output of DR 112, used to receive the second drive output signal S2Ta, and output a transformer signal based on the second drive output signal S2Ta; the first input of TR 122 is electrically connected to UEB 111, DR 112, UEB 121, TR 122, AMX 114, AS115, first DMX 116, and DSI 117. The first output terminal of 121 is electrically connected to receive the transformer signal and outputs an ultrasonic measurement signal MS to CN through the second output terminal based on the transformer signal. It also receives the ultrasonic reflection signal ES returned through CN through the second input terminal and outputs a received signal based on ES through the first output terminal. At this time, the transformer signal and the received signal constitute the measurement signal S3Ta output by the measurement system 120. It should be noted that the received signal can be sent from TR 122 to UEB 121 and then output to the outside of the measurement system through the second output terminal of UEB 121. At this time, the first input terminal of AMX 114 is electrically connected to the second output terminal of UEB 121 to receive the measurement signal S3Ta. After receiving the measurement signal S3Ta, AMX 114 outputs a second analog input signal S4Ta based on the measurement signal S3Ta. The input terminal of AS115 is electrically connected to the output terminal of AMX 114 to receive the second analog input signal S4Ta and output a second analog output signal S5Ta based on the second analog input signal S4Ta. The first DMX... The first input terminal of 116 is electrically connected to the output terminal of AS115, and is used to receive the second analog output signal S5Ta, and output the third digital input signal S6Ta according to the second analog output signal S5Ta; the input terminal of DS I 117 is electrically connected to the output terminal of the first DMX 116, and is used to receive the third digital input signal S6Ta, and output the fifth response signal S7Ta according to the third digital input signal S6Ta.

[0094] Since the fifth response signal S7Ta includes the response results to the transformer signal and the response results to the received signal, when the first input terminal of CTR 110 receives the fifth response signal S7Ta, it can determine whether there is a fault in the measurement system based on the fifth response signal S7Ta. Specifically, if the response result of the fifth response signal S7Ta to the transformer signal meets expectations, but the response result to the received signal does not meet expectations, then the measurement system is confirmed to be faulty, and the fault can be repaired by debugging the module of the measurement system. If the response result of the fifth response signal S7Ta to the transformer signal does not meet expectations, then it is confirmed that there is a faulty module in DSO 111, DR 112, AS115 and DSI 117, and the self-diagnostic path enters the second test path.

[0095] The embodiments of this application can confirm whether there is a fault in the measurement system through the first test path, realize independent detection of the measurement system, so that when the measurement system is faulty, the measurement system can be debugged separately.

[0096] In specific implementation, when the structure of the signal path self-diagnostic circuit of the ultrasonic radar chip is as follows: Figure 6-8 As shown, there is another first test path. The following uses... Figure 8 Let's take an example to illustrate.

[0097] See Figure 11 The embodiments of this application are based on Figure 8 A schematic diagram of the first test path of the signal path self-diagnostic circuit for another ultrasonic radar chip is provided, wherein the first test path is as follows: Figure 11 As shown by the bold black line in the image. Specifically, the first test path includes digital test unit 113, third DMX 118, DR 112, UEB 121, TR 122, AMX 114, AS 115, first DMX 116, and DSI 117. The digital test unit 113 is electrically connected to the third output of the CTR 110, and is used to receive the first test signal S0Ta output by the CTR 110, and output a second digital test signal S8Ta based on the first test signal S0Ta. The second input of the third DMX 118 is electrically connected to the first output of the digital test unit 113, and is used to receive the second digital test signal S8Ta, and output a digital signal S9Ta based on the second digital test signal S8Ta. The input of the DR 112 is electrically connected to the first output of the third DMX 118, and is used to receive the digital signal S9Ta, and output a second drive output signal S2Ta based on the digital signal S9Ta. The circuit connections of the other UEB 121, TR 122, AMX 114, AS115, first DMX 116 and DSI 117 can be found in the following diagram. Figure 10For the sake of brevity, the embodiments of this application will not be described in detail here.

[0098] In this embodiment, the second digital test signal can be directly output to the DR 112 via the digital test unit 113, thereby controlling the first test path to perform fault detection of the measurement system and avoiding interference with the line test when the DSO 111 is faulty.

[0099] In this embodiment, since the function of the digital test unit 113 is the same as that of the DSO 111, the digital test unit 113 can have the same circuit structure as the DSO 111. Based on this, to save costs and reduce circuit area, the digital test unit 113 and the DSO 111 can share some circuit structures. Specifically, the digital test unit 113 and the DSO 111 can share a single logic unit. That is, the circuit structure of the DSO 111 includes a first register configuration module and a first logic unit connected in sequence, and the circuit structure of the digital test unit 113 includes a second register configuration module and a first logic unit connected in sequence. The first register configuration module can also be called a working register, and the second register configuration module can also be called a test register.

[0100] See Figure 12 This is a schematic diagram of the second test path of a signal path self-diagnostic circuit for an ultrasonic radar chip provided in an embodiment of this application. The second test path is as follows: Figure 12 As shown by the bold black line, when the second test path is working, the CTR 110 outputs a second test signal S0Tb to the second test path. The second test signal S0Tb includes a first detection signal S0Tb1 and a second detection signal S0Tb2.

[0101] Specifically, the second test path includes a first sub-test path and a second sub-test path. The first sub-test path includes DSO 111, DR 112, and DR monitoring unit 212. The input terminal of DSO 111 is electrically connected to the first output terminal of CTR 110, used to receive the first detection signal S0Tb1 output by CTR 110, and output a first digital signal S1Tb based on the first detection signal S0Tb1; the input terminal of DR 112 is electrically connected to the first output terminal of DSO 111, used to receive the first digital signal S1Tb, and output a first drive output signal S2Tb based on the first digital signal S1Tb; the input terminal of DR monitoring unit 212 is electrically connected to the second output terminal of DR 112, used to receive the first drive output signal S2Tb, and output a first response signal S12Tb based on the first drive output signal S2Tb.

[0102] After receiving the first response signal S12Tb at the first input terminal of CTR 110, it can determine whether the DSO 111 and DR 112 modules are faulty based on the first response signal S12Tb. When the first response signal S12Tb meets the expectations, it is confirmed that the DSO 111 and DR 112 modules are fault-free. When the first response signal S12Tb does not meet the expectations, it is confirmed that there is a faulty module in DSO 111 and DR 112, and the self-diagnostic path enters the third test path.

[0103] In this embodiment, by setting a DR monitoring unit 212 to monitor the first drive output signal S2Tb and converting it into a drive monitoring signal S10Tb (digital signal), which is then sent to the signal generation monitoring unit 214 for correctness judgment, the diagnosis of DSO 111 and DR 112 can be realized, ensuring accurate fault location.

[0104] Continue reading Figure 12 The second sub-test path includes analog test unit 221, AMX 114, AS115, first DMX 116, and DSI 117. Specifically, the input terminal of the analog test unit 221 is electrically connected to the second output terminal of the CTR 110, for receiving the second detection signal S0Tb2 output by the CTR 110, and outputting an analog test signal S13Tb based on the second detection signal S0Tb2; the second input terminal of the AMX 114 is electrically connected to the output terminal of the analog test unit 221, for receiving the analog test signal S13Tb, and outputting a first analog input signal S4Tb based on the analog test signal S13Tb; the input terminal of the AS115 is electrically connected to the output terminal of the AMX 114, for receiving the first analog input signal S4Tb, and outputting a first analog output signal S5Tb based on the first analog input signal S4Tb; the first input terminal of the first DMX 116 is electrically connected to the output terminal of the AS115, for receiving the first analog output signal S5Tb, and outputting a first digital input signal S6Tb based on the first analog output signal S5Tb; the input terminal of the DSI 117 is electrically connected to the first DMX 116. The output terminal of 116 is electrically connected to receive the first digital input signal S6Tb and output the second response signal S7Tb according to the first digital input signal S6Tb.

[0105] After receiving the second response signal S7Tb at the second input terminal of CTR 110, it can determine whether the AS115 and DSI 117 modules are faulty based on the second response signal S7Tb. When the second response signal S7Tb meets the expectations, it is confirmed that the AS115 and DSI 117 modules are not faulty. When the second response signal S7Tb does not meet the expectations, it is confirmed that there is a faulty module in AS115 and DSI 117, and the self-diagnostic path enters the third test path.

[0106] In this embodiment of the application, the measurement signal output by the simulation test unit 221 is simulated by the measurement system, which can realize the diagnosis of AS115 and DSI 117, and ensure the accurate location of the fault.

[0107] In specific implementation, when the structure of the signal path self-diagnostic circuit of the ultrasonic radar chip is as follows: Figure 5-7 As shown, there is also another second test path. The following example... Figure 5 Let's take an example to illustrate.

[0108] See Figure 13 The embodiments of this application are based on Figure 5 A schematic diagram of the second test path of the self-diagnostic circuit for another ultrasonic radar chip is provided, wherein the second test path is as follows: Figure 12 As shown by the bold black line in the image.

[0109] Specifically, the first sub-test path includes DSO 111, DR 112, DR monitoring unit 212, second DMX 213 and signal generation monitoring unit 214. Specifically, the input terminal of DSO 111 is electrically connected to the first output terminal of CTR 110, for receiving the first detection signal S0Tb1 output by CTR 110, and outputting a first digital signal S1Tb based on the first detection signal S0Tb1; the input terminal of DR 112 is electrically connected to the first output terminal of DSO 111, for receiving the first digital signal S1Tb, and outputting a first drive output signal S2Tb based on the first digital signal S1Tb; the input terminal of DR monitoring unit 212 is electrically connected to the second output terminal of DR 112, for receiving the first drive output signal S2Tb, and outputting a drive monitoring signal S10Tb based on the first drive output signal S2Tb; the first input terminal of the second DMX 213 is electrically connected to the output terminal of DR monitoring unit 212, for receiving the drive monitoring signal S10Tb, and outputting a first monitoring input signal S11Tb based on the drive monitoring signal S10Tb; the input terminal of signal generation monitoring unit 214 is connected to the second DMX The output terminal of 213 is electrically connected to receive the first monitoring input signal S11Tb and output the first response signal S12Tb according to the first monitoring input signal S11Tb.

[0110] In specific implementation, when the structure of the signal path self-diagnostic circuit of the ultrasonic radar chip is as follows: Figure 8 As shown, there is also another second test path.

[0111] See Figure 14 The embodiments of this application are based on Figure 8 A schematic diagram of the second test path of the self-diagnostic circuit for another ultrasonic radar chip is provided, wherein the second test path is as follows: Figure 14 As shown by the bold black line in the image.

[0112] Specifically, with Figure 13 The first sub-test pathway in the middle is different, Figure 13 The first sub-test path also includes a third DMX 118. The first input terminal of the third DMX 118 is electrically connected to the output terminal of DSO 111, and the first output terminal of the third DMX 118 is electrically connected to the input terminal of DR 112, so as to receive the first digital signal S1Tb output by DSO 111, and output a digital signal S9Tb to DR 112 according to the first digital signal S1Tb. DR 112 outputs a first drive output signal S2Tb according to the digital signal S9Tb.

[0113] Specifically, with Figure 13 The second sub-test pathway differs from the one in that, Figure 13 The second sub-test path also includes a digital test unit 113. The input terminal of the digital test unit 113 is electrically connected to the third output terminal of the CTR 110, and is used to receive the second detection signal S0Tb2 output by the CTR 110, and output a third digital test signal S14Tb based on the second detection signal S0Tb2. The input terminal of the analog test unit 221 is electrically connected to the third output terminal of the digital test unit 113, and is used to receive the third digital test signal S14Tb, and output an analog test signal S13Tb based on the third digital test signal S14Tb.

[0114] In this embodiment, a third digital test signal can be directly generated by a digital test unit, and an analog test signal can be generated by an analog test unit based on the third digital signal to perform fault diagnosis of AS115 and DSI 117, providing multiple test circuits for fault diagnosis of AS115 and DSI117.

[0115] In this embodiment, when the input terminal of the analog test unit 221 is directly electrically connected to the second output terminal of the CTR 110, the circuit structure of the analog test unit 221 can be the same as the circuit structure after the DSO 111 and DR 112 are electrically connected. That is, the analog test unit 221 can be obtained by copying the circuit structure after the DSO 111 and DR 112 are electrically connected. Based on this, to save costs and reduce circuit area, the analog test unit 221 can share some circuit structures with the circuit after the DSO 111 and DR 112 are electrically connected. Specifically, the analog test unit 221 can share a logic unit with both the DSO 111 and DR 112. That is, the circuit after the DSO 111 and DR 112 are electrically connected includes a first register configuration module, a first logic unit, and a second logic unit connected in sequence, and the analog test unit includes a third register configuration module, a first logic unit, and a second logic unit connected in sequence.

[0116] When the input terminal of the analog test unit 221 is electrically connected to the third output terminal of the digital test unit 113, since the circuit structure of the digital test unit 113 is the same as that of DSO 111, the circuit structure of the analog test unit 221 is also the same as that of DR 112. Based on this, to save costs and reduce circuit area, the analog test unit 221 and DR 112 can share some circuit structures. Specifically, the analog test unit 221 and DR 112 can share a single logic unit; that is, DR 112 includes two logic units, and the analog test unit 221 includes a second logic unit.

[0117] See Figure 15 This is a schematic diagram of the third test path of a signal path self-diagnostic circuit for an ultrasonic radar chip provided in an embodiment of this application. The third test path is as follows: Figure 15 As shown by the bold black line, when the third test path is working, the CTR 110 outputs the third test signal S0Tc to the third test path. The third test signal S0Tc includes the third detection signal S0Tc1 and the fourth detection signal S0Tc2.

[0118] Specifically, the third test path includes a third sub-test path and a fourth sub-test path. The third sub-test path includes DS0 111 and a signal generation and monitoring unit 214. The input of DS0 111 is electrically connected to the first output of CTR 110, and is used to receive the third detection signal S0Tc1 output by CTR 110, and output a second digital signal S1Tc based on the third detection signal S0Tc1; the input of the signal generation and monitoring unit 214 is electrically connected to the second output of DS0 111, and is used to receive the second digital signal S1Tc, and output a third response signal S12Tc based on the second digital signal S1Tc.

[0119] In specific implementation, when a second DMX 213 exists, the structure of the third sub-test path can also be as follows: Figure 16As shown. Specifically, the input terminal of DSO 111 is electrically connected to the first output terminal of CTR 110, for receiving the third detection signal S0Tc1 output by CTR 110, and outputting a second digital signal S1Tc based on the third detection signal S0Tc1; the second input terminal of the second DMX 213 is electrically connected to the second output terminal of DSO 111, for receiving the second digital signal S1Tc, and outputting a second monitoring input signal S11Tc based on the second digital signal S1Tc; the input terminal of the signal generation monitoring unit 214 is electrically connected to the output terminal of the second DMX 213, for receiving the second monitoring input signal S11Tc, and outputting a third response signal S12Tc based on the second monitoring input signal S11Tc. After the first input terminal of CTR 110 receives the third response signal S12Tc, it can determine whether the DSO 111 module is faulty based on the third response signal S12Tc. When the third response signal S12Tc meets the expectations, it is confirmed that the DSO 111 module is not faulty. When the third response signal S12Tc does not meet the expectations, it is confirmed that the DSO 111 module is faulty. At this time, the DSO 111 module can be debugged separately to repair the DSO 111 module.

[0120] Understandably, if the DSO 111 module is fault-free, but the first response signal S12Tb does not meet expectations, then the DR 112 module is confirmed to be faulty. In this case, the DR 112 module can be debugged separately to repair it. If the DSO 111 module is faulty, then after repairing the DSO 111 module, signal testing can be performed through the first sub-test path. If the first response signal S12Tb meets expectations, then the DR 112 module is confirmed to be fault-free; otherwise, if the first response signal S12Tb does not meet expectations, then the DR 112 module is confirmed to be faulty, and the DR 112 module can be debugged separately to repair it.

[0121] This embodiment of the application, through the signal generation and monitoring unit 214, enables the self-diagnostic circuit to monitor signals during the signal generation stage, facilitating timely detection and handling of anomalies and enhancing the stability of the signal path of the ultrasonic radar chip. Simultaneously, by monitoring the digital signal generation device 211, this embodiment of the application can automatically identify potential errors during operation, reducing human intervention and improving overall functional safety. This embodiment of the application makes the testing process more systematic and automated, facilitating subsequent quality control and verification.

[0122] Continue reading Figure 15The fourth sub-test path includes a digital test unit 113, a first DMX 116, and a DSI 117. The input terminal of the digital test unit 113 is electrically connected to the third output terminal of the CTR 110, and is used to receive the fourth detection signal S0Tc2 output by the CTR 110, and output a first digital test signal S14Tc based on the fourth detection signal S0Tc2. The second input terminal of the first DMX 116 is electrically connected to the output terminal of the digital test unit 113, and is used to receive the first digital test signal S14Tc, and output a second digital input signal S6Tc based on the first digital test signal S14Tc. The input terminal of the DSI 117 is electrically connected to the output terminal of the second DMX 116, and is used to receive the second digital input signal S6Tc, and output a fourth response signal S7Tc based on the second digital input signal S6Tc.

[0123] After the second input terminal of CTR 110 receives the fourth response signal S7Tc, it can determine whether the DSI 117 module is faulty based on the fourth response signal S7Tc. When the fourth response signal S7Tc meets the expectations, it is confirmed that the DSI 117 module is fault-free. When the fourth response signal S7Tc does not meet the expectations, it is confirmed that there is a fault in the DSI 117 module. At this time, the DSI 117 module can be debugged separately to repair the DSI 117 module.

[0124] Understandably, if the DS I 117 module is fault-free, and the second response signal S7Tb does not meet expectations, then the AS115 module is confirmed to be faulty. In this case, the AS115 module can be debugged separately to repair it. If the DS I 117 module is faulty, then after repairing the DS I 117 module, signal testing can be performed through the second sub-test path. If the second response signal S7Tb meets expectations, then the AS115 module is confirmed to be fault-free; otherwise, if the second response signal S7Tb does not meet expectations, then the AS115 module is confirmed to be faulty, and the AS115 module can be debugged separately to repair it.

[0125] The digital test unit 113 of this application embodiment generates a test signal under the control of CTR, and transmits the signal to DSI 117 via the second DMX 116. By controlling the digital test unit 113, digital paths such as envelope processing can be detected.

[0126] It is understood that in this embodiment, when the response result of the fifth response signal S7Ta to the transformer signal does not meet expectations, and the response result to the received signal does not meet expectations, the faulty modules in DSO 111, DR 112, AS115 and DSI 117 can be identified first through the second test path and the third test path, and the faulty modules can be debugged and repaired. Then, the signal detection can be performed again through the first test path to determine whether there is a fault in the measurement system. If, at this time, the response result of the fifth response signal S7Ta to the transformer signal and the response result to the received signal both meet expectations, then the measurement system is confirmed to be fault-free. If the response result of the fifth response signal S7Ta to the transformer signal meets expectations, but the response result to the received signal does not meet expectations, then the measurement system is confirmed to be faulty, and the fault can be repaired by debugging the modules of the measurement system.

[0127] It should be noted that, in this embodiment, the digital test unit 113 can directly generate a first digital test signal, a second digital test signal, or a third digital test signal, or it can be electrically connected to the digital channel simulation unit and output the first digital test signal, the second digital test signal, or the third digital test signal through the digital channel simulation unit. The analog test unit 221 can directly generate an analog test signal, or it can be electrically connected to the analog channel simulation unit and output the analog test signal through the analog channel simulation unit.

[0128] This application embodiment utilizes a first test path, a second test path, and a third test path to independently test each module. This allows for accurate identification of faulty modules when problems occur in the signal path of the ultrasonic radar chip, enabling individual debugging of these faulty modules and reducing safety hazards caused by system failures. This application embodiment also saves significant debugging time and costs through precise signal monitoring.

[0129] Corresponding to the above embodiments, this application also provides a schematic diagram of the structure of an ultrasonic radar chip.

[0130] See Figure 17 This is a schematic diagram of the structure of an ultrasonic radar chip provided in an embodiment of this application. Figure 17 As shown, the ultrasonic radar chip 1700 includes a signal path self-diagnostic circuit 1710. The specific details of the ultrasonic radar chip signal path self-diagnostic circuit 1710 can be found in the above description. Figures 2 to 16 For the sake of brevity, the description of the embodiments will not be repeated here.

[0131] In this application embodiment, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent the existence of A alone, the simultaneous existence of A and B, or the existence of B alone. A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" and similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, and c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0132] Those skilled in the art will recognize that the units and algorithm steps described in the embodiments disclosed herein can be implemented using electronic hardware, computer software, or a combination of electronic hardware and software. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0133] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0134] In the several embodiments provided in this application, any function, if implemented as a software functional unit and sold or used as an independent product, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0135] The above description is merely a specific embodiment of this application. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the protection scope of this application. The protection scope of this application should be determined by the protection scope of the claims.

Claims

1. A signal path self-diagnostic circuit for an ultrasonic radar chip, characterized in that, The circuit includes: The first test path has an input terminal electrically connected to the first output terminal of the control unit and an output terminal electrically connected to the second input terminal of the control unit. The first test path is used to receive a first test signal output by the control unit and to detect the measurement system based on the first test signal. The measurement system is an ultrasonic radar measurement system. The second test path includes a first sub-test path and a second sub-test path. The input terminal of the first sub-test path is electrically connected to the first output terminal of the control unit, and the output terminal of the first sub-test path is electrically connected to the first input terminal of the control unit. The first sub-test path is used to receive a first detection signal output by the control unit and to test the digital signal generation unit and the driver stage unit according to the first detection signal. The input terminal of the second sub-test path is electrically connected to the second output terminal of the control unit, and the output terminal of the second sub-test path is electrically connected to the second input terminal of the control unit. The second sub-test path is used to receive a second detection signal output by the control unit and to test the analog input circuit and the digital input circuit according to the second detection signal.

2. The circuit according to claim 1, characterized in that, The first sub-test path includes a digital signal generation unit, a driver stage unit, and a driver stage monitoring unit; wherein, The input terminal of the digital signal generation unit is electrically connected to the first output terminal of the control unit. The digital signal generation unit is used to receive the first detection signal output by the control unit and output a first digital signal according to the first detection signal. The input terminal of the drive stage unit is electrically connected to the first output terminal of the digital signal generation unit. The drive stage unit is used to receive the first digital signal and output a first drive output signal according to the first digital signal. The input terminal of the drive stage monitoring unit is electrically connected to the second output terminal of the drive stage unit. The drive stage monitoring unit is used to receive the first drive output signal and output a first response signal according to the first drive output signal.

3. The circuit according to claim 1, characterized in that, The second sub-test path includes an analog test unit, an analog multiplexer, an analog input circuit, a first digital multiplexer, and a digital input circuit; wherein, The input terminal of the analog test unit is electrically connected to the second output terminal of the control unit. The analog test unit is used to receive the second detection signal and output an analog test signal according to the second detection signal. The second input terminal of the analog multiplexer is electrically connected to the output terminal of the analog test unit. The analog multiplexer is used to receive the analog test signal and output a first analog input signal according to the analog test signal. The input terminal of the analog input circuit is electrically connected to the output terminal of the analog multiplexer. The analog input circuit is used to receive the first analog input signal and output a first analog output signal according to the first analog input signal. The first input terminal of the first digital multiplexer is electrically connected to the output terminal of the analog input circuit. The first digital multiplexer is used to receive the first analog output signal and output a first digital input signal according to the first analog output signal. The input terminal of the digital input circuit is electrically connected to the output terminal of the first digital multiplexer. The output terminal of the digital input circuit is electrically connected to the second input terminal of the control unit. The digital input circuit is used to receive the first digital input signal and output a second response signal according to the first digital input signal.

4. The circuit according to claim 1, characterized in that, The circuit also includes: The third test path includes a third sub-test path and a fourth sub-test path. The input terminal of the third sub-test path is electrically connected to the first output terminal of the control unit, and the output terminal of the third sub-test path is electrically connected to the third input terminal of the control unit. The third sub-test path is used to receive a third detection signal output by the control unit and to detect the digital signal generation unit based on the third detection signal. The input terminal of the fourth sub-test path is electrically connected to the third output terminal of the control unit, and the output terminal of the fourth sub-test path is electrically connected to the second input terminal of the control unit. The fourth sub-test path is used to receive a fourth detection signal output by the control unit and to detect the digital input circuit based on the fourth detection signal.

5. The circuit according to claim 4, characterized in that, The third sub-test path includes a digital signal generation unit and a signal generation monitoring unit; wherein... The input terminal of the digital signal generating unit is electrically connected to the first output terminal of the control unit. The digital signal generating unit is used to receive the third detection signal and output a second digital signal according to the third detection signal. The input terminal of the signal generating monitoring unit is electrically connected to the second output terminal of the digital signal generating unit. The output terminal of the signal generating monitoring unit is electrically connected to the third input terminal of the control unit. The signal generating monitoring unit is used to receive the second digital signal and output a third response signal according to the second digital signal.

6. The circuit according to claim 4, characterized in that, The fourth sub-test path includes a digital test unit, a first digital multiplexer, and a digital input circuit; wherein... The input terminal of the digital test unit is electrically connected to the third output terminal of the control unit. The digital test unit is used to receive the fourth detection signal and output a first digital test signal according to the fourth detection signal. The second input terminal of the first digital multiplexer is electrically connected to the output terminal of the digital test unit. The first digital multiplexer is used to receive the first digital test signal and output a second digital input signal according to the first digital test signal. The input terminal of the digital input circuit is electrically connected to the output terminal of the first digital multiplexer. The output terminal of the digital input circuit is electrically connected to the second input terminal of the control unit. The digital input circuit is used to receive the second digital input signal and output a fourth response signal according to the second digital input signal.

7. The circuit according to claim 1, characterized in that, The first test path includes a digital signal generation unit, a driver stage unit, a measurement system, an analog multiplexer, an analog input circuit, a second digital multiplexer, and a digital input circuit; wherein, The input terminal of the digital signal generation unit is electrically connected to the first output terminal of the control unit. The digital signal generation unit is used to receive the first test signal and output a third digital signal according to the first test signal. The input terminal of the drive stage unit is electrically connected to the first output terminal of the digital signal generation unit. The drive stage unit is used to receive the third digital signal and output a second drive output signal according to the third digital signal. The input terminal of the measurement system is electrically connected to the first output terminal of the drive stage unit. The measurement system is used to receive the second drive output signal and output a measurement signal according to the second drive output signal. The first input terminal of the analog multiplexer is connected to the first output terminal of the measurement system. The output terminal of the system is electrically connected. The analog multiplexer is used to receive the measurement signal and output a second analog input signal according to the measurement signal. The input terminal of the analog input circuit is electrically connected to the output terminal of the analog multiplexer. The analog input circuit is used to receive the second analog input signal and output a second analog output signal according to the second analog input signal. The first input terminal of the second digital multiplexer is electrically connected to the output terminal of the analog input circuit. The analog input circuit is used to output a third digital input signal according to the second analog output signal. The digital input circuit is used to output a fifth response signal according to the third digital input signal.

8. The circuit according to claim 1, characterized in that, The first test path includes a digital test unit, a driver stage unit, a measurement system, an analog multiplexer, an analog input circuit, a first digital multiplexer, and a digital input circuit; wherein, The digital test unit is used to output a second digital test signal based on the first test signal. The drive stage unit is used to output a second drive output signal based on the second digital test signal. The measurement system is used to output a measurement signal based on the second drive output signal. The analog multiplexer is used to output a second analog input signal based on the measurement signal. The analog input circuit is used to output a second analog output signal based on the second analog input signal. The first digital multiplexer is used to output a third digital input signal based on the second analog output signal. The input terminal of the digital input circuit is electrically connected to the output terminal of the first digital multiplexer. The output terminal of the digital input circuit is electrically connected to the second input terminal of the control unit. The digital input circuit is used to receive the third digital input signal and output a fifth response signal based on the third digital input signal.

9. The circuit according to claim 7 or 8, characterized in that, The measurement system includes a transformer and an ultrasonic transducer. The input terminal of the transformer is electrically connected to the output terminal of the drive stage unit. The first output terminal of the transformer is electrically connected to the first input terminal of the ultrasonic transducer. The first output terminal of the ultrasonic transducer is electrically connected to the second output terminal of the transformer. The ultrasonic transducer is used to receive the transformer signal output by the transformer and output an ultrasonic measurement signal to the measurement channel through the second output terminal based on the transformer signal. The ultrasonic transducer is also used to receive the ultrasonic reflection signal returned from the measurement channel through the second input terminal and output a received signal through the first output terminal based on the ultrasonic reflection signal. The second output terminal of the transformer is also electrically connected to the first input terminal of the analog multiplexer for outputting the transformer signal and the received signal to the analog multiplexer.

10. The circuit according to claim 2, characterized in that, The first sub-test path further includes a second digital multiplexer. The driver-level monitoring unit is electrically connected to the signal generation and monitoring unit through the second digital multiplexer. At this time, the driver-level monitoring unit is used to output a driver monitoring signal according to the first driver output signal. The first input terminal of the second digital multiplexer is electrically connected to the output terminal of the driver-level monitoring unit. The second digital multiplexer is used to receive the driver monitoring signal and output a first monitoring input signal according to the driver monitoring signal. The input terminal of the signal generation and monitoring unit is electrically connected to the output terminal of the second digital multiplexer. The output terminal of the signal generation and monitoring unit is electrically connected to the third input terminal of the control unit. The signal generation and monitoring unit is used to receive the first monitoring input signal and output a first response signal according to the first monitoring input signal.

11. The circuit according to claim 5, characterized in that, The third sub-test path further includes a second digital multiplexer. The digital signal generation unit is electrically connected to the signal generation and monitoring unit through the second digital multiplexer. At this time, the digital signal generation unit is used to output a second digital signal according to the third detection signal. The second input terminal of the second digital multiplexer is electrically connected to the second output terminal of the digital signal generation unit. The second digital multiplexer is used to receive the second digital signal and output a second monitoring input signal according to the second digital signal. The input terminal of the signal generation and monitoring unit is electrically connected to the output terminal of the second digital multiplexer. The output terminal of the signal generation and monitoring unit is electrically connected to the third input terminal of the control unit. The signal generation and monitoring unit is used to receive the second monitoring input signal and output a third response signal according to the second monitoring input signal.

12. The circuit according to claim 3, characterized in that, The second sub-test path further includes a digital test unit, which is located at the input of the analog test unit. In this case, the analog test unit is a digital-to-analog converter. The input terminal of the simulation test unit is electrically connected to the second output terminal of the control unit. The simulation test unit is used to receive the second detection signal and output a simulation test signal according to the second detection signal, including: The input terminal of the digital test unit is electrically connected to the third output terminal of the control unit. The digital test unit is used to receive the second detection signal and output a third digital test signal according to the second detection signal. The input terminal of the analog test unit is electrically connected to the output terminal of the digital test unit. The analog test unit is used to receive the third digital test signal and output an analog test signal according to the third digital test signal.

13. The circuit according to claim 6, 8, or 12, characterized in that, The digital test unit has the same circuit function as the digital signal generation unit.

14. The circuit according to claim 6, 8, or 12, characterized in that, The digital test unit and the digital signal generation unit share some circuit structures. The digital signal generation unit includes a first register configuration module and a first logic unit that are electrically connected in sequence. The digital test unit includes a second register configuration module and a first logic unit that are electrically connected in sequence.

15. The circuit according to claim 6, 8, or 12, characterized in that, The digital test unit is electrically connected to the digital channel simulation unit, and outputs a first digital test signal, a second digital test signal, or a third digital test signal through the digital channel simulation unit.

16. The circuit according to claim 3, characterized in that, The circuit function of the analog test unit is the same as that of the digital signal generation unit and the drive stage unit after they are electrically connected.

17. The circuit according to claim 3, characterized in that, The analog test unit shares a common circuit structure with the circuit after being electrically connected to the digital signal generation unit and the driver stage unit. The circuit after being electrically connected to the digital signal generation unit and the driver stage unit includes a first register configuration module, a first logic unit and a second logic unit connected in sequence. The analog test unit includes a third register configuration module, a first logic unit and a second logic unit connected in sequence.

18. The circuit according to claim 3, characterized in that, The simulation test unit has the same circuit function as the drive stage unit.

19. The circuit according to claim 3, characterized in that, The simulation test unit and the driver stage unit share some circuit structures, wherein the driver stage unit includes a second logic unit and the simulation test unit includes a second logic unit.

20. The circuit according to claim 3 or 12, characterized in that, The simulation test unit is electrically connected to the simulation channel simulation unit, and outputs the simulation test signal through the simulation channel simulation unit.

21. An ultrasonic radar chip, characterized in that, Includes the signal path self-diagnostic circuit as described in any one of claims 1-20.

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