Optical module
By designing a series link of redundant pads and bumps in the optical module, the problem of untimely identification of soldering quality in the optical module is solved, realizing fast and low-cost solder joint detection and reducing the defective product inflow rate.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- INNOLIGHT TECHNOLOGY (SUZHOU) LTD
- Filing Date
- 2025-05-15
- Publication Date
- 2026-05-19
AI Technical Summary
Existing technologies cannot effectively and promptly identify the chip welding quality in optical modules, leading to defective products flowing into subsequent processes, resulting in high costs and significant risks.
The design incorporates pads and bumps on the circuit board and photonic integrated chip in the optical module, forming a series link of redundant solder joints. The soldering status is checked by detecting this series link, including setting functional pads, redundant pads, functional bumps, and redundant bumps, and the soldering status is determined by the detection circuit.
This technology enables rapid and low-cost inspection of solder joint quality after chip and circuit board mounting, timely identification of soldering problems, prevention of defective products from being transferred, and reduction of the defect rate.
Smart Images
Figure CN224263439U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of optical communication technology, and more specifically, to an optical module. Background Technology
[0002] As optical module speeds increase, the requirements for optoelectronic integration also increase, and the packaging of devices has gradually changed from discrete devices to integrated packages; at the same time, the requirements for signal loss are also forcing the packages to become smaller and smaller.
[0003] In highly integrated, high-speed optical modules, optical components such as optical modulators and wavelength division multiplexers can be integrated into a single photonic integrated circuit (PIC) chip to improve integration density and achieve miniaturized packaging. Furthermore, to shorten the high-frequency path and improve high-frequency performance, the PIC can be flip-chip bonded to the edge of the printed circuit board (PCB) in a bare die configuration. Due to the need for light output from the optical port, the port portion must be suspended off the board. Therefore, during flip-chip reflow soldering, there is a risk of solder joint cracking due to factors such as chip tilting caused by misalignment of the center of gravity, warping caused by thermal stress, and stress caused by the chip's location at the edge.
[0004] Currently, after surface mount technology (SMT) is completed, soldering information can only be confirmed using X-rays, but X-rays cannot effectively identify soldering quality. Often, soldering abnormalities in the PIC are only discovered during the later stages of optical module assembly, through performance testing. At this point, scrapping the module is extremely costly, with high analysis costs and significant potential risks. Utility Model Content
[0005] The purpose of this application is to provide an optical module to solve the problem in the prior art that the chip welding quality in the optical module cannot be identified in a timely and effective manner.
[0006] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows:
[0007] This application provides an optical module, which includes a circuit board and a photonic integrated chip, wherein the photonic integrated chip is flip-chip soldered onto the circuit board; wherein...
[0008] The area where the circuit board is soldered to the photonic integrated chip is provided with multiple functional pads and multiple redundant pads. The photonic integrated chip is provided with multiple functional bumps and multiple redundant bumps. The redundant bumps are soldered to the redundant pads to form multiple redundant solder joints, and the functional bumps are soldered to the functional pads to form multiple functional solder joints.
[0009] The circuit board is also provided with a plurality of discontinuous first electrical connection lines, each of which is used to connect two adjacent redundant pads; the photonic integrated chip is also provided with a plurality of discontinuous second electrical connection lines, each of which is used to connect two adjacent redundant bumps, and the positions of the first electrical connection lines and the second electrical connection lines are complementary.
[0010] Each of the first electrical connection lines is connected to a second electrical connection line via the redundant solder joint at its end, and all the first electrical connection lines, the redundant solder joint, and the second electrical connection line are connected to form at least one series link.
[0011] Optionally, the plurality of functional bumps and the plurality of redundant bumps are arranged in an array, wherein at least two columns and / or two rows in the array are the redundant bumps;
[0012] The multiple functional pads and the multiple redundant pads are arranged in an array, and the positions of the redundant pads correspond to the redundant bumps.
[0013] Optionally, one of the first electrical connection wire and the second electrical connection wire is a horizontal electrical connection wire, and the other is a vertical electrical connection wire; or
[0014] One of the first electrical connection wires and the second electrical connection wire is a diagonal electrical connection wire, and the other is a vertical electrical connection wire or a horizontal electrical connection wire; or
[0015] Both the first electrical connection line and the second electrical connection line are oblique electrical connection lines.
[0016] Optionally, the redundant bump is disposed around the functional bump, and the redundant pad is disposed around the functional pad.
[0017] Optionally, all redundant pads are arranged in multiple detection areas, and each serial link in each detection area is configured with two detection endpoints. The two detection endpoints are the first and last pads of the serial link in the corresponding detection area, respectively, or the two detection endpoints are electrically connected to the first and last pads of the serial link in the corresponding detection area.
[0018] Optionally, each of the aforementioned serial links is configured with two detection endpoints.
[0019] Optionally, the optical module further includes a detection circuit, the serial link being electrically connected to the detection circuit, and the detection circuit being used to detect the welding status of redundant solder joints in the corresponding serial link.
[0020] Optionally, the detection circuit includes an MCU and a detection resistor. One end of the circuit after the detection resistor and the series link are connected to a power supply, and the other end is grounded. The detection port of the MCU is electrically connected to the connection point of the detection resistor and the series link to obtain the voltage level at the connection point. The MCU is configured to determine the welding status of the redundant solder joint based on the voltage level.
[0021] Optionally, the resistance of the detection resistor is 1KΩ to 10KΩ.
[0022] Optionally, the photonic integrated chip is flip-chip bonded to the circuit board near the edge of the circuit board, and one end of the photonic integrated chip with the optical port is suspended outside the edge of the circuit board; or, the circuit board is provided with a cutout, the photonic integrated chip is flip-chip bonded to the circuit board near the cutout, and one end of the photonic integrated chip with the optical port is suspended at the cutout.
[0023] The redundant bumps are located on the remaining edge regions of the photonic integrated chip, excluding the optical port side, and the redundant pads on the circuit board are opposite to the positions of the redundant bumps.
[0024] Compared with the prior art, this application has the following technical effects:
[0025] The optical module provided in this application improves the design of the circuit board's pads and chip bumps, so that after the chip and circuit board are flip-chip bonded, the redundant bumps of the chip and the redundant pads of the circuit board form a series link. After the chip and circuit board are mounted, the solder joints can be checked by detecting this series link. This detection method is convenient, fast, and low in cost. It can also promptly identify soldering problems and prevent defective products from flowing to subsequent processes, resulting in more defective products.
[0026] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description
[0027] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0028] Figure 1 This is a schematic diagram of the packaging of the circuit board and the photonic integrated chip in an optical module according to an embodiment of this application.
[0029] Figure 2 This is a schematic diagram showing the layout of the pads and the first connection line on the circuit board provided in an embodiment of this application.
[0030] Figure 3 This is a schematic diagram of the bumps and the second connection line on the photonic integrated chip provided in the embodiments of this application.
[0031] Figure 4 This is a schematic diagram of the first solder joint layout after the photonic integrated chip and the circuit board are soldered, as provided in the embodiments of this application.
[0032] Figure 5 This is a schematic diagram of a second solder joint layout after the photonic integrated chip and the circuit board are soldered, as provided in an embodiment of this application.
[0033] Figure 6 This is a schematic diagram of a third type of solder joint layout after the photonic integrated chip and the circuit board are soldered, as provided in the embodiments of this application.
[0034] Figure 7 This is a schematic diagram of a fourth solder joint layout after the photonic integrated chip and the circuit board are soldered, as provided in the embodiments of this application.
[0035] Figure 8 This is a schematic diagram of the fifth solder joint layout after the photonic integrated chip and the circuit board are soldered, as provided in the embodiments of this application.
[0036] Figure 9 This is a circuit diagram of the detection circuit provided in an embodiment of this application.
[0037] In the picture:
[0038] 1-Circuit board; 2-Knockout; 3-Photonic integrated chip; 31-Optical port; 110-Redundant pad; 120-Functional pad; 130-First electrical connection line; 210-Redundant bump; 220-Functional bump; 230-Second electrical connection line; 310-Redundant solder joint; 320-Functional solder joint. Detailed Implementation
[0039] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.
[0040] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.
[0041] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.
[0042] It should be noted that in this paper, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.
[0043] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.
[0044] Please see Figure 1 The optical module provided in one embodiment of this application includes a circuit board 1 and a photonic integrated chip 3. The photonic integrated chip 3 is flip-chip bonded to the circuit board 1 using a flip-chip process. In this embodiment, due to the light output requirements of the optical port 31 of the photonic integrated chip 3, a cutout 2 is provided on the circuit board 1 to avoid obstructing the optical port 31 of the photonic integrated chip 3. The photonic integrated chip 3 is flip-chip bonded to the circuit board 1 near the cutout 2, and one end of the photonic integrated chip 3 with the optical port 31 is suspended at the cutout 2 (the left side of the photonic integrated chip 3 in the figure). This facilitates the coupling of the optical port 31 with the optical fiber, meets the light output requirements, and results in higher light output quality and better performance of the optical module.
[0045] In some other embodiments, the photonic integrated chip 3 can also be flip-chip soldered onto the circuit board 1 near the edge of the circuit board 1, with one end of the photonic integrated chip 3 having the optical port 31 suspended outside the edge of the circuit board 1. In this way, there is no need to provide a cutout 2 on the circuit board 1 to avoid the optical port 31.
[0046] However, suspending the photonic integrated chip outside the board increases the risk of solder joint cracking during flip-chip reflow soldering. Furthermore, the soldering quality cannot be effectively assessed after soldering is complete.
[0047] Therefore, the optical module provided in this application improves the design of the solder pads and chip bumps on the circuit board. After the chip is flip-chip bonded to the circuit board, the redundant bumps on the chip and the redundant solder pads on the circuit board form a series link. After the chip and circuit board are mounted, the solder joint condition can be checked by inspecting this series link. This design is convenient for inspection, low in cost, and can promptly identify chip soldering problems, thereby preventing defective products from flowing to subsequent processes and causing more waste.
[0048] For details, please refer to Figures 2-4 In one embodiment of this application, an optical module is provided, in which the area where the circuit board and the photonic integrated chip are soldered is provided with a plurality of functional pads 120 and a plurality of redundant pads 110. The photonic integrated chip is provided with a plurality of functional bumps 220 and a plurality of redundant bumps 210. The redundant bumps 210 and the redundant pads 110 are soldered to each other to form a plurality of redundant solder points 310. The functional bumps 220 and the functional pads 120 are soldered to each other to form a plurality of functional solder points 320.
[0049] The circuit board also features multiple discontinuous first electrical connection lines 130, each connecting two adjacent redundant pads 110. The photonic integrated chip also features multiple discontinuous second electrical connection lines 230, each connecting adjacent redundant bumps 210. The positions of the first and second electrical connection lines 130 are complementary. Each first electrical connection line 130 is connected to a second electrical connection line 230 via a redundant solder joint 310 at its end. All first electrical connection lines 130, redundant solder joints 310, and second electrical connection lines 230 form at least one series link.
[0050] In this application, after the circuit board is mounted on the photonic integrated chip, the redundant pads 110 of the circuit board and all the redundant bumps 210 of the photonic integrated chip form at least one series link through the first electrical connection line 130, the redundant solder joints 310, and the second electrical connection line 230. If a solder joint in this series link cracks, it is equivalent to an open circuit in the series link, and the equivalent resistance of the series link will increase sharply. Therefore, by detecting the equivalent resistance of the series link, it is possible to determine whether a solder joint crack has occurred in that link, thereby achieving quality inspection of all solder joints in the series link.
[0051] In this embodiment, the photonic integrated chip is flip-chip soldered onto the circuit board near the cutout, with one end of the photonic integrated chip having an optical port suspended above the cutout. Redundant bumps 210 are located on the remaining edge areas of the photonic integrated chip, excluding the side with the optical port. Correspondingly, redundant pads 110 on the circuit board are located on the remaining edge areas of the soldering area, excluding the area adjacent to the cutout, opposite to the redundant bumps 210 on the photonic integrated chip, to form multiple redundant solder joints 310, thereby forming a series link in the edge area.
[0052] Because the stress is greatest at the solder edges during flip-chip soldering using the above method, the edge solder joints are the first to be affected during flip-chip reflow soldering of the photonic integrated chip. Therefore, if the solder joints in the edge area are fine, the functional solder joints 320 in the middle area are usually also fine. Therefore, this application places redundant bumps 210 and redundant pads 110 in the edge area. By detecting the soldering condition of the redundant solder joints 310 located in the edge area, the soldering quality between the photonic integrated chip and the circuit board is checked without affecting the working performance of the photonic integrated chip.
[0053] It should be noted that you should refer to [link / reference]. Figure 2 , Figure 2 The diagram shows a schematic of the pads on a PCB. The pads within the dashed border at the edge are redundant pads 110, while the remaining pads within the dashed border in the middle are functional pads 120. Functional pads 120 are those that, after being soldered to the photonic integrated chip, need to perform corresponding functions, such as signal pads, ground pads, and power pads. Redundant pads 110 are those that, after being soldered to the photonic integrated chip, do not need to perform any functions. These redundant pads 110 can serve as expansion pads. For example, when the photonic integrated chip needs to add a certain function, the number of functional pads 120 needs to be increased. In this case, some pads from the redundant pads 110 can be selected as functional pads 120. Furthermore, the redundant pads 110 provide support and protection for the functional pads 120.
[0054] In this embodiment, multiple functional bumps and multiple redundant bumps are arranged in an array, with at least two columns and / or two rows in the array being redundant bumps; multiple functional pads and multiple redundant pads are arranged in an array, with the position of the redundant pads corresponding to the redundant bumps.
[0055] For details, please refer to Figure 2 The pad layout is shown for ease of demonstration. Figure 2 The example shown is a 10x10 array of pads. Of course, in practical applications, the appropriate number of pads can be selected according to the chip requirements. Figure 2Taking the upper edge near the cutout 2 as an example, the pads on the remaining edges are designated as redundant pads 110. For instance, the left, lower, and right portions of all pads are used as redundant pads 110. Thus, by inspecting the soldering status of the redundant solder points 310 located in the edge region, the soldering quality between the photonic integrated chip and the circuit board can be quickly checked without affecting the working performance of the photonic integrated chip.
[0056] In other embodiments, the position and number of redundant pads 110 can be adjusted according to actual requirements. For example, only the left portion of all pads can be used as redundant pads 110, and the remaining pads can be used as functional pads 120.
[0057] Similarly, bumps on photonic integrated chips can also be divided into functional bumps 220 and redundant bumps 210. Similar to pads on a circuit board, redundant bumps 210 can generally be placed around the functional bumps 220 and correspond one-to-one with redundant pads 110. Of course, redundant pads 110 and redundant bumps 210 can also be placed in other locations.
[0058] It needs to be clarified that during the actual soldering process, redundant bumps 210 are soldered to redundant pads 110, and functional bumps 220 are soldered to functional pads 120. Therefore, the number of redundant bumps 210 and redundant pads 110 are the same and their positions are matched, so that during soldering, each redundant bump 210 is soldered to one redundant pad 110 to form a redundant solder joint 310; each functional bump 220 is soldered to one functional pad 120 to form a functional solder joint 320, that is, there is also a one-to-one soldering between functional bumps 220 and functional pads 120.
[0059] In theory, the number of bumps on a photonic integrated chip needs to be less than or equal to the number of pads on the circuit board. For example, when the number of pads on the circuit board is 10*10, the number of bumps on the photonic integrated chip can be 10*10. Of course, it is also possible to accommodate photonic integrated chips with a smaller number of bumps, such as photonic integrated chips with 9*9 pads. In this case, the pads on the circuit board opposite to the redundant bumps can be set as redundant pads.
[0060] In this application, each first electrical connection line 130 is used to connect two adjacent redundant pads 110, and each second electrical connection line 230 is used to connect two adjacent redundant bumps 210. Here, the two adjacent redundant bumps 210 or the two adjacent redundant pads 110 can be horizontally adjacent, vertically adjacent, or diagonally adjacent. Figure 2 The redundant pads a, b, c, and d shown are all horizontally adjacent to each other, vertically adjacent to each other, and diagonally adjacent to each other.
[0061] Furthermore, if three consecutive redundant bumps 210 are interconnected, the redundant solder joint 310 formed by soldering the middle redundant bump 210 to the corresponding redundant pad 110 will be short-circuited. After soldering, the soldering quality of this redundant solder joint 310 cannot be inspected. Therefore, even if this redundant solder joint 310 cracks, the entire series link cannot achieve a high-resistance state, making it impossible to inspect the soldering quality of the redundant solder joint 310. This may result in some defective products being missed, causing them to flow into the next process.
[0062] Therefore, in order to detect the quality of each solder joint, the first electrical connection lines 130 are intermittent, and the second electrical connection lines 230 are also intermittent. That is, the first electrical connection lines 130 are not connected to each other, and the second electrical connection lines 230 are not connected to each other. Therefore, each redundant pad 110 is connected to at most one first electrical connection line 130, and each redundant bump 210 is connected to at most one second electrical connection line 230. Moreover, the positions of the first electrical connection lines 130 and the second electrical connection lines 230 are complementary.
[0063] In this application, the positions of the first electrical connection line 130 and the second electrical connection line 230 are complementary, meaning that after the circuit board and the photonic integrated chip are soldered, the first electrical connection line 130 and the second electrical connection line 230 do not overlap, and the first electrical connection line 130 and the second electrical connection line 230 can be connected into a series link through corresponding redundant solder joints 310. Two adjacent first electrical connection lines 130 can be connected into a series link through the middle second electrical connection line 230 and the corresponding two redundant solder joints 310.
[0064] For example, Figure 2 As shown, when redundant pad b and redundant pad d are connected via the first electrical connection line 130, the redundant bump D corresponding to redundant pad d and the redundant bump C corresponding to redundant pad c on the redundant bump 210 can be connected via the second electrical connection line 230. Simultaneously, the redundant bump A corresponding to redundant pad a and the redundant bump B corresponding to redundant pad b can also be connected via the second electrical connection line 230. Thus, after the circuit board is soldered to the photonic integrated chip, the redundant pads a, b, c, and the several redundant solder points 310 corresponding to redundant pad d can be connected in series via the first electrical connection line 130 and the second electrical connection line 230.
[0065] Please continue to refer to this. Figure 2-4In this embodiment, all redundant bumps 210 are arranged in multiple detection areas, including a left area, a bottom area, and a right area, corresponding to the left, bottom, and right portions of the aforementioned chip bumps, respectively. The left and right areas each include two columns of redundant bumps 210, and the bottom area includes two rows of redundant bumps 210. The positions of the redundant pads 110 on the circuit board are opposite to the redundant bumps 210, so as to be soldered to the corresponding redundant bumps 210.
[0066] In this embodiment, one type of the first electrical connection line 130 and the second electrical connection line 230 is a horizontal electrical connection line, and the other is a vertical electrical connection line. Taking the vertical electrical connection line 130 on the circuit board as an example, the first electrical connection line 130 connects two vertically adjacent redundant pads 110. The second electrical connection line 230 on the photonic integrated chip is a horizontal electrical connection line, connecting two horizontally adjacent redundant bumps 210. The first electrical connection line 130 and the second electrical connection line 230 are arranged in a complementary manner. Thus, when the redundant pads 110 and redundant bumps 210 are soldered one-to-one, the resulting redundant solder joints 310 and series links are as follows... Figure 4 As shown, two vertically adjacent redundant solder joints 310 are connected by a first electrical connection line 130, and two horizontally adjacent redundant solder joints 310 are connected by a second electrical connection line 230, forming a series link that is similar to a "bow" shaped bend.
[0067] In this embodiment, all redundant pads are arranged in multiple detection areas, and each serial link in each detection area is configured with two detection endpoints. The two detection endpoints are the first and last pads of the serial link in the corresponding detection area, respectively, or the two detection endpoints are electrically connected to the first and last pads of the serial link in the corresponding detection area.
[0068] For details, please refer to Figure 4 The redundant bumps 210 in each region are soldered to the corresponding redundant pads 110 to form redundant solder joints 310, which are then connected to form a series link through the corresponding first electrical connection line 130 and second electrical connection line 230. The first and last pads of each series link are configured as two detection endpoints. For example... Figure 4In this diagram, all solder joints are divided into three regions: Y1 on the left, Y2 at the bottom, and Y3 on the right. The first pad a and the last pad f of the serial link L1 in region Y1 are designated as detection endpoints X1 and X3, respectively. Similarly, the first pad f and the last pad g of the serial link L2 in region Y2 are designated as detection endpoints X3 and X4, respectively. Finally, the first pad e and the last pad g of the serial link L3 in region Y3 are designated as detection endpoints X2 and X4, respectively. Here, the first and last pads are used for ease of description, and their positions can be interchanged. In other embodiments, the detection endpoints can also be additional pads on the circuit board, electrically connected to the first and last pads at both ends of each serial link.
[0069] In one implementation, in this embodiment, the redundant solder joints 310 in regions Y1, Y2, and Y3 are also connected in a large series link via the first electrical connection line 130 and the second electrical connection line 230. This series link has detection endpoints X1 and X2. When inspecting solder joint quality, all solder joints can be checked for defects using detection endpoints X1 and X2. If the soldering is good, the test passes in one go. If defects are found, each region is then inspected separately to further determine if defects exist in each region. Specifically, region Y1 can be inspected using detection endpoints X1 and X3, region Y2 using detection endpoints X3 and X4, and region Y3 using detection endpoints X4 and X2. Therefore, when a defective solder joint is identified, different regions can be inspected using different combinations of detection endpoints, allowing for rapid location of the problem area and thus achieving solder joint quality inspection. Once a crack is found in a solder joint within a certain area, the cracked solder joint can be further identified through methods such as cross-sectioning.
[0070] This embodiment can perform initial screening by testing all redundant solder joints 310 in one go, which can effectively improve the screening efficiency of defective products. For products with soldering defects, further regional inspection is carried out to confirm the location of the solder joint with defects, and then further analyze the cause of the soldering defects. Regional inspection helps to accurately analyze the location of soldering defects, thereby improving the efficiency of defect cause analysis, so as to make timely improvements and reduce the defect rate.
[0071] Please refer to Figure 5 As a second implementation, in this embodiment, one of the first electrical connection line 130 and the second electrical connection line 230 is an oblique electrical connection line, and the other is a vertical or horizontal electrical connection line.
[0072] Figure 5The example illustrates the case where redundant solder joints 310 are two rows of solder joints in the left region. In this embodiment, the first electrical connection line 130 on the circuit board is a diagonal electrical connection line, and the second electrical connection line 230 on the photonic integrated chip is a horizontal electrical connection line. The first electrical connection line 130 and the second electrical connection line 230 are arranged in a complementary manner, so that when the redundant pads 110 and redundant bumps 210 are soldered one-to-one, all redundant solder joints 310 will form a series link. In this embodiment, the first pad b in the region is used as the starting detection endpoint X1, and the last pad f is used as the ending detection endpoint X2. By detecting the equivalent resistance between endpoints X1 and X2, it is possible to determine whether there is cracking in the two rows of solder joints.
[0073] Please refer to Figure 6 As a third implementation, in this embodiment, both the first electrical connection line 130 and the second electrical connection line 230 are oblique electrical connection lines.
[0074] Figure 6 The example shows two rows of redundant solder joints 310 in the left-hand region. In this embodiment, the first electrical connection line 130 on the circuit board and the second electrical connection line 230 on the photonic integrated chip are used as examples. The two oblique electrical connection lines intersect, and the first electrical connection line 130 and the second electrical connection line 230 are arranged in a complementary manner, meaning their tilt directions are opposite. Thus, when the redundant pads 110 and redundant bumps 210 are soldered one-to-one, two series links are formed. One series link uses its first pad a as the starting detection endpoint X1 and its last pad h as the ending detection endpoint X2; the other series link uses its first pad b as the starting detection endpoint X3 and its last pad f as the ending detection endpoint X4. By detecting the equivalent resistance between detection endpoints X1 and X2, and between detection endpoints X3 and X4, it is possible to determine whether the solder joints of the two series links are cracked.
[0075] Please refer to Figure 7 As a fourth implementation, in this embodiment, both the first electrical connection line 130 and the second electrical connection line 230 are horizontal or vertical electrical connection lines.
[0076] Specifically, Figure 7The example shows the case where redundant solder joints 310 are arranged in two columns on the left. In this embodiment, the first electrical connection line 130 on the circuit board and the second electrical connection line 230 on the photonic integrated chip are both vertical electrical connection lines, and the first electrical connection line 130 and the second electrical connection line 230 are arranged in a complementary manner. Thus, when the redundant pads 110 and redundant bumps 210 are soldered one-to-one, two series links are formed. One series link uses its first pad a as the starting detection endpoint X1 and its last pad f as the ending detection endpoint X2; the other series link uses its first pad b as the starting detection endpoint X3 and its last pad h as the ending detection endpoint X4. By detecting the equivalent resistance between detection endpoints X1 and X2, and by detecting the equivalent resistance between detection endpoints X3 and X4, it is possible to determine whether there is cracking in the two columns of solder joints.
[0077] When the number of rows or columns of redundant solder joint 310 is greater than 2, such as Figure 8 As shown, the three columns of pads in the left area are used as redundant pads 110 as an example. In this embodiment, for ease of detection, both the first electrical connection line 130 and the second electrical connection line 230 are horizontal or vertical electrical connection lines, and the number of series links is equal to the number of rows or columns of the redundant bumps 210. Of course, in some other embodiments, a combination of diagonal electrical connection lines and horizontal or vertical electrical connection lines can also be used to implement series links, or a combination of horizontal and vertical electrical connection lines can be used to implement series links.
[0078] Taking the first electrical connection line 130 on the circuit board and the second electrical connection line 230 on the photonic integrated chip as examples, both being vertical electrical connection lines, the first electrical connection line 130 and the second electrical connection line 230 are arranged in a complementary manner. Thus, when the redundant pads 110 and redundant bumps 210 are soldered one-to-one, three series links are formed. The first series link uses its first pad a as the starting detection endpoint X1 and its last pad f as the ending detection endpoint X2; the second series link uses its first pad b as the starting detection endpoint X3 and its last pad h as the ending detection endpoint X4; and the third series link uses its first pad i as the starting detection endpoint X5 and its last pad j as the ending detection endpoint X6. By detecting the equivalent resistance between detection endpoints X1 and X2, X3 and X4, and X5 and X6, the presence of cracks in the three rows of solder joints can be determined.
[0079] Therefore, this application achieves rapid detection of solder joint cracks by setting complementary first electrical connection line 130 and second electrical connection line 230, without the need for complex equipment and with simpler operation.
[0080] The optical module provided in another embodiment of this application differs from the embodiments described above in that, based on the implementation methods of the embodiments described above, the circuit board of the optical module in this embodiment is further provided with a detection circuit, which is used to detect the welding status of redundant solder joints 310 in the corresponding serial link.
[0081] Please see Figure 9 The detection circuit includes an MCU and a detection resistor R1. One end of the circuit formed by the detection resistor R1 and the series link is connected to a power supply, and the other end is grounded. The MCU's detection port is electrically connected to the connection point of the detection resistor R1 and the series link to obtain the voltage level at the connection point. Unlike the previous embodiments, in this embodiment, the MCU is configured to determine the welding status of the redundant solder joint 310 based on the obtained voltage level.
[0082] The sensing resistor R1 can be used as either a pull-up resistor or a pull-down resistor. For example... Figure 9 As shown, in this embodiment, the sensing resistor R1 is used as a pull-up resistor, and the equivalent resistance of the series link is R2. The resistance value of the sensing resistor is in the range of 1KΩ to 10KΩ. In some other embodiments, the positions of the sensing resistor R1 and the equivalent resistance R2 can be interchanged, that is, the sensing resistor can be used as a pull-down resistor.
[0083] like Figure 9 As shown in this embodiment, when performing solder joint detection, the power supply VCC can be 3.3V, and the detection resistor R1 and the equivalent resistance of the series link, R2, form a voltage divider circuit. When no solder joint cracking occurs, the resistance value of the equivalent resistance R2 of the series link is relatively small. At this time, after the voltage division effect of R1 and R2, the level received by the MCU detection port is relatively low, for example, it may be close to 0V. However, when solder joint cracking occurs, the resistance value of the equivalent resistance R2 of the series link changes abruptly, possibly much greater than 10KΩ. At this time, the level received by the MCU detection port is relatively large, for example, it may be close to 3.3V. By measuring the level detected by the MCU detection port, it is possible to determine whether a fault such as solder joint cracking has occurred. This detection circuit has a simple structure, low cost, and can quickly check the soldering status of solder joints.
[0084] In summary, this application provides an optical module that improves the design of the circuit board pads and chip bumps in the optical module. After the chip and circuit board are flip-chip bonded, the redundant bumps of the chip and the redundant pads of the circuit board form a series link. After the chip and circuit board are mounted, the solder joints can be checked by detecting this series link. This detection method is convenient, fast, and low in cost. It can also promptly identify soldering problems and prevent defective products from flowing to subsequent processes, causing more waste.
[0085] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.
[0086] It will be apparent to those skilled in the art that this application is not limited to the details of the exemplary embodiments described above, and that this application can be implemented in other specific forms without departing from the spirit or essential characteristics of this application. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this application is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this application. No reference numerals in the claims should be construed as limiting the scope of the claims.
Claims
1. An optical module, characterized in that, The optical module includes a circuit board and a photonic integrated chip, wherein the photonic integrated chip is flip-chip soldered onto the circuit board; wherein... The area where the circuit board is soldered to the photonic integrated chip is provided with multiple functional pads and multiple redundant pads. The photonic integrated chip is provided with multiple functional bumps and multiple redundant bumps. The redundant bumps are soldered to the redundant pads to form multiple redundant solder joints, and the functional bumps are soldered to the functional pads to form multiple functional solder joints. The circuit board is also provided with a plurality of discontinuous first electrical connection lines, each of which is used to connect two adjacent redundant pads; the photonic integrated chip is also provided with a plurality of discontinuous second electrical connection lines, each of which is used to connect two adjacent redundant bumps, and the positions of the first electrical connection lines and the second electrical connection lines are complementary. Each of the first electrical connection lines is connected to a second electrical connection line via the redundant solder joint at its end, and all the first electrical connection lines, the redundant solder joint, and the second electrical connection line are connected to form at least one series link.
2. The optical module as described in claim 1, characterized in that, The plurality of functional bumps and the plurality of redundant bumps are arranged in an array, wherein at least two columns and / or two rows in the array are the redundant bumps. The multiple functional pads and the multiple redundant pads are arranged in an array, and the positions of the redundant pads correspond to the redundant bumps.
3. The optical module as described in claim 1, characterized in that, One of the first electrical connection wire and the second electrical connection wire is a horizontal electrical connection wire, and the other is a vertical electrical connection wire; or One of the first electrical connection wires and the second electrical connection wire is a diagonal electrical connection wire, and the other is a vertical electrical connection wire or a horizontal electrical connection wire; or Both the first electrical connection line and the second electrical connection line are oblique electrical connection lines.
4. The optical module as described in claim 1, characterized in that, The redundant bumps are located around the functional bumps, and the redundant pads are located around the functional pads.
5. The optical module as described in claim 1, characterized in that, All redundant pads are arranged in multiple testing areas, and each serial link in each testing area is configured with two testing endpoints. The two testing endpoints are the first and last pads of the serial link in the corresponding testing area, respectively, or the two testing endpoints are electrically connected to the first and last pads of the serial link in the corresponding testing area.
6. The optical module as described in claim 1, characterized in that, Each of the aforementioned serial links is configured with two detection endpoints.
7. The optical module as described in claim 1, characterized in that, The optical module also includes a detection circuit, and the serial link is electrically connected to the detection circuit. The detection circuit is used to detect the welding status of redundant solder points in the corresponding serial link.
8. The optical module as described in claim 7, characterized in that, The detection circuit includes an MCU and a detection resistor. One end of the circuit formed by the detection resistor and the series link is connected to a power supply, and the other end is grounded. The detection port of the MCU is electrically connected to the connection point of the detection resistor and the series link to obtain the voltage level at the connection point. The MCU is configured to determine the welding status of the redundant solder joints based on the voltage level.
9. The optical module as described in claim 8, characterized in that, The resistance of the detection resistor is 1KΩ to 10KΩ.
10. The optical module as described in claim 1, characterized in that, The photonic integrated chip is flip-chip bonded to the circuit board near the edge of the circuit board, and one end of the photonic integrated chip with an optical port is suspended outside the edge of the circuit board; or, the circuit board is provided with a cutout, the photonic integrated chip is flip-chip bonded to the circuit board near the cutout, and one end of the photonic integrated chip with an optical port is suspended at the cutout. The redundant bumps are located on the remaining edge regions of the photonic integrated chip, excluding the optical port side, and the redundant pads on the circuit board are opposite to the positions of the redundant bumps.