Semiconductor device

Abstract

Memory cells in a memory array in an interconnect layer of a semiconductor device may be distributed over a plurality of vertically disposed layers in the interconnect layer. As such, a three-dimensional array of memory cells in the interconnect layer of the semiconductor device can be implemented, which provides a greater amount of lateral area for the memory cells in each metallization layer. According to the invention, high-density memory units can be realized in the memory array without sacrificing the size of the memory units and / or the distance between the memory units, so that the memory units can be operated more stably and have longer operation life.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device. Background Technology

[0002] Many types of semiconductor devices include memory cells. Some types of semiconductor devices include memory cells in interconnect layers (e.g., back-end regions). Memory cells in the interconnect layers of a semiconductor device can support device functions included in the device layer of the semiconductor device, such as on-board memory and cache for logic devices in the device layer. Utility Model Content

[0003] The embodiments disclosed herein provide a semiconductor device. The semiconductor device includes a semiconductor substrate, an interconnect layer, and a memory array. The interconnect layer is located above the semiconductor substrate. The memory array is located within the interconnect layer and includes a first memory layer and a second memory layer. The first memory layer includes a first plurality of memory structures, each of the first plurality of memory structures being located at a first vertical height within the interconnect layer. The second memory layer includes a second plurality of memory structures, each of the second plurality of memory structures being located at a second vertical height within the interconnect layer. The first vertical height and the second vertical height are different vertical heights.

[0004] The embodiments disclosed herein provide a semiconductor device. The semiconductor device includes a semiconductor substrate, an interconnect layer, and a memory array. The interconnect layer is located above the semiconductor substrate and includes a multilayer interconnect structure and a multilayer metallization structure that alternates perpendicularly to the multilayer interconnect structure. The memory array is located in the interconnect layer and includes a first memory layer and a second memory layer. The first memory layer includes a first plurality of memory structures, each of which is located in a first interconnect structure of the multilayer interconnect structure. The second memory layer includes a second plurality of memory structures, each of which is located in a second interconnect structure of the multilayer interconnect structure. The multilayer metallization structure is perpendicularly located between the first interconnect structure and the second interconnect structure.

[0005] The embodiments disclosed herein provide a semiconductor device. The semiconductor device includes a substrate comprising an integrated circuit device, wherein the integrated circuit device is located in or above the substrate. The semiconductor device further includes an interconnect layer located above the substrate, and the interconnect layer includes multiple vertically conductive layers. The semiconductor device also includes a first plurality of memory structures and a second plurality of memory structures located in the vertically conductive layers, the first plurality of memory structures having a first height, and the second plurality of memory structures having a second height, wherein the second height is greater than the first height. Attached Figure Description

[0006] The various embodiments disclosed herein can be best understood by reading in conjunction with the accompanying drawings through the following detailed description. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0007] Figures 1A to 1D This is a schematic diagram of an exemplary semiconductor device described in this disclosure;

[0008] Figures 2A to 2I This is a schematic diagram illustrating an exemplary embodiment of the semiconductor device described in this disclosure;

[0009] Figures 3A to 3E This is a schematic diagram of an exemplary semiconductor device described in this disclosure;

[0010] Figure 4 This is a schematic diagram of an exemplary semiconductor device described in this disclosure;

[0011] Figure 5 This is a schematic diagram of an exemplary semiconductor device described in this disclosure;

[0012] Figure 6 This is a schematic diagram of an exemplary semiconductor device described in this disclosure;

[0013] Figures 7A to 7C This is a schematic diagram of an exemplary semiconductor device described in this disclosure;

[0014] Figures 8A to 8C This is a schematic diagram of an exemplary semiconductor device described in this disclosure;

[0015] Figure 9 This is a schematic diagram of the exemplary memory structure described in this disclosure; and

[0016] Figure 10 This is a flowchart of an exemplary process related to the formation of the semiconductor device described in this disclosure.

[0017] [Symbol Explanation]

[0018] 100, 300, 400, 500, 600, 700, 800: Semiconductor devices

[0019] 102, 302, 402, 502, 602, 702, 802: Memory array

[0020] 104, 304, 404, 504, 604, 704, 804: Interconnection layer

[0021] 106, 106a, 106b, 306, 306a, 306b, 306c, 306d, 406, 406a, 406b, 506, 506a, 506b, 506c, 506d, 606, 606a, 606b, 606c, 606d, 706, 706a, 706b, 806, 806a, 806b: Memory Structure

[0022] 108, 308, 708, 808: Device layer

[0023] 110,310,710,810:Substrate

[0024] 112, 312, 712, 812: Integrated circuit devices

[0025] 114,314,714,814,904: Dielectric layer

[0026] 116, 316, 716: Contacts

[0027] 118,318,718,818: ILD layer / interlayer dielectric layer

[0028] 120, 320, 720, 820: ESL / Etching Stop Layer

[0029] 122a,122b,122c,122d,124a,124b,124c,322a,322b,322c,322d,322e,322f,324a,324b,324c,324d,324e,722a,722b,722c,722d,724a,724b,724c,822a,822b,822c,822d,824a,824b,824c: Layer

[0030] 126,326,726,726a,726b,826: Metallized structures

[0031] 128, 128a, 128b, 328, 328a, 328b, 728, 828, 828a, 828b: Interconnection structure

[0032] 130a, 130b, 330a, 330b, 330c, 330d, 730a, 730b, 830a, 830b: Memory Layer

[0033] 200,900: Implementation Methods

[0034] 332a, 332b, 332c, 332d, 332e, 332f, 332g, 332h: Overlapping regions

[0035] 902: Memory Structure

[0036] 906: Bottom Electrode

[0037] 908: Top Electrode

[0038] 910: Data Storage Layer

[0039] 1000: Process

[0040] 1010, 1020, 1030, 1040, 1050: Steps

[0041] AA,BB,CC,DD,EE,FF,GG,HH,II,JJ,KK: Profile lines

[0042] D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13: Dimensions

[0043] x, y, z: Direction Detailed Implementation

[0044] The following disclosure provides many different embodiments or examples of configurations to achieve different features of the subject matter of this disclosure. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely exemplary and not intended to limit this disclosure. For example, as described later, forming a first feature over a second feature may include embodiments where the first and second features are in direct contact, or embodiments where an additional feature is formed between the first and second features such that the first and second features are not in direct contact. Additionally, reference numerals and / or letters may be repeated in various examples of the drawings. Such repetition of reference numerals and / or letters is for simplicity and clarity and is not in itself intended to limit the relationship between the various embodiments and / or configurations described.

[0045] Furthermore, for ease of description, spatially related terms such as “below,” “under,” “lower,” “above,” and “upper” may be used in this disclosure to describe an element or feature relative to another element or feature as shown in the figures. In addition to the orientations depicted in the figures, the spatially related terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatially relative descriptions used in this disclosure may be interpreted similarly and accordingly.

[0046] One of the primary goals of the semiconductor industry is to gradually shrink the size of components in semiconductor devices. For example, advancements in semiconductor manufacturing process nodes allow for smaller components such as transistors and memory cells, leading to greater component density, lower power consumption, and / or faster operation. Shrinking the size of memory cells in a semiconductor device enables greater density of memory cells in the memory array. However, shrinking the size of memory cells may reduce their performance in one or more ways. For instance, shrinking the size of memory cells may lead to unstable operation, making them more susceptible to bit errors and data corruption. As another example, shrinking the size of multiple layers of memory cells may reduce the robustness and lifespan of these layers, making them more prone to failure and causing accelerated wear of the memory cells.

[0047] In some embodiments described in this disclosure, memory cells in a memory array within the interconnect layer of a semiconductor device can be distributed across multiple vertically disposed layers within the interconnect layer. For example, a first subset of the memory cells in the memory array can be contained within a first conductive structure layer of the interconnect layer, while a second subset of the memory cells can be contained within a second conductive structure layer of the interconnect layer. This allows for a three-dimensional array of memory cells within the interconnect layer of the semiconductor device, providing a larger lateral area for the memory cells in each metallization layer. This enables the realization of high-density memory cells in the memory array without sacrificing the size of the memory cells and / or the spacing between them, resulting in more stable operation and a longer operating life for the memory cells.

[0048] Figures 1A to 1D This is a schematic diagram of an exemplary semiconductor device 100 as described in this disclosure. The semiconductor device 100 may include a system-on-chip (SoC) device, logic elements (such as a central processing unit (CPU) or graphics processing unit (GPU)), memory devices (such as high bandwidth memory (HBM) devices), and / or another type of semiconductor device.

[0049] Figure 1A A top view of the semiconductor device 100 is shown. (As shown) Figure 1AAs shown, the semiconductor device 100 includes a memory array 102 in an interconnect layer 104 of the semiconductor device 100. The interconnect layer 104 may be referred to as a back end region or back end of line (BEOL) region of the semiconductor device 100, and may include conductive structures configured to transmit signals and / or provide power distribution throughout the semiconductor device 100.

[0050] Memory array 102 includes a plurality of memory structures 106 arranged in an array. The memory structures 106 of memory array 102 may include one or more types of memory structures configured to selectively change states corresponding to different logic values. For example, memory structures 106 may include dynamic random access memory (DRAM) structures, magnetic random access memory (MRAM) structures, resistive random access memory (RRAM) structures, phase-change RAM (PCRAM) structures, ferroelectric RAM (FeRAM) structures, floating gate memory structures (e.g., flash memory structures), and / or another type of memory structure. Memory structures 106 may store logic values ​​based on the resistance state of memory structure 106, the charge accumulation state of memory structure 106, the magnetic state of memory structure 106, the polarity of the memory, and / or another property of memory structure 106.

[0051] In some embodiments, memory structure 106 corresponds to a portion of the memory cells of memory array 102. For example, memory structure 106 may include a magnetic tunnel junction (MTJ) of an MRAM cell, a ferroelectric tunnel junction (FTJ) of an FeRAM cell, and / or a capacitor structure of a DRAM cell. In these embodiments, memory structure 106 may be electrically coupled to transistor structures (e.g., back-end transistors in interconnect layer 104, front-end transistors in the device layer of the semiconductor device) that enable memory structure 106 to be selected. In some embodiments, memory structure 106 corresponds to an access or selection mechanism integrated into the memory cells within memory structure 106. For example, memory structure 106 may include a floating gate transistor or a ferroelectric field-effect transistor (FeFET).

[0052] As described in this disclosure, since the memory structures 106 are disposed in three dimensions within the interconnect layer 104 of the semiconductor device 100, including the x, y, and z directions of the interconnect layer 104, the memory array 102 is configured in three dimensions. Furthermore, as described in this disclosure, the memory structures 106 are distributed across vertical layers spanning multiple conductive structures within the interconnect layer 104. For example, a first plurality of memory structures 106a of the memory array 102 may be contained within a first conductive layer of the interconnect layer 104, and a second plurality of memory structures 106b of the memory array 102 may be contained within a second conductive layer. The three-dimensional distribution of the memory structures 106 within the interconnect layer 104 allows the memory structures 106 to have a larger size than when configured as a two-dimensional array, and / or allows for greater lateral spacing between the memory structures 106 (e.g., only in the x and y directions), while achieving a similar or greater memory structure density in the memory array 102.

[0053] For example, the y-direction spacing between adjacent memory structures 106a in the first conductive structure of interconnect layer 104 (in Figure 1A (denoted by dimension D1), and / or the x-direction spacing between adjacent memory structures 106a in the first conductive structure of interconnect layer 104 (in the ...). Figure 1A (denoted by dimension D2) can be four times larger than the spacing between adjacent memory structures in a two-dimensional distributed memory structure of each semiconductor device in the interconnect layer. In some embodiments, the x-direction spacing and / or y-direction spacing between adjacent memory structures 106a is more than four times larger than the spacing between adjacent memory structures in a two-dimensional distributed memory structure in the interconnect layer of the memory structure.

[0054] As another example, the y-direction spacing between adjacent memory structures 106b in the second conductive structure of interconnect layer 104 (in... Figure 1A (denoted by dimension D3), and / or the x-direction spacing between adjacent memory structures 106b in the second conductive structure of interconnect layer 104 (in the ...). Figure 1A (denoted by dimension D4) can be four times larger than the spacing between adjacent memory structures in a two-dimensional distributed memory structure of each semiconductor device in the interconnect layer. In some embodiments, the x-direction spacing and / or y-direction spacing between adjacent memory structures 106b is more than four times larger than the spacing between adjacent memory structures in a two-dimensionally arranged memory structure in the interconnect layer of the memory structure.

[0055] As another example, the z-direction spacing between memory structure 106a in the first conductive layer of interconnect layer 104 and memory structure 106b in the second conductive layer of interconnect layer 104 can be four times larger than the spacing between adjacent memory structures in a two-dimensionally distributed memory structure in the interconnect layer of a semiconductor device. In some embodiments, the z-direction spacing between memory structure 106a and memory structure 106b is more than four times larger than the spacing between adjacent memory structures in a two-dimensionally distributed memory structure in the interconnect layer of the memory structure.

[0056] As another example, the y-direction width of the memory structure 106a in the first conductive structure of interconnect layer 104 (in...) Figure 1A (denoted by dimension D5), and / or the x-direction width of the memory structure 106a in the first conductive structure of the interconnect layer 104 (in Figure 1A (denoted by dimension D6) can be four times larger than the width between adjacent memory structures in a two-dimensional distributed memory structure of each semiconductor device in the interconnect layer. In some embodiments, the x-direction width and / or y-direction width between adjacent memory structures 106a are more than four times larger than the width between adjacent memory structures in a two-dimensional distributed memory structure in the interconnect layer of the memory structure.

[0057] As another example, due to the large lateral and / or vertical spacing between memory structures 106a and 106b, the y-direction width of memory structure 106b in the second conductive structure of interconnect layer 104 (in Figure 1A (denoted by dimension D7), and / or the x-direction width of the memory structure 106b in the second conductive structure of the interconnect layer 104 (in the dimension D7). Figure 1A (denoted by dimension D8) can be four times larger than the width between adjacent memory structures in a two-dimensional distributed memory structure of each semiconductor device in the interconnect layer. In some embodiments, the x-direction width and / or y-direction width between adjacent memory structures 106b are more than four times larger than the width between adjacent memory structures in a two-dimensional distributed memory structure in the interconnect layer of the memory structure.

[0058] Further as Figure 1A As shown, memory structure 106a can be spaced at a distance (in Figure 1A (Indicated by dimension D9) Extends laterally beyond the end or side of memory structure 106b, and / or memory structure 106b may have a distance (in Figure 1A(Described by dimension D9) Extends laterally beyond the ends or sides of memory structure 106a. This is because memory structures 106a and 106b are contained within a multilayer conductive structure or interconnect layer 104 at different vertical (z-direction) heights, and the minimum spacing between memory structures 106a and 106b is maintained in the z-direction within interconnect layer 104. In some embodiments, dimension D9 is greater than 0 nanometers and less than or approximately equal to 50 nanometers. However, other values ​​and ranges are also within the scope of this disclosure.

[0059] Figure 1B It is drawn along Figure 1A The cross-sectional view of the semiconductor device 100 is shown with section line AA in the figure. Therefore, Figure 1B The cross-sectional view is located in the xz plane of the semiconductor device 100 and spans multiple memory structures 106a. For example... Figure 1B As shown, the semiconductor device 100 may include a device layer 108. In the z-direction of the semiconductor device 100, an interconnect layer 104 is located above the device layer 108. The device layer 108 may also be referred to as the front-end region or the production line front-end (FEOL) region of the semiconductor device 100.

[0060] Device layer 108 includes a substrate 110 of semiconductor device 100. Substrate 110 may correspond to a portion of a semiconductor wafer on which semiconductor device 100 is formed. Substrate 110 may include a silicon (Si) substrate, a substrate formed of a silicon material, a III-V compound semiconductor material substrate such as gallium arsenide (GaAs), a silicon-on-insulator (SOI) substrate, or other types of substrates. Substrate 110 may extend in the x-direction and / or y-direction of semiconductor device 100.

[0061] Integrated circuit device 112 may be contained in and / or on substrate 110 in device layer 108 of semiconductor device 100. Integrated circuit device 112 may include front-end transistor structures (e.g., front-end planar transistor structures, front-end fin field-effect transistor (finFET) structures, front-end gate all-around (GAA) transistor structures), pixel sensors, capacitors, resistors, inductors, photodetectors, transceivers, transmitters, receivers, optical circuits, and / or other types of front-end semiconductor devices. In some embodiments, integrated circuit device 112 is electrically coupled to memory structure 106 in memory array 102 to form memory cells of memory array 102.

[0062] The front-end transistor structure may include multiple source / drain regions, which may correspond to doped regions of substrate 110 and are separated by channels in substrate 110. In some embodiments, the source / drain regions are doped with a first type of dopant (e.g., p-type dopant of boron (B) and / or gallium (Ga), or n-type dopant of phosphorus (P) and / or arsenic (As), and the channel regions are doped with a second type of dopant different from the first type of dopant. The front-end transistor structure may include a gate structure located above and / or around the channel regions. The gate dielectric layer of the front-end transistor structure may be included between the gate structure and the channel regions. The gate structure may include a polysilicon gate, a metal gate having a high dielectric constant (high k) gate dielectric layer (e.g., having hafnium oxide (HfO)). x (e.g., HfO2), and / or other types of gate structures.

[0063] A dielectric layer 114 is included above the substrate 110. The dielectric layer 114 includes an interlayer dielectric (ILD) layer, an etch stop layer (ESL), and / or other types of dielectric layers. The dielectric layer 114 includes a dielectric material and enables selective etching or prevents etching of various portions of the substrate 110 and / or the integrated circuit device 112, and / or electrically isolates the integrated circuit device 112 in the device layer 108. The dielectric layer 114 includes silicon nitride (Si). x N y ), oxides (e.g., silicon oxide (SiO2) x The dielectric layer 114 may extend in the x-direction and / or y-direction of the semiconductor device 100. Contacts 116 (e.g., source / drain contacts, gate contacts) may extend through the dielectric layer 114 and be located between the integrated circuit device 112 and the interconnect layer 104. Contacts 116 may electrically connect the integrated circuit device 112 and the interconnect layer 104. Contacts 116 may include vias, plugs, and / or other types of elongated conductive structures. Contacts 116 may include tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), and / or gold (Au) and other conductive materials.

[0064] Interconnect layer 104 of semiconductor device 100 is included over substrate 110 and integrated circuit device 112 in the z-direction of semiconductor device 100. Interconnect layer 104 includes a plurality of dielectric layers (e.g., back-end dielectric layers) disposed along a direction substantially perpendicular to substrate 110 (e.g., z-direction). The dielectric layers may include ILD layer 118 and ESL 120 disposed alternately in the z-direction. ILD layer 118 and ESL 120 may extend in the x-direction and / or y-direction of semiconductor device 100.

[0065] Each ILD layer 118 may each include an oxide (e.g., silicon oxide (SiO2)). x The dielectric material can be an undoped silicate glass (USG), a borosilicate glass (BSG), a fluorine-containing silicate glass (FSG), a tetraethyl orthosilicate (TEOS), a hydrogensilsesquioxane (HSQ), or other suitable dielectric materials. In some embodiments, the ILD layer 118 comprises an extremely low dielectric constant (ELK) dielectric material with a dielectric constant less than about 2.5. Examples of ELK dielectric materials include carbon-doped silicon oxide (C-SiO₂). x amorphous fluorinated carbon (aC) x F y ), parylene, bis-benzocyclobutene (BCB), polytetrafluoroethylene (PTFE), silicon carbide (SiOC) polymers, porous HSQ, porous methyl silsesquioxane (MSQ), porous polyarylether (PAE), and / or porous silica (SiO2). x )wait.

[0066] Each ESL 120 may contain silicon nitride (Si) x N y Silicon carbide (SiC), silicon oxynitride (SiON), and / or other suitable dielectric materials. In some embodiments, ILD layers 118 and ESL 120 comprise different dielectric materials to provide etch selectivity, enabling the formation of various structures in interconnect layer 104.

[0067] Interconnect layer 104 includes a plurality of conductive structures disposed in the multilayer. The conductive structures may be electrically coupled and / or physically coupled to one or more integrated circuit devices 112 in device layer 108. The conductive structures provide electrical wiring and allow signals and / or power to be provided to and / or from the integrated circuit devices 112 and / or memory structures 106 in interconnect layer 104, and / or from the memory structures 106 in interconnect layer 104.

[0068] The multilayer conductive structure may include multiple layers 122a-122d arranged vertically and alternating (e.g., vertically alternating) with multiple layers 124a-124c in the z-direction. Each layer 122a-122d includes a metallization structure 126, and each layer 124a-124c includes an interconnection structure 128. Each layer 122a-122d of the metallization structure 126 may be referred to as an M layer. For example, layer 122a of metallization structure 126 (referred to as metal-0 (M0) layer) may be located at the bottom of interconnect layer 104 and may be directly coupled to device layer 108 (e.g., to contact 116); layer 122b of metallization structure 126 (referred to as metal-1 (M1) layer) may be located above layer 122a of metallization structure 126 in interconnect layer 104, layer 122c of metallization structure 126 (referred to as metal-2 (M2) layer) may be located above layer 122b of metallization structure 126 in interconnect layer 104, and so on. Layer 124a of interconnection structure 128 (referred to as via 1 (V1) layer) may be included between M0 layer and M1 layer to interconnect M0 layer and M1 layer; layer 124b of interconnection structure 128 (referred to as via 2 (V2) layer) may be included between M1 layer and M2 layer to interconnect M1 layer and M2 layer, and so on.

[0069] Metallization structure 126 may include combinations of trenches, metallization layers, wires, and / or other types of conductive structures. Interconnection structure 128 may include combinations of vias, interconnects, and / or other types of conductive structures. Metallization structure 126 and interconnection structure 128 may be one or more conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), and / or combinations thereof, as well as other examples of conductive materials. In some embodiments, one or more padding layers are included between the dielectric layer of interconnection layer 104 and metallization structure 126, and / or between the dielectric layer of interconnection layer 104 and interconnection structure 128. The one or more padding layers may include barrier pads, adhesive pads, and / or other types of pads. Examples of materials disposed in the one or more pads include tantalum nitride (TaN) and / or titanium nitride (TiN).

[0070] In some embodiments, the top layer of the conductive structure (e.g., the top layer of the metallization structure 126, the top layer of the interconnect structure 128) may be coupled to a connection structure on top of the semiconductor device 100. The connection structure may include solder balls, solder bumps, contact pads (e.g., land grid array (LGA) pads), contact pins (e.g., pin grid array (PGA) pins), under-bump metallization (UBM) connections, microbumps, ball grid array (BGA) balls, controlled collapse chip connection (C4) bumps, and / or other types of connection structures.

[0071] Further as Figure 1B As shown, memory structure 106a may be contained within memory layer 130a in interconnect layer 104. Memory layer 130a (and therefore memory structures 106a contained within memory layer 130a) is located at a first vertical (z-direction) height in interconnect layer 104 (e.g., relative to substrate 110, relative to the bottom of interconnect layer 104) and at the same ILD layer 118 in interconnect layer 104. In some embodiments, two or more memory structures 106a contained in memory layer 130a are located at the same vertical (z-direction) height in memory layer 130a and are therefore contained in the same xy plane in interconnect layer 104. In some embodiments, two or more memory structures 106a contained in memory layer 130a are located at different vertical (z-direction) heights in memory layer 130a and are therefore contained in different xy planes in interconnect layer 104, while still located in the same ILD layer 118.

[0072] In some embodiments, memory layer 130a (and therefore memory structure 106a included in memory layer 130a) is contained within an interconnect structure 128, for example... Figure 1B The example shows layer 124b. However, memory layer 130a (and therefore memory structure 106a included in memory layer 130a) may be included in another interconnect structure 128 in interconnect layer 104, or may be located in, for example, Figures 7A to 7C The metallized structure 126 shown is a single layer.

[0073] In layer 124b of interconnect structure 128, memory structure 106a may be electrically and / or physically coupled to interconnect structure 128a at its bottom, and electrically and / or physically coupled to interconnect structure 128b at its top. Therefore, each interconnect structure 128a and 128b coupled to memory structure 106a may vertically span a height less than the entire vertical (z-direction) of layer 124b of interconnect structure 128. Interconnect structure 128a in layer 124b may be electrically and / or physically coupled to metallization structure 126 in layer 122b below layer 124b, and interconnect structure 128b in layer 124b may be electrically and / or physically coupled to metallization structure 126 in layer 122c above layer 124b.

[0074] Figure 1C It is drawn along Figure 1A The cross-sectional view of the semiconductor device 100 is shown in section line BB. Therefore, Figure 1C The cross-sectional view is located in the xz plane of the semiconductor device 100 and spans multiple memory structures 106b. For example... Figure 1C As shown, memory structure 106b may be contained within memory layer 130b in interconnect layer 104. Memory layer 130b (and therefore memory structure 106b contained within memory layer 130b) is located at a second vertical (z-direction) height in interconnect layer 104 (e.g., relative to substrate 110, relative to the bottom of interconnect layer 104). In some embodiments, two or more memory structures 106b contained in memory layer 130b are located at the same vertical (z-direction) height in memory layer 130b, and are therefore contained in the same xy plane in interconnect layer 104. In some embodiments, two or more memory structures 106b contained in memory layer 130b are located at different vertical (z-direction) heights in memory layer 130b, and are therefore contained in different xy planes in interconnect layer 104, while still located in the same ILD layer 118.

[0075] In some implementations, memory layer 130b (and therefore memory structure 106b included in memory layer 130b) is contained within an interconnect structure 128, for example... Figure 1C The example shows layer 124c. However, memory layer 130b (and therefore memory structure 106b included in memory layer 130b) may be included in another interconnect structure 128 in interconnect layer 104, or may be located in, for example, Figures 7A to 7C The metallized structure 126 shown is a single layer.

[0076] In layer 124c of interconnect structure 128, memory structure 106b may be electrically and / or physically coupled to interconnect structure 128a at its bottom, and electrically and / or physically coupled to interconnect structure 128b at its top. Therefore, each interconnect structure 128a and 128b coupled to memory structure 106b may vertically span the entire vertical (z-direction) height of layer 124c of interconnect structure 128. Interconnect structure 128a in layer 124c may be electrically and / or physically coupled to metallization structure 126 in layer 122c below layer 124c, and interconnect structure 128b in layer 124c may be electrically and / or physically coupled to metallization structure 126 in layer 122d above layer 124c.

[0077] In some implementations, each memory structure 106a and each memory structure 106b may be electrically coupled to different signal lines in the interconnect layer 104 (e.g., different vertical arrangements of the metallization structure 126 and the interconnect structure 128). This enables each memory structure 106a to be electrically coupled to each memory structure 106b for individual addressability and accessibility within the memory array 102.

[0078] Figure 1D It is drawn along Figure 1A The cross-sectional view of the semiconductor device 100 is shown in section line CC. Therefore, Figure 1D The cross-sectional view is located in the yz plane of the semiconductor device 100 and spans the alternating memory structures 106a and 106b. For example... Figure 1D As shown, the second vertical (z-direction) height of memory layer 130b is greater than the first vertical (z-direction) height of memory layer 130a. Therefore, memory layer 130b (and thus memory structure 106b included in memory layer 130b) is located above memory layer 130a (and thus memory structure 106a included in memory layer 130a). This allows for an increase in the size of memory structure 106a and / or the spacing between memory structures 106a, and / or an increase in the size of memory structure 106b and / or the spacing between memory structures 106b, while simultaneously maintaining sufficient z-direction spacing between memory structures 106a and 106b.

[0079] As mentioned above, Figures 1A to 1D Provided as an example, and other examples can be used in conjunction with it. Figures 1A to 1D The differences are as described.

[0080] Figures 2A to 2IThis is a schematic diagram illustrating an exemplary embodiment 200 of the semiconductor device described herein. Although the processing operations of the exemplary embodiment 200 are shown and described in conjunction with the semiconductor device 100 described herein, the processing operations of the exemplary embodiment 200 may be performed to form another semiconductor device as described herein, for example... Figures 3A to 3E Semiconductor device 300, Figure 4 Semiconductor device 400, Figure 5 Semiconductor devices 500, Figure 6 Semiconductor device 600, Figures 7A to 7C Semiconductor device 700, Figures 8A to 8C The semiconductor device 800, and / or another semiconductor device. In some embodiments, combined with Figures 2A to 2I One or more of the semiconductor processing operations can be performed using one or more semiconductor processing tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / wafer transport tools, and / or other types of semiconductor processing tools.

[0081] Please see Figure 2A A substrate 110 is provided. The substrate 110 may be provided in the form of a semiconductor wafer, such as a silicon (Si) wafer as an SOI wafer and / or another type of semiconductor workpiece.

[0082] like Figure 2B and Figure 2C As shown, an integrated circuit device 112 may be formed in and / or on a substrate 110 in a device layer 108 of a semiconductor device 100. One or more semiconductor processing tools may be configured to form one or more portions of the integrated circuit device 112. For example, a deposition tool may be configured to perform various deposition operations to deposit layers and / or structures of the integrated circuit device 112, and / or deposit a photoresist layer configured to etch portions of the substrate 110 and / or the deposited layer. As another example, an exposure tool may be used to expose the photoresist layer to form a pattern in the photoresist layer. As another example, a developing tool may develop the pattern in the photoresist layer. As another example, an etching tool may be configured to etch portions of the substrate 110 and / or the deposited layer to form the integrated circuit device 112. As another example, a planarization tool may be configured to planarize portions of the integrated circuit device 112.

[0083] Additionally and / or alternatively, integrated circuit devices may be formed in the interconnect layer of a semiconductor device, for example, by combining Figures 8A to 8C Integrated circuit device 812 in interconnect layer 804 of semiconductor device 800 shown and described.

[0084] Further as Figure 2B and Figure 2CAs shown, the deposition tool is configured to deposit a dielectric layer 114 over and / or on the substrate 110 and over and / or on the integrated circuit device 112. The deposition tool may be configured to deposit the dielectric layer 114 using physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), oxidation techniques, and / or other suitable deposition techniques. In some embodiments, a planarization tool may be configured to perform a planarization operation, such as chemical mechanical planarization (CMP), to planarize the dielectric layer 114 after deposition.

[0085] Further as Figure 2B and Figure 2C As shown, contacts 116 of the integrated circuit device 112 can be formed through the dielectric layer 114. Contacts 116 can be formed in recesses within the dielectric layer 114. In these embodiments, a photoresist layer can be formed on the dielectric layer 114 using a deposition tool. An exposure tool can be configured to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool can be configured to etch the dielectric layer based on the pattern to form the recess. In some embodiments, the etching operation includes dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or other types of etching operations. In some embodiments, a photoresist removal tool can be configured to remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or other techniques). In some embodiments, a hard mask layer is used as an alternative technique to etching the dielectric layer 114 based on the pattern to form the recess.

[0086] The deposition tool can be configured to deposit material for contact 116 in the recess using CVD, PVD, ALD, electroplating, and / or other suitable deposition techniques. The material for contact 116 can be deposited in one or more deposition operations. In some embodiments, a seed layer is first deposited, and the material for contact 116 is deposited on the seed layer. In some embodiments, after depositing contact 116, a planarization tool is used to perform a planarization operation (e.g., CMP operation) to planarize contact 116 such that the top of contact 116 is substantially coplanar with the top of dielectric layer 114.

[0087] like Figures 2D to 2FAs shown, a first portion of the interconnect layer 104 of the semiconductor device 100 is formed over the dielectric layer 114. One or more deposition tools are used to deposit alternating layers of ILD layers 118 and ESL layers 120 in the first portion of the interconnect layer 104 of the semiconductor device 100. In this way, the ILD layers 118 and ESL layers 120 can be disposed in the z-direction of the semiconductor device 100. Each ILD layer 118 and each ESL layer 120 can be deposited using one or more deposition tools via PVD, ALD, CVD, oxidation, and / or other suitable deposition techniques. In some embodiments, after depositing the ILD layers 118 and / or ESL layers 120, a planarization tool can be used to planarize the ILD layers 118 and / or ESL layers 120.

[0088] like Figure 2E and Figure 2F As shown, deposition tools, exposure tools, developing tools, etching tools, planarization tools, electroplating tools, and / or other semiconductor processing tools can be used to perform various operations to form the layers 122a and 122b of the metallization structure 126, and the layers 124a and 124b of the interconnect structure 128 in the first portion of the interconnect layer 104 of the semiconductor device 100. The layers 122a and 122b of the metallization structure 126 and the layers 124a and 124b of the interconnect structure 128 may be included in the ILD layer 118 and / or ESL 120.

[0089] like Figure 2E and Figure 2F As shown, deposition tools, exposure tools, developing tools, etching tools, planarization tools, electroplating tools, and / or other semiconductor processing tools can be used to perform various operations to form a memory structure 106a of memory layer 130a in interconnect layer 104. As an example, ESL 120 and ILD layer 118 can be deposited, and then etching can be performed to form a recess in ESL 120 and ILD layer 118. This layer 122a of metallization structure 126 (e.g., metal 0 layer or MO layer) can be formed in the recess, such that one or more metallization structures 126 are bonded to contact 116. Another ESL 120 and another ILD layer 118 can be formed on this layer 122a of metallization structure 126, and then etching can be performed to form a recess in ESL 120 and ILD layer 118. The interconnect structure 128 of the layer 124a (e.g., via 0 layer or V0 layer) can be formed in the recess such that one or more of the interconnect structures 128 are bonded to one or more of the metallization structures 126 of the layer 122a.

[0090] Another ESL 120 and another ILD layer 118 may be formed on layer 124a of interconnect structure 128, and then etching is performed to form recesses in ESL 120 and ILD layer 118. Layer 122b of metallization structure 126 (e.g., metal I layer or M1 layer) may be formed in the recesses, such that one or more metallization structures 126 are bonded to one or more interconnect structures 128 of layer 124a. A first portion of another ESL 120 and another ILD layer 118 may be formed on layer 122b of metallization structure 126, and then etching is performed to form recesses in the first portion of ESL 120 and ILD layer 118. Interconnect structures 128a of layer 124b (e.g., via I layer or V1 layer) may be formed in the recesses, such that one or more of the interconnect structures 128a are bonded to one or more of the metallization structures 126 of layer 122b. The memory structure 106a of memory layer 130a may be formed on interconnect structure 128a and a first portion of ILD layer 118. A second portion of ILD layer 118 may then be formed, followed by etching to form recesses through ILD layer 118, including reaching memory structure 106a and / or reaching one or more of the metallization structures 126 in layer 122b. Interconnect structure 128b and / or interconnect structure 128 of layer 124b may be formed in the recesses.

[0091] like Figures 2G to 2I As shown, a second portion of the interconnect layer 104 of the semiconductor device 100 is formed over the first portion of the interconnect layer 104. Alternating layers of ILD layers 118 and ESL layers 120 are deposited on the second portion of the interconnect layer 104 of the semiconductor device 100 using one or more deposition tools. In this way, the ILD layers 118 and ESL layers 120 can be disposed in the z-direction of the semiconductor device 100. Each ILD layer 118 and each ESL layer 120 can be deposited using one or more deposition tools via PVD, ALD, CVD, oxidation, and / or other suitable deposition techniques. In some embodiments, after depositing the ILD layers 118 and / or ESL layers 120, a planarization tool can be used to planarize the ILD layers 118 and / or ESL layers 120.

[0092] Further as Figure 2H and Figure 2IAs shown, deposition tools, exposure tools, developing tools, etching tools, planarization tools, electroplating tools, and / or other semiconductor processing tools can be used to perform various operations to form layers 122c and 122d of the metallization structure 126, and layer 124c of the interconnect structure 128 in the second portion of the interconnect layer 104 of the semiconductor device 100. Layers 122c and 122d of the metallization structure 126 and layer 124c of the interconnect structure 128 may be included in the ILD layer 118 and / or ESL 120.

[0093] Further as Figure 2H and Figure 2I Deposition tools, exposure tools, developing tools, etching tools, planarization tools, electroplating tools, and / or other semiconductor processing tools may be configured to perform various operations to form a memory structure 106b of memory layer 130b in interconnect layer 104. As an example, ESL 120 and ILD layer 118 may be deposited, and then etching may be performed to form a recess in ESL 120 and ILD layer 118. This layer 122c of metallization structure 126 (e.g., a metal 2 layer or M2 layer) may be formed in the recess, such that one or more of the metallization structures 126 are bonded to interconnect structure 128 and / or bonded to interconnect structure 128b.

[0094] Another ESL 120 and a first portion of another ILD layer 118 may be formed on layer 122c of metallization structure 126, and then etching is performed to form recesses in ESL 120 and the first portion of ILD layer 118. Interconnect structures 128a (e.g., via 2-layer or V2-layer) of layer 124c may be formed in the recesses, such that one or more of the interconnect structures 128a are bonded to one or more of the metallization structures 126 of layer 122c. Memory structure 106b of memory layer 130b may be formed on interconnect structure 128a and the first portion of ILD layer 118. A second portion of ILD layer 118 may then be formed, and then etching is performed to form recesses through ILD layer 118, including reaching memory structure 106b and / or reaching one or more of the metallization structures 126 in layer 122c. The interconnect structure 128 of interconnect structure 128b and / or layer 124c may be formed in a recess.

[0095] Another ESL 120 and another ILD layer 118 may be formed on layer 124c, including one or more of the interconnect structures 128 and / or one or more of the interconnect structures 128b of layer 124c. ESL 120 and ILD layer 118 may be etched to form recesses in ESL 120 and ILD layer 118. Layer 122d of metallization structure 126 (e.g., a metal 3 layer or M3 layer) may be formed in the recesses, such that one or more of the metallization structures 126 are bonded to one or more interconnect structures 128 and / or one or more interconnect structures 128b of layer 124c.

[0096] As mentioned above, Figures 2A to 2I Provided as an example, and other examples can be used in conjunction with it. Figures 2A to 2I The differences are as described. Combinations can be performed. Figures 2D to 2I The process described herein forms an additional memory layer of the memory structure, thereby forming a multilayer memory array in the interconnect layer of the semiconductor device disclosed herein.

[0097] Figures 3A to 3E This is a schematic diagram of the exemplary semiconductor device 300 described in this disclosure. Figures 3A to 3E As shown, semiconductor device 300 includes various layers and / or structures similarly arranged to semiconductor device 100. For example, semiconductor device 300 includes a memory array 302 in interconnect layer 304, memory array 302 including a plurality of memory structures 306 in interconnect layer 304, device layer 308 located below interconnect layer 304 and including integrated circuit device 312 and dielectric layer 314 located in substrate 310, and contacts 316 of integrated circuit device 312 extending through dielectric layer 314. In addition, interconnect layer 304 includes a multilayer 322a of a plurality of metallization structures 326 and a multilayer 324b of a plurality of interconnect structures 328 disposed perpendicular to the multilayer 322a of metallization structures 326.

[0098] However, as Figures 3A to 3E As shown, semiconductor device 300 includes a larger number of memory layers in interconnect layer 104 than semiconductor device 100. As an example, semiconductor device 300 includes memory structures 306 distributed on four vertically arranged memory layers 330a-330d. Memory layer 330a includes memory structure 306a, memory layer 330b includes memory structure 306b, memory layer 330c includes memory structure 306c, and memory layer 330d includes memory structure 306d. Figures 3A to 3E The memory structures and the number of memory layers shown are exemplary, and other numbers of memory structures and memory layers are also within the scope of this disclosure.

[0099] like Figure 3AAs shown in the top view, memory structures 306a and 306b may be arranged in the same column in the y-direction of the semiconductor device 100, and memory structures 306c and 306d may be arranged in the same column in the y-direction of the semiconductor device 100. However, other top view arrangements of memory structures 306a-306d are also within the scope of this disclosure. For example, memory structures 306a and 306c may be arranged in the same column in the y-direction of the semiconductor device 100, and memory structures 306b and 306d may be arranged in the same column in the y-direction of the semiconductor device 100. In another example, memory structures 306a and 306d may be arranged in the same column in the y-direction of the semiconductor device 100, and memory structures 306b and 306c may be arranged in the same column in the y-direction of the semiconductor device 100.

[0100] Further as Figure 3A As shown, the columns of memory structure 306 can be staggered or offset along the x-direction in the y-direction. For example, a column of memory structures 306a and 306b can be laterally offset in the y-direction relative to the adjacent columns of memory structures 306c and 306d. However, in some embodiments, multiple columns of memory structures 306a and 306b and multiple columns of memory structures 306c and 306d are configured such that the ends of multiple columns of memory structures 306a and 306b and the ends of multiple columns of memory structures 306c and 306d are aligned along the y-direction.

[0101] Further as Figure 3A As shown, a column of memory structures 306a and 306b may partially overlap laterally with adjacent columns of memory structures 306c and 306d. Since memory structures 306a and 306b are located at different vertical (z-direction) heights in interconnect layer 304 than memory structures 306c and 306d, this column of memory structures 306a and 306b and adjacent columns of memory structures 306c and 306d may partially overlap laterally. Additionally and / or optionally, since memory structures 306a and 306b in a column are located at different vertical (z-direction) heights in interconnect layer 304, memory structure 306a in that column may partially overlap laterally with memory structure 306b in that column. Additionally and / or optionally, since memory structures 306c and 306d in adjacent columns are located at different vertical (z-direction) heights in the interconnect layer 304, memory structure 306c in one column can partially overlap laterally with memory structure 306d in the adjacent column. In some embodiments, the overlap between memory structures 306 in the memory array 302 is greater than 0 nanometers and less than or approximately equal to 50 nanometers. However, other values ​​and ranges are also within the scope of this disclosure.

[0102] Figure 3BIt is drawn along Figure 3A The cross-sectional view of semiconductor device 300 with section line DD in the figure. Therefore, Figure 3B The cross-sectional view is located in the yz plane of the semiconductor device 300 and spans a row of memory structures 306a and 306b. For example... Figure 3B As shown, interconnect layer 304 includes an ILD layer 318 and an ESL layer 320 arranged vertically (z-direction), and multiple layers 322a-322f of metallization structure 326 and multiple layers 324a-324e of interconnect structure 328 arranged vertically (z-direction). The number and arrangement of ILD layer 318, ESL 320, multiple layers 322a-322f of metallization structure 326 and multiple layers 324a-324e of interconnect structure 328 are exemplary, and other numbers and arrangements are also within the scope of this disclosure.

[0103] Further as Figure 3B As shown, memory structure 306a may be included in memory layer 330a in interconnect layer 304, and memory structure 306b may be included in memory layer 330b in interconnect layer 304. Memory layer 330a (and therefore memory structure 306a included in memory layer 330a) is located at a first vertical (z-direction) height in interconnect layer 304 and is located in the same ILD layer 318 in interconnect layer 304, and memory layer 330b (and therefore memory structure 306b included in memory layer 330b) is located at a second vertical (z-direction) height in interconnect layer 304 and is located in the same ILD layer 318 in interconnect layer 304. The first vertical (z-direction) height and the second vertical (z-direction) height are different vertical (z-direction) heights, such that memory layer 330b (and therefore memory structure 306b included in memory layer 330b) is located above memory layer 330a (and therefore memory structure 306a included in memory layer 330a).

[0104] In some embodiments, memory layer 330a (and therefore memory structure 306a included in memory layer 330a) is included in an interconnect structure 328, for example Figure 3B The example illustrates layer 324b. However, memory layer 330a (and therefore memory structure 306a included in memory layer 330a) may be included in interconnect structure 328 of another layer in interconnect layer 304, or may be located in, for example, Figures 7A to 7C The metallized structure 326 shown is a single layer.

[0105] In layer 324b of interconnect structure 328, memory structure 306a can be electrically and / or physically coupled to interconnect structure 328a at the bottom of memory structure 306a, and can be electrically and / or physically coupled to interconnect structure 328b at the top of memory structure 306a. Therefore, the vertical span of each interconnect structure 328a and 328b coupled to memory structure 306a can be less than the entire vertical (z-direction) height of layer 324b of interconnect structure 328. Interconnect structure 328a in layer 324b can be electrically and / or physically coupled to metallization structure 326 in layer 322b below layer 324b, and interconnect structure 328b in layer 324b can be electrically and / or physically coupled to metallization structure 326 in layer 322c above layer 324b.

[0106] In some embodiments, memory layer 330b (and thus memory structure 306b included in memory layer 330b) is contained within one layer of interconnect structure 328, for example... Figure 3B The example shows layer 324c. However, memory layer 330b (and therefore memory structure 306b included in memory layer 330b) may be included in interconnect structure 328 of another layer in interconnect layer 304, or may be located in, for example, Figures 7A to 7C The metallized structure 326 shown is a single layer.

[0107] In layer 324c of interconnect structure 328, memory structure 306b can be electrically and / or physically coupled to interconnect structure 328a at the bottom of memory structure 306b, and can be electrically and / or physically coupled to interconnect structure 328b at the top of memory structure 306b. Therefore, the vertical span of each interconnect structure 328a and 328b coupled to memory structure 306b can be less than the entire vertical (z-direction) height of layer 324c of interconnect structure 328. Interconnect structure 328a in layer 324c can be electrically and / or physically coupled to metallization structure 326 in layer 322c below layer 324c, and interconnect structure 328b in layer 324c can be electrically and / or physically coupled to metallization structure 326 in layer 322d above layer 324c.

[0108] Figure 3C It is drawn along Figure 3A The cross-sectional view of semiconductor device 300 with section line EE in the figure. Therefore, Figure 3C The cross-sectional view is located in the yz plane of semiconductor device 300 and spans a row of memory structures 306c and 306d. For example... Figure 3CAs shown, memory structure 306c may be contained within memory layer 330c in interconnect layer 304, and memory structure 306d may be contained within memory layer 330d in interconnect layer 304. Memory layer 330c (and therefore memory structure 306c contained within memory layer 330c) is located at a third vertical (z-direction) height in interconnect layer 304 and is located within the same ILD layer 318 in interconnect layer 304, and memory layer 330d (and therefore memory structure 306d contained within memory layer 330d) is located at a fourth vertical (z-direction) height in interconnect layer 304 and is located within the same ILD layer 318 in interconnect layer 304. The third vertical (z-direction) height and the fourth vertical (z-direction) height are different vertical (z-direction) heights, such that memory layer 330c (and therefore memory structure 306d included in memory layer 330d) is located above memory layer 330c (and therefore memory structure 306c included in memory layer 330c).

[0109] In some embodiments, memory layer 330c (and thus memory structure 306c included in memory layer 330c) is included in an interconnect structure 328 of one layer, for example... Figure 3C The example illustrates layer 324d. However, memory layer 330c (and therefore memory structure 306c included in memory layer 330c) may be included in interconnect structure 328 of another layer in interconnect layer 304, or may be located in, for example, Figures 7A to 7C The metallized structure 326 shown is a single layer.

[0110] In layer 324d of interconnect structure 328, memory structure 306c can be electrically and / or physically coupled to interconnect structure 328a at the bottom of memory structure 306c, and can be electrically and / or physically coupled to interconnect structure 328b at the top of memory structure 306c. Therefore, the vertical span of each interconnect structure 328a and 328b coupled to memory structure 306c can be less than the entire vertical (z-direction) height of layer 324d of interconnect structure 328. Interconnect structure 328a in layer 324d can be electrically and / or physically coupled to metallization structure 326 in layer 322d below layer 324d, and interconnect structure 328b in layer 324d can be electrically and / or physically coupled to metallization structure 326 in layer 322e above layer 324d.

[0111] In some embodiments, memory layer 330d (and therefore memory structure 306d included in memory layer 330d) is included in an interconnect structure 328, for example Figure 3CThe example illustrates layer 324e. However, memory layer 330d (and therefore memory structure 306d included in memory layer 330d) may be included in interconnect structure 328 of another layer in interconnect layer 304, or may be located in, for example, Figures 7A to 7C The metallized structure 326 shown is a single layer.

[0112] In layer 324e of interconnect structure 328, memory structure 306d may be electrically and / or physically coupled to interconnect structure 328a at the bottom of memory structure 306d, and may be electrically and / or physically coupled to interconnect structure 328b at the top of memory structure 306d. Therefore, the vertical span of each interconnect structure 328a and 328b coupled to memory structure 306d may be less than the entire vertical (z-direction) height of layer 324e of interconnect structure 328. Interconnect structure 328a in layer 324e may be electrically and / or physically coupled to metallization structure 326 in layer 322e below layer 324e, and interconnect structure 328b in layer 324e may be electrically and / or physically coupled to metallization structure 326 in layer 322f above layer 324e.

[0113] Figure 3D It is drawn along Figure 3A The cross-sectional view of semiconductor device 300 with section line FF in the figure. Therefore, Figure 3D The cross-sectional view is located in the x / yz plane of the semiconductor device 300 and spans multiple columns of memory structures 306. Each memory structure 306a-306d can be electrically coupled to different signal lines in the interconnect layer 304 (e.g., different vertically arranged metallization structures 326 and interconnect structures 328). Furthermore, each memory structure 306a-306d can be electrically coupled to different integrated circuit devices 312 (e.g., different transistors). Thus, each memory structure 306a-306d can be electrically coupled to different memory structures to be individually addressable and accessible in the memory array 302.

[0114] Figure 3E It is drawn along Figure 3A The cross-sectional view of semiconductor device 300 with section line GG in the figure. Therefore, Figure 3E The cross-sectional view is located in the yz plane of the semiconductor device 300, and spans the overlapping area between a column of memory structures 306a and 306b and adjacent columns of memory structures 306c and 306d. For example... Figure 3EAs shown, the first vertical (z-direction) height of memory layer 330a, the second vertical (z-direction) height of memory layer 330b, the third vertical (z-direction) height of memory layer 330c, and the fourth vertical (z-direction) height of memory layer 330d are different vertical (z-direction) heights in interconnect layer 304. Memory layer 330b (and therefore memory structure 306b included in memory layer 330b) is located above memory layer 330a (and therefore memory structure 306a included in memory layer 330a). Memory layer 330c (and therefore memory structure 306c included in memory layer 330c) is located above memory layer 330a (and therefore memory structure 306a included in memory layer 330a) and memory layer 330b (and therefore memory structure 306b is included in memory layer 330b). Memory layer 330d (and therefore memory structure 306d included in memory layer 330d) is located above memory layer 330a (and therefore memory structure 306a included in memory layer 330a), memory layer 330b (and therefore memory structure 306b included in memory layer 330b) and memory layer 330c (and therefore memory structure 306c included in memory layer 330c).

[0115] Further as Figure 3E As shown, memory structures 306a-306d located in different vertical (z-direction) memory layers 330a-330d enable the creation of regions where memory structures 306a-306d at least partially overlap laterally. For example, overlapping region 332a may exist in the region where memory structures 306a, 306c, and 306d at least partially overlap laterally. As another example, overlapping region 332b may exist in the region where memory structures 306a and 306d at least partially overlap laterally. As another example, overlapping region 332c may exist in the region where memory structures 306a, 306b, and 306d at least partially overlap laterally. As another example, overlapping region 332d may exist in the region where memory structures 306b and 306d at least partially overlap laterally. As yet another example, overlapping region 332e may exist in the region where memory structures 306b, 306c, and 306d at least partially overlap laterally. In another example, the overlapping region 332f may exist in the region where memory structures 306b and 306c at least partially overlap laterally. In another example, the overlapping region 332g may exist in the region where memory structures 306a, 306b, and 306c at least partially overlap laterally. In another example, the overlapping region 332h may exist in the region where memory structures 306a and 306c at least partially overlap laterally.

[0116] As mentioned above, Figures 3A to 3E Provided as an example, and other examples can be used in conjunction with it. Figures 3A to 3E The differences are as described.

[0117] Figure 4 This is a schematic diagram of the exemplary semiconductor device 400 described in this disclosure. Figure 4 As shown, semiconductor device 400 includes various layers and / or structures similarly arranged to semiconductor device 100. For example, semiconductor device 400 includes a memory array 402 in an interconnect layer 404, and the memory array 402 includes a plurality of memory structures 406 in the interconnect layer 404. The memory structures 406 include a first plurality of memory structures 406a and a second plurality of memory structures 406b. Memory structures 406a are located at a first vertical (z-direction) height in the interconnect layer 404, and memory structures 406b are located at a second vertical (z-direction) height in the interconnect layer 404, different from the first vertical (z-direction) height. Therefore, memory structures 406a and 406b are arranged vertically in the memory array 402, in addition to being arranged laterally in the memory array 402.

[0118] Further as Figure 4 As shown, memory structures 406a and 406b have different dimensions. For example, memory structure 406b may have a larger lateral area than memory structure 406a. The smaller size of memory structure 406a allows it to operate at faster read and write speeds, and is therefore configurable to benefit from memory applications with lower read and write latency. The larger size of memory structure 406b allows it to retain information for a longer period, and is therefore configurable for long-term storage applications.

[0119] Memory structure 406a may have a width in the y-direction (in Figure 4 (represented by dimension D10) and width in the x direction (in Figure 4 (Represented by dimension D11). The memory structure 406b may have a width in the y-direction (in... Figure 4 (represented by dimension D12) and width in the x direction (in Figure 4 (denoted by dimension D13). In some embodiments, the x-direction width (dimension D13) of memory structure 406b is greater than the x-direction width (dimension D11) of memory structure 406a. In some embodiments, the x-direction width (dimension D13) of memory structure 406b is substantially the same as the x-direction width (dimension D11) of memory structure 406a.

[0120] In some embodiments, the y-direction width (dimension D12) of memory structure 406b is greater than the y-direction width (dimension D10) of memory structure 406a. This greater y-direction width (dimension D12) of memory structure 406b allows multiple memory structures 406a to at least partially overlap laterally with the same memory structure 406b on the same side. In some embodiments, the overlap between memory structures 406a and 406b is greater than 0 nanometers and less than or approximately equal to 50 nanometers. However, other values ​​and ranges are also within the scope of this disclosure. In some embodiments, the y-direction width (dimension D12) of memory structure 406b and the y-direction width (dimension D10) of memory structure 406a are substantially the same width.

[0121] As mentioned above, Figure 4 Provided as an example, and other examples can be used in conjunction with it. Figure 4 The differences are as described.

[0122] Figure 5 This is a schematic diagram of the exemplary semiconductor device 500 described in this disclosure. Figure 5 As shown, semiconductor device 500 includes various layers and / or structures arranged similarly to those in semiconductor device 300. For example, semiconductor device 500 includes a memory array 502 in interconnect layer 504, and memory array 502 includes a plurality of memory structures 506 in interconnect layer 504.

[0123] The memory structure 506 includes a first plurality of memory structures 506a, a second plurality of memory structures 506b, a third plurality of memory structures 506c, and a fourth plurality of memory structures 506d. Memory structures 506a are located at a first vertical (z-direction) height in the interconnect layer 504, memory structures 506b are located at a second vertical (z-direction) height in the interconnect layer 504, memory structures 506c are located at a third vertical (z-direction) height in the interconnect layer 504, and memory structures 506d are located at a fourth vertical (z-direction) height in the interconnect layer 504. The first vertical (z-direction) height, the second vertical (z-direction) height, the third vertical (z-direction) height, and the fourth vertical (z-direction) height in the interconnect layer 504 are located at different vertical (z-direction) heights in the interconnect layer 504. Therefore, memory structures 506a-506d are not only arranged horizontally in memory array 502, but also vertically in memory array 502.

[0124] However, as Figure 5As shown, memory structures 506a-506d have different top-view shapes than each of memory structures 306a-306d. Specifically, memory structures 506a-506d each have an approximately octagonal top-view shape. The octagonal top-view shape of memory structures 506a-506d can provide efficiency in photolithography in some semiconductor devices. However, other top-view shapes of the memory structures described in this disclosure are also within the scope of this disclosure.

[0125] As mentioned above, Figure 5 Provided as an example, and other examples can be used in conjunction with it. Figure 5 The differences are as described.

[0126] Figure 6 This is a schematic diagram of the exemplary semiconductor device 600 described in this disclosure. Figure 6 As shown, semiconductor device 600 includes various layers and / or structures arranged similarly to those in semiconductor device 300. For example, semiconductor device 600 includes a memory array 602 in interconnect layer 604, and memory array 602 includes a plurality of memory structures 606 in interconnect layer 604.

[0127] Memory structure 606 includes a first plurality of memory structures 606a, a second plurality of memory structures 606b, a third plurality of memory structures 606c, and a fourth plurality of memory structures 606d. Memory structures 606a are located at a first vertical (z-direction) height in interconnect layer 604, memory structures 606b are located at a second vertical (z-direction) height in interconnect layer 604, memory structures 606c are located at a third vertical (z-direction) height in interconnect layer 604, and memory structures 606d are located at a fourth vertical (z-direction) height in interconnect layer 604. The first vertical (z-direction) height, the second vertical (z-direction) height, the third vertical (z-direction) height, and the fourth vertical (z-direction) height in interconnect layer 604 are located at different vertical (z-direction) heights in interconnect layer 604. Therefore, memory structures 606a-606d are not only arranged horizontally in memory array 602, but also vertically in memory array 602.

[0128] However, as Figure 6As shown, memory structure 606a has a different top-view shape than memory structures 606b-606c. Specifically, each memory structure 606a has an approximately square top-view shape, and each memory structure 606b-606c has an approximately octagonal top-view shape. These different top-view shapes can be configured to optimize the performance of memory structures 606a-606d configured for different memory functions. However, other top-view shapes of the memory structures described in this disclosure are also within the scope of this disclosure. Furthermore, different arrangements and distributions of the shapes of the memory structures described in this disclosure are also within the scope of this disclosure.

[0129] As an example, memory structure 606a may have a first top view shape, memory structure 606b may have a second top view shape, memory structure 606c may have a third top view shape, and memory structure 606d may have a fourth top view shape. Two or more of the first, second, third, and fourth top view shapes may be the same top view shape, and / or two or more of the first, third, and fourth top view shapes may be different top view shapes.

[0130] As another example, memory structure 606a in the first column of memory array 602 may have a first top view shape, and memory structure 606a in the second column of memory array 602 may have a second top view shape. The first top view shape and the second top view shape may be the same top view shape. Alternatively, the first top view shape and the second top view shape may be different top view shapes. Similarly, memory structures 606b, 606c, and / or 606d in different columns may have the same or different top view shapes.

[0131] As an example, memory structure 606a may have a first top view area, memory structure 606b may have a second top view area, memory structure 606c may have a third top view area, and memory structure 606d may have a fourth top view area. Two or more of the first, second, third, and fourth top view areas may be substantially the same top view area, and / or two or more of the first, second, third, and fourth top view areas may be different top view areas.

[0132] As another example, memory structure 606a in the first column of memory array 602 may have a first top view area, and memory structure 606a in the second column of memory array 602 may have a second top view area. The first top view area and the second top view area may be the same top view area on the substrate. Alternatively, the first top view area and the second top view area may be different top view areas. Similarly, memory structures 606b, 606c, and / or 606d in different columns may have the same or different top view areas.

[0133] As mentioned above, Figure 6 Provided as an example, and other examples can be used in conjunction with it. Figure 6 The differences are as described.

[0134] Figures 7A to 7C This is a schematic diagram of the exemplary semiconductor device 700 described in this disclosure. Figures 7A to 7C As shown, semiconductor device 700 includes various layers and / or structures similarly arranged to semiconductor device 100. For example, semiconductor device 700 includes a memory array 702 in interconnect layer 704, memory array 702 including a plurality of memory structures 706 in interconnect layer 704, device layer 708 located below interconnect layer 704 and including integrated circuit device 712 and dielectric layer 714 located in substrate 710, and contacts 716 of integrated circuit device 712 extending through dielectric layer 714. In addition, interconnect layer 704 includes a plurality of ILD layers 718, a plurality of ESL 720, a plurality of metallization structures 726 in multiple layers 722a-722d, and a plurality of interconnect structures 728 in multiple layers 724a-724c disposed perpendicular to the multiple layers of metallization structures 726 in multiple layers 722a-722d.

[0135] However, as Figures 7A to 7C As shown, the memory layer 730a of memory structure 706a and the memory layer 730b of memory structure 706b are included in one or more of the multiple layers 722a-722d of the metallization structure 726 of interconnect layer 704, rather than in one or more of the multiple layers 724a-724c of interconnect structure 728. For example, as Figure 7B along Figure 7A As shown in the cross-sectional view along section line HH, the memory layer 730a of the memory structure 706a may be included in layer 722b of the metallized structure 726. As another example, as... Figure 7C Along the middle Figure 7AAs shown in the cross-sectional view of section line II, the memory layer 730b of the memory structure 706b may be included in the layer 722c of the metallization structure 726. The metallization structure 726a may be coupled to the bottom of the memory structure 706a and the bottom of the memory structure 706b, and the metallization structure 726b may be coupled to the top of the memory structure 706a and the top of the memory structure 706b.

[0136] Alternatively, the memory layer 730a of memory structure 706a may be included in one of the multiple layers 722a-722d of metallization structure 726 in interconnect layer 704, and the memory layer 730b of memory structure 706b may be included in one of the multiple layers 722a-722d of metallization structure 726 in interconnect layer 704. Alternatively, the memory layer 730a of memory structure 706a may be included in one of the multiple layers 724a-724c of interconnect structure 728 in interconnect layer 704, and the memory layer 730b of memory structure 706b may be included in one of the multiple layers 722a-722d of metallization structure 726 in interconnect layer 704.

[0137] As mentioned above, Figures 7A to 7C Provided as an example, and other examples can be used in conjunction with it. Figures 7A to 7C The differences are as described.

[0138] Figures 8A to 8C This is a schematic diagram of the exemplary semiconductor device 800 described in this disclosure. Figures 8A to 8C As shown, semiconductor device 800 includes various layers and / or structures similarly arranged to semiconductor device 100. For example, semiconductor device 800 includes a memory array 802 in interconnect layer 804, the memory array 802 including multiple memory structures 806 in interconnect layer 804, and device layer 808 located below interconnect layer 804 and including substrate 810 and dielectric layer 814. In addition, interconnect layer 804 includes multiple ILD layers 818, multiple ESLs 820, multiple metallization structures 826 in multiple layers 822a-822d, and interconnect structures 828 in multiple layers 824a-824c arranged perpendicular to the metallization structures 826 in multiple layers 822a-822d.

[0139] However, as Figures 8A to 8C As shown, the integrated circuit device 812 and its associated contacts are located in the interconnect layer 804, rather than in the substrate 810 of the device layer 808. Therefore, as Figure 8B along Figure 8A The cross-sectional view of section line JJ in the middle and Figure 8C along Figure 8AAs shown in the cross-sectional view by line KK, the integrated circuit device 812 is electrically coupled to the memory structure 806 (including the memory structure 806a in memory layer 830a and the memory structure 806b contained in memory layer 830b), which is a back-end transistor structure. The back-end transistor structure (e.g., integrated circuit device 812) may include a conductive gate structure, a channel layer, a gate dielectric layer between the gate structure and the channel layer, and source / drain electrodes on the opposite side of the channel layer.

[0140] Each gate electrode and source / drain electrode may include conductive materials such as platinum (Pt), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), iron (Fe), nickel (Ni), cobalt (Co), chromium (Cr), beryllium (Be), antimony (Sb), iridium (Ir), molybdenum (Mo), osmium (Os), thorium (Th), vanadium (V), palladium (Pd), copper (Cu), aluminum (Al), ruthenium (Ru), and / or alloys thereof.

[0141] The gate dielectric layer may include one or more high-k dielectric materials, and the dielectric constant of the high-k dielectric material is greater than that of silicon dioxide (SiO2, with a dielectric constant of about 3.9). Examples of such high-k dielectric materials include metal oxide materials, such as hafnium oxide (HfO). x For example, HfO2), aluminum oxide (Al) x O y For example, Al2O3), zirconium oxide (ZrO2) x For example, ZrO2), silicon oxynitride (SiON), and oxide materials containing two or more of europium (Hf), titanium (Ti), lanthanum (La), silicon (Si) and / or zirconium (Zr) (e.g., hafnium titanium oxide (Hf)). x Ti y O z ), europium oxide lanthanum (Hf) x La y O z europium silicon oxide (Hf) x Si y O z ) and / or hafnium zirconium oxide (Hf x Zr y O z Additionally and / or optionally, the gate dielectric layer may include silicon oxide (SiO2), etc. x (e.g., SiO2) and / or low-k dielectric layers.

[0142] The channel layer may include an oxide semiconductor material. Therefore, the back-end transistor (e.g., integrated circuit device 812) may be an oxide-semiconductor field-effect transistor (OSFET). In some embodiments, the oxide semiconductor material includes n-type oxide semiconductor materials, such as tin dioxide (SnO2), indium gallium zinc oxide (InGaZnO or IGZO), indium gallium oxide (InGaO or IGO), indium zinc oxide (InZnO or IZO), indium tungsten oxide (InWO or IWO), and / or indium oxide (In2O3). In some embodiments, the oxide semiconductor material includes p-type oxide semiconductor materials, such as nickel oxide (NiO), copper oxide (Cu2O), aluminum copper oxide (CuAlO2), gallium copper oxide (CuGaO2), indium copper oxide (CuInO2), strontium copper oxide (SrCu2O2), and / or tin oxide (SnO).

[0143] As mentioned above, Figures 8A to 8C Provided as an example, and other examples can be used in conjunction with it. Figures 8A to 8C The differences are as described.

[0144] Figure 9 This is a schematic diagram of an exemplary embodiment 900 of the memory structure 902 disclosed herein. In some embodiments, one or more memory structures 106 (including memory structures 106a and / or 106b), memory structures 306 (including memory structures 306a, 306b, 306c, and / or 306d), memory structures 406 (including memory structures 406a and / or 406b), memory structures 506 (including memory structures 506a, 506b, 506c, and / or 506d), memory structures 606 (including memory structures 606a, 606b, 606c, and / or 606d), memory structures 706 (including memory structures 706a and / or 706b), and / or memory structures 806 (including memory structures 806a and / or 806b) may be implemented as memory structure 902.

[0145] like Figure 9As shown, memory structure 902 may be contained within dielectric layer 904, and dielectric layer 904 may correspond to one or more of ILD layer 118, ILD layer 318, ILD layer 718, and / or ILD layer 818. Memory structure 902 may include a bottom electrode 906, a top electrode 908, and a data storage layer 910 sandwiched between the bottom electrode 906 and the top electrode 908. Electrical inputs (e.g., voltage, current) may be applied to data storage layer 910 through bottom electrode 906 and top electrode 908 to selectively modify one or more properties of data storage layer 910 to edit programs (or write data) or delete logic values ​​stored in data storage layer 910.

[0146] Each bottom electrode 906 and / or top electrode 908 may include one or more conductive materials, such as tantalum nitride (TaN), titanium nitride (TiN), tungsten (W), aluminum (Al), ruthenium (Ru), cobalt (Co), copper (Cu), platinum (Pt), chromium (Cr), beryllium (Be), antimony (Sb), iridium (Ir), molybdenum (Mo), osmium (Os), thorium (Th), vanadium (V), and / or alloys thereof.

[0147] In some embodiments, the memory structure 902 is an RRAM structure, and the data storage layer 910 comprises an insulating material with non-volatile resistance. In other words, the resistance of the data storage layer 910 can be configured to various continuous resistance states. Such an insulating material may include hafnium oxide (HfO). x For example, HfO2), titanium dioxide (TiO2) x For example, TiO2), tantalum oxide (Ta x O y For example, Ta₂O₅), nickel oxide (NiO), zinc oxide (ZnO), zinc titanate (ZnO). x TiO y For example, Zn2TiO4), manganese oxide (MnO) x For example, MnO2), magnesium oxide (MgO), aluminum oxide (Al2O3) x O y For example, Al2O3), and zirconium dioxide (ZrO2). x For example, ZrO2, etc.

[0148] In some embodiments, the memory structure 902 is an MRAM structure or an MTJ structure, and the data storage layer 910 includes a tunnel barrier layer sandwiched between two ferromagnetic layers. This allows the data storage layer 910 to have a non-volatile magnetic polarity. In other words, the data storage layer 910 can be configured to various persistent states of magnetic polarity. The ferromagnetic layer material may include an iron-containing material, including one or more combinations of iron (Fe) and cobalt (Co), boron (B), and / or nickel (Ni). The tunnel barrier layer may include magnesium oxide (MgO) and / or other suitable materials.

[0149] In some embodiments, the memory structure 902 is an FeRAM structure or an FTJ structure, and the data storage layer 910 includes a ferroelectric layer to selectively store information based on the polarization of the data storage layer 910. Examples of ferroelectric materials disposed in the data storage layer 910 include hafnium oxide (e.g., HfO or HfO2), zirconium oxide (e.g., ZrO2), HfZrO, or HZO (e.g., HfO2). x Zr 1- x O y Where x is between 0 and 1, for example, Hf 0.5 Zr 0.5 O2), hafnium silicon oxide (e.g., HfSiO), hafnium lanthanum oxide (e.g., HfLaO), aluminum nitride (AlN), aluminum scandium nitride (e.g., AlScN), PBT (e.g., PbZrO3), PZT (e.g., Pb[Zr]O3). x Ti 1-x O3, (0≤x≤1), PLZT (e.g., Pb) 1-x La x Zr 1-y Ti y O3), barium titanate (e.g., BaTiO3), lead titanate (e.g., PbTiO3), lead metaniobate (e.g., PbNb2O6), lithium niobate (e.g., LiNbO3), lithium tantalate (e.g., LiTaO3), PMN (e.g., PbMg) 1-3 Nb 2 / 3 O3), PST (e.g., PbSc) 1 / 2 Ta 1 / 2 O3), SBT (e.g., SrBi2Ta2O9), BNT (e.g., Bi 1 / 2 Na 1 / 2 TiO3), and / or combinations thereof. In some embodiments, the ferroelectric material may include dopants such as scandium (Sc), lanthanum (La), calcium (Ca), barium (Ba), yttrium (Y), styrene (Sr), and / or gadolinium (Gd).

[0150] In some embodiments, the memory structure 902 is a capacitor structure for a DRAM cell, and the data storage layer 910 optionally forms an insulating layer between the bottom electrode 906 and the top electrode 908 to form a metal-insulator-metal (MIM) capacitor. The MIM capacitor can be a thin-film capacitor structure, a deep trench capacitor (DTC) structure, and / or other types of capacitor structures. In some embodiments, the insulating layer is a low-k dielectric layer, such as silicon oxide (SiO2). x (e.g., SiO2). In some embodiments, the insulating layer may include a high-k dielectric layer, such as hafnium oxide (HfO). x For example, HfO2), lanthanum oxide (La) x O y For example, La2O3), and / or zirconium oxide (ZrO2). x For example, ZrO2, etc.

[0151] As mentioned above, Figure 9 Provided as an example, and other examples can be used in conjunction with it. Figure 9 The differences are as described.

[0152] Figure 10 This is a flowchart of an exemplary process 1000 related to the formation of the semiconductor device described herein. In some embodiments, one or more semiconductor processing tools are used to perform the process. Figure 10 One or more processing steps, wherein the semiconductor processing tools are, for example, deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / bare die transport tools, and / or other types of semiconductor processing tools.

[0153] like Figure 10 As shown, process 1000 may include forming one or more integrated circuit devices in or over a substrate of a semiconductor device (step 1010). For example, one or more semiconductor processing tools may be configured to form one or more integrated circuit devices (e.g., integrated circuit device 112, integrated circuit device 312, integrated circuit device 712, integrated circuit device 812) in or over a substrate (e.g., substrate 110, substrate 310, substrate 710, substrate 810) of a semiconductor device (e.g., semiconductor device 100, semiconductor device 300, semiconductor device 400, semiconductor device 800), as described above.

[0154] Further as Figure 10As shown, process 1000 may include forming a first conductive structure of an interconnect layer over a substrate (step 1020). For example, one or more semiconductor processing tools may be configured to form a first conductive structure (e.g., a layer 124b of interconnect structure 128, a layer 324b of interconnect structure 328, a layer 324c of interconnect structure 328, a layer 324d of interconnect structure 328, a layer 722b of metallization structure 726, and a layer 824b of interconnect structure 828) of interconnect structure 328 over a substrate, as described above.

[0155] Further as Figure 10 As shown, process 1000 may include forming a first memory layer comprising a first plurality of memory structures in a first conductive structure (step 1030). For example, one or more semiconductor processing tools may be configured to form a first memory layer (e.g., memory layer 130a, memory layer 330a, memory layer 330b, memory layer 330c, memory layer 730a, memory layer 830a) comprising a first plurality of memory structures (e.g., memory structures 106a, 306a, 306b, 306c, 406a, 506a, 506b, 506c, 606a, 606b, 606c, 706a, 806a, 902) in a first conductive structure.

[0156] Further as Figure 10 As shown, process 1000 may include forming a second conductive structure (step 1040) over the first conductive structure, which is an interconnect layer. For example, one or more semiconductor processing tools may be configured to form a second conductive structure (e.g., a layer 124c of interconnect structure 128, a layer 324c of interconnect structure 128, a layer 324d of interconnect structure 128, a layer 324e of interconnect structure 128, a layer 722c of metallization structure 126, and a layer 824c of interconnect structure 828) over the foregoing.

[0157] Further as Figure 10As shown, process 1000 may include forming a second memory layer containing a second plurality of memory structures in the second conductive structure (step 1050). For example, one or more semiconductor processing tools may be configured to form a second memory layer (e.g., memory layer 130b, memory layer 330b, memory layer 330c, memory layer 330d, memory layer 730b, memory layer 806b, memory structure 902) containing a second plurality of memory structures (e.g., memory structure 106b, memory structure 306b, memory structure 306c, memory structure 306d, memory structure 706b, memory structure 806b, memory structure 902) in the second conductive structure.

[0158] Process 1000 may include additional implementations, such as any single implementation or any combination of implementations that are combined with one or more other processes described in other parts of this disclosure, as described later.

[0159] In a first embodiment, process 1000 includes forming a third conductive structure (e.g., a metallization structure 126 of layer 122c, a metallization structure 326 of layer 322c, an interconnection structure 728 of layer 724b, and a metallization structure 826 of layer 822c) over a first conductive structure, wherein forming a second conductive structure includes forming a second conductive structure over a third conductive structure.

[0160] In the second embodiment, forming the first conductive layer structure, either alone or in combination with the first embodiment, includes forming a first set of conductive structures (e.g., interconnect structures 128a, 328a, metallization structures 726a, and 828) before forming the first memory layer, and forming a second set of conductive structures (e.g., interconnect structures 128, 128b, 328, 328b, 726, 726b, 828, and 828b) after forming the first memory layer.

[0161] In the third embodiment, forming a first memory layer, either alone or in combination with one or more of the first and second embodiments, includes forming a first plurality of memory structures on a first group of conductive structures of the first layer conductive structure.

[0162] In the fourth embodiment, each first plurality of memory structures is electrically coupled to a corresponding plurality of the first group of conductive structures in the first conductive structure, either alone or in combination with one or more of the first to third embodiments. Furthermore, each second plurality of memory structures is electrically coupled to a corresponding plurality of the second group of conductive structures in the first conductive structure. The second group of conductive structures is different from the first group of conductive structures.

[0163] In the fifth embodiment, process 1000 includes, alone or in combination with one or more of the first to fourth embodiments, a third conductive structure (e.g., an interconnect structure 328 of layer 324d) forming an interconnect layer above the second conductive structure, a third memory layer (e.g., memory layer 330c) forming in the third conductive structure including a third plurality of memory structures (e.g., memory structure 306c, memory structure 506c, memory structure 606c), a fourth conductive structure (e.g., an interconnect structure 328 of layer 324e) forming an interconnect layer above the third conductive structure, and a second memory layer (e.g., memory layer 330d) forming in the second conductive structure layer including a second plurality of memory structures (e.g., memory structure 306d, memory structure 506d, memory structure 606d).

[0164] Although Figure 10 Exemplary steps of process 1000 are illustrated, but in some embodiments, process 1000 includes... Figure 10 The steps shown in the diagram can be more steps, fewer steps, different steps, or steps with different settings compared to the steps depicted.

[0165] In this way, memory cells in a memory array within the interconnect layer of a semiconductor device can be disposed on multiple vertically arranged multilayers within the interconnect layer. For example, a first subset of the memory cells in the memory array can be contained within a first conductive layer of the interconnect layer, and a second subset of the memory cells can be contained within a second conductive layer of the interconnect layer. This enables a three-dimensional array of memory cells within the interconnect layer of the semiconductor device, thus providing a larger lateral area for memory cells in each metallization layer. Consequently, a high density of memory cells can be achieved in the memory array without sacrificing the size of the memory cells and / or the spacing between them, resulting in more stable operation and a longer operating life.

[0166] As described in more detail above, some embodiments of this disclosure provide a semiconductor device. The semiconductor device includes a semiconductor substrate. The semiconductor device includes an interconnect layer located above the semiconductor substrate. The semiconductor device includes a memory array in the interconnect layer. The memory array includes a first memory layer, and each of the first memory layers includes a first plurality of memory structures located at a first vertical height in the interconnect layer. The memory array includes a second memory layer, and the second memory layer includes a second plurality of memory structures, each of the second plurality of memory structures located at a second vertical height in the interconnect layer, wherein the first vertical height and the second vertical height are different vertical heights. In some embodiments, the interconnect layer includes a multilayer conductive structure, the first memory layer is included in a first conductive layer of the multilayer conductive structure, the second memory layer is included in a second conductive layer of the multilayer conductive structure, and the second conductive layer is located above the first conductive layer. In some embodiments, a third conductive layer of the multilayer conductive structure is vertically located between the first conductive layer and the second conductive layer. In some embodiments, the first memory structure of the first plurality of memory structures is laterally offset in the semiconductor device in a first lateral direction and a second lateral direction relative to the second memory structure of the second plurality of memory structures. In some embodiments, the first memory structure of the first plurality of memory structures at least partially overlaps laterally with the second memory structure of the second plurality of memory structures. In some embodiments, each of the first plurality of memory structures has a first top-view shape, each of the second plurality of memory structures includes a second top-view shape, and the first top-view shape and the second top-view shape are different top-view shapes. In some embodiments, each of the first plurality of memory structures has a first top-view area, each of the second plurality of memory structures includes a second top-view area, and the second top-view area is larger than the first top-view area.

[0167] As described in more detail above, some embodiments of this disclosure provide a semiconductor device. The semiconductor device includes a semiconductor substrate. The semiconductor device includes an interconnect layer located above the semiconductor substrate. The interconnect layer includes a multilayer interconnect structure and a multilayer metallization structure perpendicularly alternating with the multilayer interconnect structure. The semiconductor device includes a memory array located within the interconnect layer. The memory array includes a first memory layer, and the first memory layer includes a first plurality of memory structures, each of which is located within a first interconnect structure of the multilayer interconnect structure. The memory array includes a second memory layer, and the second memory layer includes a second plurality of memory structures, each of which is located within a second interconnect structure of the multilayer interconnect structure. A metallization structure of one layer of the multilayer metallization structure is perpendicularly located between the first interconnect structure and the second interconnect structure. In some embodiments, the semiconductor device further includes a third memory layer, the third memory layer including a third plurality of memory structures, each of which is located within a third interconnect structure of the multilayer interconnect structure, and another metallization structure of the multilayer metallization structure is perpendicularly located between the second interconnect structure and the third interconnect structure. In some embodiments, a first portion of the first memory structure of the first plurality of memory structures partially overlaps laterally with a portion of the second memory structure of the second plurality of memory structures, and a second portion of the first memory structure partially overlaps laterally with a portion of the third memory structure of the third plurality of memory structures. In some embodiments, the first portion of the first memory structure of the first plurality of memory structures partially overlaps laterally with the first portion of the second memory structure of the second plurality of memory structures, but does not overlap with the third memory structure of the third plurality of memory structures; the second portion of the first memory structure partially overlaps laterally with the first portion of the third memory structure, but does not overlap with the second memory structure; and the third portion of the first memory structure partially overlaps laterally with the second portions of the second and third memory structures. In some embodiments, two or more layers of metallized structures of the multilayer metallized structure are vertically located between the first interconnect structure and the second interconnect structure. In some embodiments, the first memory structure of the first plurality of memory structures at least partially overlaps laterally with a first side of the second memory structure in the second plurality of memory structures, and the third memory structure of the first plurality of memory structures at least partially overlaps laterally with a second side of the second memory structure opposite to the first side. In some embodiments, the first memory structure of the first plurality of memory structures at least partially overlaps laterally with the second memory structure of the second plurality of memory structures, the third memory structure of the first plurality of memory structures at least partially overlaps laterally with the second memory structure, and both the first memory structure and the third memory structure at least partially overlap laterally with the same side of the second memory structure.

[0168] As described in more detail above, some embodiments of this disclosure provide a method for forming a semiconductor device. The method includes forming one or more integrated circuit devices in a substrate of the semiconductor device. The method includes forming a first conductive structure of an interconnect layer over the substrate. The method includes forming a first memory layer including a first plurality of memory structures in the first conductive structure. The method includes forming a second conductive structure of an interconnect layer over the first conductive structure. The method includes forming a second memory layer including a second plurality of memory structures in the second conductive structure. In some embodiments, the method further includes forming a third conductive structure of an interconnect layer over the first conductive structure, and forming the second conductive structure includes forming a second conductive structure over the third conductive structure. In some embodiments, forming the first conductive structure includes forming a first set of conductive structures of the first conductive structure before forming the first memory layer; and forming a second set of conductive structures of the first conductive structure after forming the first memory layer. In some embodiments, forming the first memory layer includes forming a first plurality of memory structures on the first set of conductive structures of the first conductive structure. In some embodiments, each of the first plurality of memory structures is electrically coupled to a corresponding entity in a first group of conductive structures of the first conductive layer, and each of the second plurality of memory structures is electrically coupled to a corresponding entity in a second group of conductive structures of the first conductive layer, wherein the second group of conductive structures is different from the first group of conductive structures. In some embodiments, the method further includes forming a third conductive layer with an interconnect layer above the second conductive layer, forming a third memory layer containing the third plurality of memory structures in the third conductive layer, forming a fourth conductive layer with an interconnect layer above the third conductive layer, and forming a second memory layer containing the second plurality of memory structures in the second conductive layer.

[0169] As described in more detail above, some embodiments of this disclosure provide a semiconductor device. The semiconductor device includes a substrate containing an integrated circuit device, the integrated circuit device being located in or above the substrate. The semiconductor device also includes an interconnect layer located above the substrate, the interconnect layer comprising multiple vertically conductive layers. The semiconductor device further includes a first plurality of memory structures and a second plurality of memory structures located in the vertically conductive layers, the first plurality of memory structures having a first height, the second plurality of memory structures having a second height, and the second height being greater than the first height. In some embodiments, each of the first plurality of memory structures is electrically coupled to a corresponding portion of a first set of conductive structures of the first conductive layer, and each of the second plurality of memory structures is electrically coupled to a corresponding portion of a second set of conductive structures of the first conductive layer, the second set of conductive structures being different from the first set of conductive structures.

[0170] The terms “approximately” and “substantially” can mean a given quantity that varies within 5% of that value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%). These values ​​are merely illustrative and are not intended to limit this disclosure. It should be understood that, according to this disclosure, the terms “approximately” and “substantially” can mean a percentage of a given quantity.

[0171] The foregoing has outlined the features of several embodiments to enable those skilled in the art to better understand the various implementations of this disclosure. Those skilled in the art should understand that this disclosure can easily serve as the basis for designing or modifying other processes and structures to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent structures do not depart from the spirit and scope of this disclosure, and various modifications, substitutions, and alterations can be made without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, include: A semiconductor substrate; An interconnect layer is located above the semiconductor substrate; as well as A memory array, located in the interconnect layer, and the memory array includes: A first memory layer includes a first plurality of memory structures, each of the first plurality of memory structures being located at a first vertical height in the interconnect layer; as well as A second memory layer includes a second plurality of memory structures, each of which is located at a second vertical height in the interconnect layer. The first vertical height and the second vertical height are different vertical heights.

2. The semiconductor device as claimed in claim 1, characterized in that, The interconnect layer comprises a multilayer conductive structure; The first memory layer is included in a first conductive layer of the multilayer conductive structure; The second memory layer is included in a second conductive layer of the multilayer conductive structure; and The second conductive layer is located above the first conductive layer.

3. The semiconductor device as claimed in claim 1, characterized in that, Relative to the second memory structure of the second plurality of memory structures, the first memory structure of the first plurality of memory structures is laterally offset in the semiconductor device in a first lateral direction and a second lateral direction.

4. The semiconductor device as claimed in claim 1, characterized in that, The first memory structure of the first plurality of memory structures at least partially overlaps laterally with the second memory structure of the second plurality of memory structures.

5. The semiconductor device as claimed in claim 1, characterized in that, Each of the first plurality of memory structures has a first top-view shape; Each of the second plurality of memory structures includes a second top-view shape; and The first top view shape and the second top view shape are different top view shapes.

6. A semiconductor device, characterized in that, include: A semiconductor substrate; An interconnect layer is located above the semiconductor substrate and includes: Multilayer interconnect structure; and A multilayer metallized structure, alternating perpendicularly with the multilayer interconnect structure; and A memory array, located in the interconnect layer, includes: A first memory layer, comprising a first plurality of memory structures, each of the first plurality of memory structures being located in a first layer interconnect structure of the multilayer interconnect structure; and A second memory layer includes a second plurality of memory structures, each of which is located in a second layer interconnect structure of the multilayer interconnect structure. The metallized layer of the multilayer metallized structure is vertically located between the first interconnect layer and the second interconnect layer.

7. The semiconductor device as claimed in claim 6, characterized in that, Further includes: A third memory layer includes a third plurality of memory structures, each of which is located in a third layer interconnect structure of the multilayer interconnect structure. The other metallized layer of the multilayer metallized structure is located vertically between the second interconnect structure and the third interconnect structure.

8. The semiconductor device as claimed in claim 7, characterized in that, A first portion of a first memory structure of the first plurality of memory structures partially overlaps laterally with a first portion of a second memory structure of the second plurality of memory structures, but does not overlap with a third memory structure of the third plurality of memory structures. A second portion of the first memory structure partially overlaps laterally with a first portion of the third memory structure, but does not overlap with the second memory structure; and The third part of the first memory structure partially overlaps laterally with the second part of the second memory structure and the second part of the third memory structure.

9. A semiconductor device, characterized in that, include: A substrate, comprising an integrated circuit device, wherein the integrated circuit device is located in or above the substrate; An interconnect layer is located above the substrate and includes multiple vertical conductive layers; A first plurality of memory structures, located within the multilayer vertical conductive layers, and having a first height; and A second plurality of memory structures are located in the multilayer vertical conductive layers and have a second height, wherein the second height is greater than the first height.

10. The semiconductor device as claimed in claim 9, characterized in that, Each of the first plurality of memory structures is electrically coupled to a corresponding one in a first set of conductive structures; and Each of the second plurality of memory structures is electrically coupled to a corresponding one of a second set of conductive structures, and the second set of conductive structures is different from the first set of conductive structures.

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