Thin film transistor array and display device including same

Abstract

Disclosed are a thin film transistor array and a display device including the same. The thin film transistor array includes: a first gate line extending in a first direction; a first data line and a second data line each extending in a second direction; a first write transistor connected to the first gate line and the first data line; a second write transistor connected to the first gate line and the second data line, and arranged in the first direction with the first write transistor; a first driving transistor connected to the first write transistor and arranged in a second direction with the first write transistor; a second driving transistor connected to the second write transistor, arranged in the first direction with the first driving transistor, and arranged in the second direction with the second write transistor; and a first operation control transistor connected to the first driving transistor and the second driving transistor, and arranged in the second direction with the first driving transistor. The integration level of the pixel circuit in the thin film transistor array can be relatively improved.

Description

Technical Field

[0001] Some embodiments relate to a thin-film transistor array, a display device including the same, and an electronic device including the display device. Background Technology

[0002] With the advancement of the information society, consumer demand for display devices used to display images is increasing in various forms. Examples of display devices include flat panel display devices, such as liquid crystal displays, field emission displays, and light-emitting displays.

[0003] The light-emitting display device may be an organic light-emitting display device that includes an organic light-emitting diode element that operates as a light-emitting element, an inorganic light-emitting display device that includes an inorganic semiconductor element that operates as a light-emitting element, or a light-emitting diode (LED) display device that includes an ultra-small light-emitting diode element (or a micro light-emitting diode element) that operates as a light-emitting element.

[0004] The information disclosed in this background section is only intended to enhance the understanding of the background art, and therefore the information discussed in this background section does not necessarily constitute prior art. Utility Model Content

[0005] The purpose of this invention is to provide a thin-film transistor array with relatively improved pixel circuit integration.

[0006] Some embodiments include a display device that includes the thin-film transistor array.

[0007] Some embodiments include an electronic device that includes the display device.

[0008] Additional aspects of some embodiments of this disclosure will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practice of the inventive concept.

[0009] A thin-film transistor array according to some embodiments may include: a first gate line extending in a first direction; a first data line extending in a second direction intersecting the first direction; a second data line extending in the second direction and spaced apart from the first data line in the first direction; a first data write transistor electrically connected to the first gate line and the first data line; a second data write transistor electrically connected to the first gate line and the second data line and positioned with the first data write transistor in the first direction; a first driving transistor electrically connected to the first data write transistor and positioned with the first data write transistor in the second direction; a second driving transistor electrically connected to the second data write transistor, positioned with the first driving transistor in the first direction and positioned with the second data write transistor in the second direction; and a first operation control transistor electrically connected to the first driving transistor and the second driving transistor and positioned with the first driving transistor in the second direction.

[0010] According to some embodiments, the first data write transistor, the first drive transistor, and the first operation control transistor may be arranged in a line along a second direction. According to some embodiments, the second data write transistor and the second drive transistor may be arranged in a line along the second direction.

[0011] According to some embodiments, the thin-film transistor array may further include: a first compensation transistor electrically connected to the first data write transistor and the first drive transistor, and positioned in a direction opposite to the second direction; a first emitter control transistor electrically connected to the first drive transistor and the first compensation transistor, and positioned in a direction opposite to the second direction; and a first initialization transistor electrically connected to the first emitter control transistor, and positioned in a direction opposite to the second direction. According to some embodiments, the first initialization transistor, the first emitter control transistor, the first compensation transistor, the first data write transistor, the first drive transistor, and the first operation control transistor may be arranged in a line along the second direction.

[0012] According to some embodiments, the thin-film transistor array may further include: a second compensation transistor electrically connected to the second data write transistor and the second drive transistor, and positioned in a direction opposite to the second direction; a second emitter control transistor electrically connected to the second drive transistor and the second compensation transistor, and positioned in a direction opposite to the second direction; and a second initialization transistor electrically connected to the second emitter control transistor, and positioned in a direction opposite to the second direction. According to some embodiments, the second initialization transistor, the second emitter control transistor, the second compensation transistor, the second data write transistor, and the second drive transistor may be arranged in a line along the second direction.

[0013] According to some embodiments, a second compensation transistor may be positioned relative to a first compensation transistor in a first direction. According to some embodiments, a second emitter control transistor may be positioned relative to a first emitter control transistor in a first direction. According to some embodiments, a second initialization transistor may be positioned relative to a first initialization transistor in a first direction.

[0014] According to some embodiments, the thin-film transistor array may further include a first connection line that electrically connects the drain region of the first operating control transistor, the source region of the first driving transistor, and the source region of the second driving transistor to each other.

[0015] According to some embodiments, the first connection line may be arranged on the same layer as the first gate line.

[0016] According to some embodiments, the thin-film transistor array may further include: a second gate line extending in a first direction and spaced apart from the first gate line in a second direction; a third data write transistor electrically connected to the second gate line and the first data line and positioned with the first operation control transistor in the second direction; a fourth data write transistor electrically connected to the second gate line and the second data line and positioned with the third data write transistor in the first direction; a third drive transistor electrically connected to the third data write transistor and positioned with the first operation control transistor in the second direction; a fourth drive transistor electrically connected to the fourth data write transistor and positioned with the third drive transistor in the first direction; and a second operation control transistor electrically connected to the third drive transistor and the fourth drive transistor and positioned with the first operation control transistor in the first direction.

[0017] According to some embodiments, the second operation control transistor may be located between the second driving transistor and the fourth driving transistor.

[0018] According to some embodiments, the first data write transistor, the first driving transistor, the first operation control transistor, the third data write transistor, and the third driving transistor can be arranged in a line along a second direction. According to some embodiments, the second data write transistor, the second driving transistor, the second operation control transistor, the fourth data write transistor, and the fourth driving transistor can be arranged in a line along the second direction.

[0019] According to some embodiments, the third data write transistor may be positioned between the first operation control transistor and the third drive transistor. According to some embodiments, the fourth data write transistor may be positioned between the second operation control transistor and the fourth drive transistor.

[0020] According to some embodiments, a third driving transistor may be positioned between a first operation control transistor and a third data write transistor. According to some embodiments, a fourth driving transistor may be positioned between a second operation control transistor and a fourth data write transistor.

[0021] According to some embodiments, the thin-film transistor array may further include a second connection line that electrically connects the drain region of the second operating control transistor, the source region of the third driving transistor, and the source region of the fourth driving transistor to each other.

[0022] According to some embodiments, the second connection line may be on the same layer as the first gate line and the second gate line.

[0023] According to some embodiments, the thin-film transistor array may further include an emitter control line extending in a first direction and configured to provide an emitter control signal to the gate electrode of a first operating control transistor and the gate electrode of a second operating control transistor. According to some embodiments, a second connection line may intersect the emitter control line in a planar view.

[0024] According to some embodiments, the transmit control line may include: a first extension portion, which is stacked with the gate electrode of a first operating control transistor in a plan view; a second extension portion, which is on the same layer as the first extension portion, spaced apart from the first extension portion in a first direction, and stacked with the gate electrode of a second operating control transistor in a plan view; and a bridge electrode, which is on a different layer from the first and second extension portions and electrically connects the first and second extension portions to each other. According to some embodiments, the second connection line may cross the bridge electrode in a plan view.

[0025] A thin-film transistor array according to some embodiments may include: a first gate line extending in a first direction; a second gate line extending in the first direction and spaced apart from the first gate line in a second direction intersecting the first direction; a first data line extending in the second direction; a second data line extending in the second direction and spaced apart from the first data line in the first direction; a first driving transistor electrically connected to the first gate line and the first data line; a second driving transistor electrically connected to the first gate line and the second data line and positioned with the first driving transistor in the first direction; a third driving transistor electrically connected to the second gate line and the first data line and positioned with the first driving transistor in the second direction; a fourth driving transistor electrically connected to the second gate line and the second data line, positioned with the third driving transistor in the first direction and positioned with the second driving transistor in the second direction; a first operation control transistor electrically connected to the first driving transistor and the second driving transistor and positioned between the first driving transistor and the third driving transistor; and a second operation control transistor electrically connected to the third driving transistor and the fourth driving transistor and positioned between the second driving transistor and the fourth driving transistor.

[0026] According to some embodiments, the thin-film transistor array may further include: a first connecting line electrically connecting the drain region of the first operation control transistor, the source region of the first driving transistor, and the source region of the second driving transistor to each other; and a second connecting line electrically connecting the drain region of the second operation control transistor, the source region of the third driving transistor, and the source region of the fourth driving transistor to each other.

[0027] A display device according to some embodiments may include: a first light-emitting element to a fourth light-emitting element, adjacent to each other; a first driving transistor electrically connected to the first light-emitting element; a second driving transistor electrically connected to the second light-emitting element and positioned with the first driving transistor in a first direction; a third driving transistor electrically connected to the third light-emitting element and positioned with the first driving transistor in a second direction intersecting the first direction; a fourth driving transistor electrically connected to the fourth light-emitting element, positioned with the third driving transistor in the first direction and positioned with the second driving transistor in the second direction; a first operation control transistor electrically connected to the first driving transistor and the second driving transistor and positioned between the first driving transistor and the third driving transistor; and a second operation control transistor electrically connected to the third driving transistor and the fourth driving transistor and positioned between the second driving transistor and the fourth driving transistor.

[0028] According to some embodiments, the thin-film transistor array may further include a first connection line electrically connecting the drain region of the first operation control transistor, the source region of the first driving transistor, and the source region of the second driving transistor to each other, and a second connection line electrically connecting the drain region of the second operation control transistor, the source region of the third driving transistor, and the source region of the fourth driving transistor to each other.

[0029] According to some embodiments, a thin-film transistor array may include a plurality of pixel circuits. According to some embodiments, the thin-film transistors included in each of the pixel circuits may be arranged in a line along one direction.

[0030] An electronic device according to some embodiments may include a display device and a power supply configured to provide power to the display device. The display device may include: first to fourth light-emitting elements, adjacent to each other; a first driving transistor electrically connected to the first light-emitting element; a second driving transistor electrically connected to the second light-emitting element and positioned in a first direction with the first driving transistor; a third driving transistor electrically connected to the third light-emitting element and positioned in a second direction intersecting the first direction with the first driving transistor; a fourth driving transistor electrically connected to the fourth light-emitting element, positioned in the first direction with the third driving transistor and positioned in the second direction with the second driving transistor; a first operation control transistor electrically connected to the first and second driving transistors and positioned between the first and third driving transistors; and a second operation control transistor electrically connected to the third and fourth driving transistors and positioned between the second and fourth driving transistors.

[0031] According to some embodiments, impurities can be relatively easily doped into the semiconductor substrate during the fabrication process of the thin-film transistor array. Furthermore, adjacent pixel circuits can share at least one thin-film transistor. Therefore, the integration density of the pixel circuits in the thin-film transistor array can be relatively improved. Consequently, the resolution and display quality of display devices including thin-film transistor arrays can be relatively improved.

[0032] It will be understood that both the foregoing general description and the following detailed description are illustrative and intended to provide further explanation of the claimed utility model. Attached Figure Description

[0033] The accompanying drawings are included to provide a further understanding of the utility model and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the utility model and, together with the specification, serve to explain the utility model.

[0034] Figure 1 This is a plan view illustrating a display device according to some embodiments.

[0035] Figure 2 yes Figure 1 A cross-sectional view of the display device.

[0036] Figure 3 This is a plan view illustrating a thin-film transistor array according to some embodiments.

[0037] Figure 4 It is shown that it includes Figure 3 The circuit diagrams of the first and second pixel circuits in the thin-film transistor array.

[0038] Figure 5 It is shown that it includes Figure 3 Circuit diagrams of the third and fourth pixel circuits in a thin-film transistor array.

[0039] Figure 6 It is schematically shown that includes Figure 3 A plan view of an example of the first to fourth pixel circuits in a thin-film transistor array.

[0040] Figures 7 to 11 It is shown Figure 6 The layout diagram of the first pixel circuit.

[0041] Figure 12 It is shown Figure 6 The layout diagram of the first pixel circuit to the fourth pixel circuit.

[0042] Figure 13 and Figure 14 It is shown Figure 6 A magnified view of region A.

[0043] Figure 15 It is schematically shown that includes Figure 3 A plan view of an example of the first to fourth pixel circuits in a thin-film transistor array.

[0044] Figure 16 It is shown Figure 15 A magnified view of region B.

[0045] Figure 17 This is a block diagram illustrating an electronic device according to some embodiments. Detailed Implementation

[0046] The invention will now be described more fully below with reference to the accompanying drawings, in which various embodiments are illustrated. However, the invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The same reference numerals throughout refer to the same elements.

[0047] It will be understood that when an element is referred to as being related to another element (such as "on" another element), it can be directly on said other element, or there can be an intermediary element between them. Conversely, when an element is referred to as being related to another element (such as "directly on" another element), there is no intermediary element.

[0048] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another. Therefore, without departing from the teaching herein, the first element, first component, first region, first layer, or first part discussed below may be referred to as a second element, second component, second region, second layer, or second part.

[0049] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, “a,” “an,” “the,” and “at least one” do not indicate a limitation of quantity and are intended to include both singular and plural forms. For example, unless the context clearly indicates otherwise, “an element” has the same meaning as “at least one element.” “At least one” should not be construed as limited to “a” or “an.” “Or” means “and / or.” As used herein, reference numerals may indicate a single element or multiple elements. For example, reference numerals that denote elements in the singular form in the drawings may be used in the context of the specification to indicate multiple single elements.

[0050] As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will also be understood that when the terms “comprising,” “including,” and / or “variations thereof” are used in this specification, it indicates the presence of the stated features, areas, integrals, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or groups thereof.

[0051] Furthermore, relative terms such as “below” or “bottom” and “above” or “top” may be used here to describe the relationship between one element and another as shown in the figure. It will be understood that, in addition to the orientation depicted in the figure, the relative terms are intended to cover different orientations of the device. For example, if a device in one of the figures is flipped, an element described as being “below” the other element will subsequently be oriented “above” the other element. Thus, the term “below” can cover both “below” and “above” orientations, depending on the specific orientation of the figure. Similarly, if a device in one of the figures is flipped, an element described as being “below” or “under” the other element will subsequently be oriented “above” the other element. Thus, the terms “below” or “under” can cover both above and below orientations.

[0052] Given the measurements discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), the terms “about” or “approximately” as used herein include the stated value and refer to an acceptable deviation from the particular value as determined by one of ordinary skill in the art. For example, “about” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0053] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms (such as those defined in common dictionaries) shall be interpreted as having the same meaning as they have in the relevant field and in the context of this disclosure, and shall not be interpreted in an idealized or overly formal sense, unless expressly defined herein.

[0054] Embodiments are described herein with reference to sectional views that are schematic illustrations of idealized examples. Thus, variations in the illustrated shapes, for example, due to manufacturing techniques and / or tolerances, will be expected. Therefore, the embodiments described herein should not be construed as limited to the specific shapes of the areas shown herein, but rather include shape deviations, for example, due to manufacturing processes. For example, areas shown or described as flat may generally have rough and / or non-linear characteristics. Furthermore, the sharp corners shown may be rounded. Therefore, the areas shown in the figures are schematic in nature, and their shapes are not intended to show the precise shapes of the areas, nor are they intended to limit the scope of the presented claims.

[0055] The illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0056] Figure 1 This is a plan view illustrating a display device according to some embodiments.

[0057] Reference Figure 1 According to some embodiments, the display device DD may have a display surface for displaying images. For example, the display surface may be parallel to (or substantially parallel to) a plane defined by a first direction DR1 and a second direction DR2 intersecting the first direction DR1, but the embodiments are not limited thereto. The display device DD may display images on a third direction DR3 through the display surface. For example, the second direction DR2 may be perpendicular to the first direction DR1. The third direction DR3 may be parallel to (or substantially parallel to) the normal direction of the display surface. The display surface may correspond to the upper surface (or front surface) of the display device DD.

[0058] The display device DD may include a display area DA and a peripheral area PA. An image may be displayed in the display area DA. Multiple pixels PX used to generate the image may be positioned in the display area DA. For example, each of the pixels PX may emit one of red, green, and blue light.

[0059] Each pixel (PX) may include pixel circuitry and a light-emitting element. The pixel circuitry may include at least one thin-film transistor (TFT) and at least one capacitor. The TFT may generate a drive current and supply the generated drive current to the light-emitting element. The light-emitting element may emit light based on the drive current. For example, the light-emitting element may include (or may be) an organic light-emitting diode (OLED), an inorganic light-emitting diode (OLED), a quantum dot OLED, etc. An image can be generated by combining the light emitted from each pixel (PX).

[0060] The peripheral region PA can be positioned around the display region DA. Alternatively, the peripheral region PA can be positioned outside the display region DA. For example, the peripheral region PA can surround the display region DA in a plan view. Drivers (e.g., data drivers, gate drivers, etc.) can be positioned within the peripheral region PA. The drivers can provide the display region DA with various drive signals for driving pixels PX, such as drive voltages, gate signals, data signals, etc.

[0061] Figure 2 yes Figure 1 A cross-sectional view of the display device.

[0062] Reference Figure 1 and Figure 2 According to some embodiments, the display device DD may include a thin-film transistor array TA, pixels PX, an insulating layer IL, a pixel defining layer PDL, and an encapsulation layer ENC. Each of the pixels PX may include pixel circuitry PC and a light-emitting element LE electrically connected to the pixel circuitry PC. The light-emitting element LE may include a pixel electrode PE, an emitting layer EL, and a common electrode CE.

[0063] A thin-film transistor array (TA) may include a substrate (SUB) and pixel circuitry (PC) positioned on the substrate (SUB). Although in Figure 2 Only one pixel circuit PC is shown, but multiple pixel circuit PCs can be positioned on the substrate SUB (see reference). Figure 3 ).

[0064] According to some embodiments, the substrate SUB can be a semiconductor substrate. For example, the substrate SUB can include silicon, germanium, or silicon / germanium, or it can be a silicon-on-insulator (SOI) substrate. Multiple active portions can be defined within the substrate SUB. See below for further details. Figure 8 This will be described in detail.

[0065] The pixel circuit PC can be positioned on the substrate SUB. Each of the pixel circuits PC may include various driving elements (e.g., at least one thin-film transistor, at least one capacitor, etc.) and wiring (e.g., gate lines, data lines, etc.) for driving the corresponding one of the light-emitting elements LE.

[0066] The insulating layer IL can be positioned on the thin-film transistor array TA. The insulating layer IL can include organic insulating materials and / or inorganic insulating materials.

[0067] Pixel electrodes PE can be positioned on insulating layer IL. For example, multiple pixel electrodes PE can be positioned on insulating layer IL to correspond to pixel circuits PC respectively. Each of the pixel electrodes PE can be electrically connected to a corresponding one in pixel circuit PC through a contact hole penetrating insulating layer IL. For example, pixel electrode PE can be an anode.

[0068] The pixel electrode PE can include conductive materials such as metals, alloys, conductive metal nitrides, conductive metal oxides, and transparent conductive materials. The pixel electrode PE can have a single-layer structure or a multi-layer structure including multiple conductive layers.

[0069] A pixel defining layer (PDL) can be positioned on a pixel electrode (PE). The PDL can cover the peripheral portion of the pixel electrode (PE) and define a pixel opening that exposes the central portion of the pixel electrode (PE). The PDL can include an organic insulating material.

[0070] The emitter layer EL can be positioned on the pixel electrode PE. According to some embodiments, the emitter layer EL can be positioned within a pixel aperture to correspond to the corresponding pixel electrode PE. According to some embodiments, the emitter layer EL can be positioned throughout the entire display area DA. In some embodiments, the emitter layer EL may comprise at least one of an organic emitting material and quantum dots.

[0071] According to some embodiments, the organic emission material may include low-molecular-weight organic compounds or high-molecular-weight organic compounds. Examples of low-molecular-weight organic compounds may include copper phthalocyanine, N,N'-diphenylbenzidine, tris-(8-hydroxyquinoline)aluminum, etc. Examples of high-molecular-weight organic compounds may include poly(3,4-ethylenedioxythiophene), polyaniline, polyphenylenevinylene, polyfluorene, etc. These may be used alone or in combination.

[0072] According to some embodiments, a quantum dot may include a core, which may include group II-VI compounds, group III-V compounds, group IV-VI compounds, group IV elements, and / or group IV compounds. According to some embodiments, the quantum dot may have a core-shell structure comprising a core and a shell surrounding the core. The shell may serve as a protective layer to prevent or reduce chemical denaturation of the core to maintain semiconductor properties, and may also serve as a charged layer to impart electrophoretic properties to the quantum dot.

[0073] The common electrode CE can be positioned on the emitter layer EL. The common electrode CE can also be positioned on the pixel definition layer PDL. The common electrode CE can include a conductive material. For example, the common electrode CE can be a cathode.

[0074] A pixel electrode PE, an emitter layer EL, and a common electrode CE can form a light-emitting element LE. The light-emitting element LE may also include various functional layers (e.g., hole injection layer, hole transport layer, electron transport layer, electron injection layer, etc.) positioned between the pixel electrode PE and the emitter layer EL and / or between the emitter layer EL and the common electrode CE.

[0075] The encapsulation layer ENC can be positioned on the common electrode CE. The encapsulation layer ENC may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. According to some embodiments, the encapsulation layer ENC may include a first inorganic encapsulation layer positioned on the common electrode CE, an organic encapsulation layer positioned on the first inorganic encapsulation layer, and a second inorganic encapsulation layer positioned on the organic encapsulation layer. The encapsulation layer ENC can cover the light-emitting element LE throughout the entire display area DA. The encapsulation layer ENC can prevent or reduce the penetration of contaminants or impurities, moisture, etc., from the outside into the light-emitting element LE.

[0076] The display device DD may also include various functional layers (e.g., touch sensing layer, color filter layer, light-concentrating layer, etc.) positioned on the encapsulation layer ENC.

[0077] Figure 3 This is a plan view illustrating a thin-film transistor array according to some embodiments.

[0078] Reference Figure 3 The thin-film transistor array TA may include multiple pixel circuits PC. According to some embodiments, the pixel circuits PC may be positioned in a matrix along a first direction DR1 and a second direction DR2.

[0079] According to some embodiments, the thin-film transistor array TA may include first pixel circuits to twelfth pixel circuits PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11 and PC12, which are respectively electrically connected to the first light-emitting element to the twelfth light-emitting element.

[0080] The first pixel circuit PC1, the second pixel circuit PC2, the fifth pixel circuit PC5, the sixth pixel circuit PC6, the ninth pixel circuit PC9, and the tenth pixel circuit PC10 can be arranged sequentially along the first direction DR1. The third pixel circuit PC3, the fourth pixel circuit PC4, the seventh pixel circuit PC7, the eighth pixel circuit PC8, the eleventh pixel circuit PC11, and the twelfth pixel circuit PC12 can be arranged sequentially along the first direction DR1. The third pixel circuit PC3, the fourth pixel circuit PC4, the seventh pixel circuit PC7, the eighth pixel circuit PC8, the eleventh pixel circuit PC11, and the twelfth pixel circuit PC12 can be positioned on the second direction DR2, respectively, in relation to the first pixel circuit PC1, the second pixel circuit PC2, the fifth pixel circuit PC5, the sixth pixel circuit PC6, the ninth pixel circuit PC9, and the tenth pixel circuit PC10.

[0081] According to some embodiments, at least some of the first to twelfth light-emitting elements can emit light of different colors.

[0082] For example, the first light-emitting element connected to the first pixel circuit PC1, the third light-emitting element connected to the third pixel circuit PC3, the sixth light-emitting element connected to the sixth pixel circuit PC6, and the eighth light-emitting element connected to the eighth pixel circuit PC8 can all emit red light.

[0083] The second light-emitting element connected to the second pixel circuit PC2, the fourth light-emitting element connected to the fourth pixel circuit PC4, the ninth light-emitting element connected to the ninth pixel circuit PC9, and the eleventh light-emitting element connected to the eleventh pixel circuit PC11 can all emit green light.

[0084] The fifth light-emitting element connected to the fifth pixel circuit PC5, the seventh light-emitting element connected to the seventh pixel circuit PC7, the tenth light-emitting element connected to the tenth pixel circuit PC10, and the twelfth light-emitting element connected to the twelfth pixel circuit PC12 can all emit blue light.

[0085] According to some embodiments, all of the first to twelfth light-emitting elements can emit light of the same color.

[0086] For example, all of the first to twelfth light-emitting elements can emit blue light. A red conversion layer that converts blue light into red light can be positioned on the first, third, sixth, and eighth light-emitting elements, respectively. A green conversion layer that converts blue light into green light can be positioned on the second, fourth, ninth, and eleventh light-emitting elements, respectively.

[0087] In another example, all of the first through twelfth light-emitting elements can emit white light. A red filter that selectively transmits red light can be positioned on the first, third, sixth, and eighth light-emitting elements, respectively. A green filter that selectively transmits green light can be positioned on the second, fourth, ninth, and eleventh light-emitting elements, respectively. A blue filter that selectively transmits blue light can be positioned on the fifth, seventh, tenth, and twelfth light-emitting elements, respectively.

[0088] The first pixel circuit PC1 and the second pixel circuit PC2, which are adjacent to each other on the first direction DR1, can share at least one thin-film transistor. The third pixel circuit PC3 and the fourth pixel circuit PC4, which are adjacent to each other on the first direction DR1, can share at least one thin-film transistor. The fifth pixel circuit PC5 and the sixth pixel circuit PC6, which are adjacent to each other on the first direction DR1, can share at least one thin-film transistor. The seventh pixel circuit PC7 and the eighth pixel circuit PC8, which are adjacent to each other on the first direction DR1, can share at least one thin-film transistor. The ninth pixel circuit PC9 and the tenth pixel circuit PC10, which are adjacent to each other on the first direction DR1, can share at least one thin-film transistor. The eleventh pixel circuit PC11 and the twelfth pixel circuit PC12, which are adjacent to each other on the first direction DR1, can share at least one thin-film transistor.

[0089] In the following text, reference will be made to Figures 4 to 17 The first to fourth pixel circuits PC1, PC2, PC3, and PC4, which are adjacent to each other in the first direction DR1 and the second direction DR2, are described in more detail below. The description of the first to fourth pixel circuits PC1, PC2, PC3, and PC4 described below can be applied equivalently (or substantially equivalently) or similarly to the fifth to eighth pixel circuits PC5, PC6, PC7, and PC8, and the ninth to twelfth pixel circuits PC9, PC10, PC11, and PC12.

[0090] Figure 4 It is shown that it includes Figure 3 The circuit diagrams of the first and second pixel circuits in the thin-film transistor array. Figure 5 It is shown that it includes Figure 3Circuit diagrams of the third and fourth pixel circuits in a thin-film transistor array.

[0091] The first to fourth pixel circuits PC1, PC2, PC3, and PC4 can have the same (or substantially the same) or similar structure. Therefore, the following description focuses on the first pixel circuit PC1, and some repetitive descriptions can be omitted or simplified.

[0092] Reference Figure 4 According to some embodiments, the first pixel circuit PC1 connected to the first light-emitting element LE1 may include a first driving transistor T1a, a first data writing transistor T2a, a first compensation transistor T3a, a first emission control transistor T4a, a first initialization transistor T5a, a first operation control transistor T6a, a first-first capacitor CA1a, and a first-second capacitor CA2a.

[0093] The first driving transistor T1a may include a gate electrode connected to the first gate node NGa, a first electrode connected to the first source node NSa, and a second electrode connected to the first drain node NDa.

[0094] According to some embodiments, the first driving transistor T1a may be a dual transistor including a first-first driving transistor T1-1a and a first-second driving transistor T1-2a. The first-first driving transistor T1-1a may include a gate electrode connected to a first gate node NGa, a first electrode connected to a first source node NSa, and a second electrode connected to the first electrode of the first-second driving transistor T1-2a. The first-second driving transistor T1-2a may include a gate electrode connected to the first gate node NGa, a first electrode connected to the second electrode of the first-first driving transistor T1-1a, and a second electrode connected to a first drain node NDa.

[0095] The first data write transistor T2a may include a gate electrode configured to receive a data write gate signal GW, a first electrode configured to receive a first data voltage VDATA1, and a second electrode connected to the first electrode of the first capacitor CA1a.

[0096] The first compensation transistor T3a may include a gate electrode configured to receive a compensation gate signal GC, a first electrode connected to a first gate node NGa, and a second electrode connected to a first drain node NDa.

[0097] The first emitter control transistor T4a may include a gate electrode configured to receive a first emitter control signal EM1, a first electrode connected to a first drain node NDa, and a second electrode connected to a first anode node NAa.

[0098] The first initialization transistor T5a may include a gate electrode configured to receive an initialization gate signal GR, a first electrode configured to receive an initialization voltage VINT, and a second electrode connected to the first anode node NAa.

[0099] The first operation control transistor T6a may include a gate electrode configured to receive a second transmit control signal EM2, a first electrode configured to receive a first power voltage ELVDD, and a second electrode connected to a first source node NSa. The first power voltage ELVDD may be a high power voltage.

[0100] The first capacitor CA1a may include a first electrode connected to the second electrode of the first data write transistor T2a and a second electrode connected to the first gate node NGa.

[0101] The first-second capacitor CA2a may include a first electrode configured to receive a first electrical voltage ELVDD and a second electrode connected to a first gate node NGa.

[0102] The first light-emitting element LE1 may include a first electrode connected to a first anode node NAa and a second electrode configured to receive a second electrical voltage ELVSS. The second electrical voltage ELVSS may be a low electrical voltage. The second electrical voltage ELVSS may be lower than the first electrical voltage ELVDD. For example, the first electrode of the first light-emitting element LE1 may be... Figure 2 The pixel electrode PE, and the second electrode of the first light-emitting element LE1 can be Figure 2 The common electrode CE.

[0103] According to some embodiments, each of the first driving transistor T1a, the first data writing transistor T2a, the first compensation transistor T3a, the first emitter control transistor T4a, the first initialization transistor T5a, and the first operation control transistor T6a may be a PMOS transistor. According to some embodiments, at least one of the first driving transistor T1a, the first data writing transistor T2a, the first compensation transistor T3a, the first emitter control transistor T4a, the first initialization transistor T5a, and the first operation control transistor T6a may be an NMOS transistor. Additionally, although... Figure 4 The first pixel circuit PC1 is shown to include six transistors and two capacitors, but this is an example and the embodiment is not limited thereto.

[0104] The second pixel circuit PC2 connected to the second light-emitting element LE2 may include a second driving transistor T1b, a second data writing transistor T2b, a second compensation transistor T3b, a second emission control transistor T4b, a second initialization transistor T5b, a first operation control transistor T6a, a second-first capacitor CA1b, and a second-second capacitor CA2b. The first electrode of the second data writing transistor T2b may be configured to receive a second data voltage VDATA2.

[0105] The first pixel circuit PC1 and the second pixel circuit PC2 can share the first operation control transistor T6a.

[0106] The second driving transistor T1b may include a gate electrode connected to the second gate node NGb, a first electrode connected to the first source node NSa, and a second electrode connected to the second drain node NDb.

[0107] According to some embodiments, the second driving transistor T1b may be a dual transistor including a second-first driving transistor T1-1b and a second-second driving transistor T1-2b. The second-first driving transistor T1-1b may include a gate electrode connected to the second gate node NGb, a first electrode connected to the first source node NSa, and a second electrode connected to the first electrode of the second-second driving transistor T1-2b. The second-second driving transistor T1-2b may include a gate electrode connected to the second gate node NGb, a first electrode connected to the second electrode of the second-first driving transistor T1-1b, and a second electrode connected to the second drain node NDb.

[0108] The first operation control transistor T6a can be electrically connected to the first driving transistor T1a and the second driving transistor T1b through the first source node NSa. For example, the first operation control transistor T6a can be electrically connected to the first-first driving transistor T1-1a and the second-first driving transistor T1-1b through the first source node NSa. Furthermore, the description of the second anode node NAb is similar to the description of the first anode node NAb.

[0109] Reference Figure 5 According to some embodiments, the third pixel circuit PC3 connected to the third light-emitting element LE3 may include a third driving transistor T1c, a third data writing transistor T2c, a third compensation transistor T3c, a third emission control transistor T4c, a third initialization transistor T5c, a second operation control transistor T6c, a third-first capacitor CA1c, and a third-second capacitor CA2c.

[0110] The fourth pixel circuit PC4 connected to the fourth light-emitting element LE4 may include a fourth driving transistor T1d, a fourth data writing transistor T2d, a fourth compensation transistor T3d, a fourth emission control transistor T4d, a fourth initialization transistor T5d, a second operation control transistor T6c, a fourth-first capacitor CA1d, and a fourth-second capacitor CA2d.

[0111] The third pixel circuit PC3 and the fourth pixel circuit PC4 can share the second operation control transistor T6c.

[0112] The third driving transistor T1c may include a gate electrode connected to the third gate node NGc, a first electrode connected to the second source node NSc, and a second electrode connected to the third drain node NDc.

[0113] According to some embodiments, the third driving transistor T1c may be a dual transistor including a third-first driving transistor T1-1c and a third-second driving transistor T1-2c. The third-first driving transistor T1-1c may include a gate electrode connected to a third gate node NGc, a first electrode connected to a second source node NSc, and a second electrode connected to the first electrode of the third-second driving transistor T1-2c. The third-second driving transistor T1-2c may include a gate electrode connected to the third gate node NGc, a first electrode connected to the second electrode of the third-first driving transistor T1-1c, and a second electrode connected to a third drain node NDc.

[0114] The fourth driving transistor T1d may include a gate electrode connected to the fourth gate node NGd, a first electrode connected to the second source node NSc, and a second electrode connected to the fourth drain node NDd.

[0115] According to some embodiments, the fourth driving transistor T1d may be a dual transistor including a fourth-first driving transistor T1-1d and a fourth-second driving transistor T1-2d. The fourth-first driving transistor T1-1d may include a gate electrode connected to the fourth gate node NGd, a first electrode connected to the second source node NSc, and a second electrode connected to the first electrode of the fourth-second driving transistor T1-2d. The fourth-second driving transistor T1-2d may include a gate electrode connected to the fourth gate node NGd, a first electrode connected to the second electrode of the fourth-first driving transistor T1-1d, and a second electrode connected to the fourth drain node NDd.

[0116] The second control transistor T6c can be electrically connected to the third driving transistor T1c and the fourth driving transistor T1d through the second source node NSC. For example, the second control transistor T6c can be electrically connected to the third-first driving transistor T1-1c and the fourth-first driving transistor T1-1d through the second source node NSC. Additionally, Figure 5 The descriptions of the data written to the gate signal GW', the compensation gate signal GC', the initialization gate signal GR', the first transmit control signal EM1', and the third anode node NAc and the fourth anode node NAD are respectively similar to Figure 4 The data is written into the gate signal GW, the compensation gate signal GC, the initialization gate signal GR, the first transmit control signal EM1, and the descriptions of the first anode node NAa and the second anode node NAb.

[0117] Figure 6 It is schematically shown that includes Figure 3 A plan view of an example of the first to fourth pixel circuits in a thin-film transistor array.

[0118] Reference Figure 6 According to some embodiments, the first driving transistor T1a, the first data writing transistor T2a, the first compensation transistor T3a, the first emission control transistor T4a, and the first initialization transistor T5a of the first pixel circuit PC1 can be positioned as a line along the second direction DR2. For example, the first driving transistor T1a, the first data writing transistor T2a, the first compensation transistor T3a, the first emission control transistor T4a, and the first initialization transistor T5a can be arranged sequentially along a direction opposite to the second direction DR2.

[0119] The second pixel circuit PC2 can be positioned on the first pixel circuit PC1 in the first direction DR1. The second driving transistor T1b, the second data writing transistor T2b, the second compensation transistor T3b, the second emission control transistor T4b, and the second initialization transistor T5b of the second pixel circuit PC2 can be arranged in a line along the second direction DR2. For example, the second driving transistor T1b, the second data writing transistor T2b, the second compensation transistor T3b, the second emission control transistor T4b, and the second initialization transistor T5b can be arranged sequentially in a direction opposite to the second direction DR2.

[0120] The second driving transistor T1b can be positioned in the first direction DR1 along with the first driving transistor T1a. The second data writing transistor T2b can be positioned in the first direction DR1 along with the first data writing transistor T2a. The second compensation transistor T3b can be positioned in the first direction DR1 along with the first compensation transistor T3a. The second emitter control transistor T4b can be positioned in the first direction DR1 along with the first emitter control transistor T4a. The second initialization transistor T5b can be positioned in the first direction DR1 along with the first initialization transistor T5a.

[0121] The third pixel circuit PC3 can be positioned on the second direction DR2 along with the first pixel circuit PC1. The fourth pixel circuit PC4 can be positioned on the second direction DR2 along with the second pixel circuit PC2.

[0122] The third driving transistor T1c, the third data writing transistor T2c, the third compensation transistor T3c, the third emission control transistor T4c, and the third initialization transistor T5c of the third pixel circuit PC3 can be arranged in a line along the second direction DR2. For example, the third driving transistor T1c, the third data writing transistor T2c, the third compensation transistor T3c, the third emission control transistor T4c, and the third initialization transistor T5c can be arranged sequentially along a direction opposite to the second direction DR2.

[0123] The fourth driving transistor T1d, the fourth data writing transistor T2d, the fourth compensation transistor T3d, the fourth emission control transistor T4d, and the fourth initialization transistor T5d of the fourth pixel circuit PC4 can be arranged in a line along the second direction DR2. For example, the fourth driving transistor T1d, the fourth data writing transistor T2d, the fourth compensation transistor T3d, the fourth emission control transistor T4d, and the fourth initialization transistor T5d can be arranged sequentially along a direction opposite to the second direction DR2.

[0124] The fourth driving transistor T1d can be positioned on the first direction DR1 along with the third driving transistor T1c. The fourth data write transistor T2d can be positioned on the first direction DR1 along with the third data write transistor T2c. The fourth compensation transistor T3d can be positioned on the first direction DR1 along with the third compensation transistor T3c. The fourth emitter control transistor T4d can be positioned on the first direction DR1 along with the third emitter control transistor T4c. The fourth initialization transistor T5d can be positioned on the first direction DR1 along with the third initialization transistor T5c.

[0125] According to some embodiments, the first operation control transistor T6a may be positioned on the second direction DR2 along with the first drive transistor T1a. For example, the first operation control transistor T6a may be positioned between the first drive transistor T1a and the third initialization transistor T5c.

[0126] The second operation control transistor T6c can be positioned on the second direction DR2 along with the second drive transistor T1b. For example, the second operation control transistor T6c can be positioned between the second drive transistor T1b and the fourth initialization transistor T5d. The second operation control transistor T6c can also be positioned on the first direction DR1 along with the first operation control transistor T6a.

[0127] According to some embodiments, the first driving transistor T1a may be positioned between the first operation control transistor T6a and the first data write transistor T2a. The third data write transistor T2c may be positioned between the first operation control transistor T6a and the third driving transistor T1c.

[0128] According to some embodiments, the second driving transistor T1b can be positioned between the second operation control transistor T6c and the second data write transistor T2b. The fourth data write transistor T2d can be positioned between the second operation control transistor T6c and the fourth driving transistor T1d.

[0129] The first operating control transistor T6a can be connected to the first driving transistor T1a and the second driving transistor T1b via the first connection line CL1. The second operating control transistor T6c can be connected to the third driving transistor T1c and the fourth driving transistor T1d via the second connection line CL2.

[0130] According to an embodiment, the thin-film transistors included in each pixel circuit can be arranged in a line along the second direction DR2. Therefore, during the fabrication process of the thin-film transistor array TA, impurities can be relatively easily doped into the substrate SUB. Furthermore, two pixel circuits adjacent to each other in the first direction DR1 can share an operating control transistor. Therefore, the integration density of the pixel circuit PC in the thin-film transistor array TA can be relatively improved. Therefore, the resolution and display quality of the display device DD can be relatively improved.

[0131] Figures 7 to 11 It is shown Figure 6 The layout diagram of the first pixel circuit.

[0132] Reference Figures 6 to 11 According to some embodiments, a thin-film transistor array TA may include a substrate SUB and a first conductive layer CTL1, a second conductive layer CTL2 and a third conductive layer CTL3 sequentially disposed on the substrate SUB.

[0133] Figure 7 The stacked state of the substrate SUB, the first conductive layer CTL1, the second conductive layer CTL2, and the third conductive layer CTL3 is shown. Figures 8 to 11The substrate SUB, the first conductive layer CTL1, the second conductive layer CTL2, and the third conductive layer CTL3 are shown respectively.

[0134] In the following text, reference will be made to Figures 6 to 11 An example of the arrangement of transistors and wiring included in the first pixel circuit PC1 of the thin-film transistor array TA is described in more detail.

[0135] Reference Figures 6 to 8 The substrate SUB may define the active portions A1-1a, A1-2a, A2a, A3a, A4a, A5a, and A6a of the first-first driving transistor T1-1a, the first-second driving transistor T1-2a, the first data write transistor T2a, the first compensation transistor T3a, the first emitter control transistor T4a, the first initialization transistor T5a, and the first operation control transistor T6a. According to some embodiments, the active portions A1-1a, A1-2a, A2a, A3a, A4a, A5a, and A6a may all extend in a first direction DR1 and may be arranged as a line along a second direction DR2.

[0136] Each of the active portions A1-1a, A1-2a, A2a, A3a, A4a, A5a, and A6a may include a source region, a drain region spaced apart from the source region, and a channel region between the source and drain regions. The channel region may be a region doped with an impurity of a first conductivity type. Each of the source and drain regions may be a region doped with an impurity of a second conductivity type. For example, the first conductivity type may be n-type, and the second conductivity type may be p-type. According to some embodiments, a device isolation layer including an insulating material may be positioned between the active portions A1-1a, A1-2a, A2a, A3a, A4a, A5a, and A6a.

[0137] According to some embodiments, the drain region D1-1a (hereinafter referred to as the first-first driving drain region) of the active portion A1-1a of the first-first driving transistor T1-1a can be spaced apart from the source region S1-1a (hereinafter referred to as the first-first driving source region) of the active portion A1-1a of the first-first driving transistor T1-1a in the first direction DR1. The first-first driving source region S1-1a can be the first electrode of the first-first driving transistor T1-1a, and the first-first driving drain region D1-1a can be the second electrode of the first-first driving transistor T1-1a.

[0138] According to some embodiments, the drain region D1-2a (hereinafter referred to as the first-second driving drain region) of the active portion A1-2a of the first-second driving transistor T1-2a can be spaced apart from the source region S1-2a (hereinafter referred to as the first-second driving source region) of the active portion A1-2a of the first-second driving transistor T1-2a in the first direction DR1. The first-second driving source region S1-2a can be the first electrode of the first-second driving transistor T1-2a, and the first-second driving drain region D1-2a can be the second electrode of the first-second driving transistor T1-2a.

[0139] According to some embodiments, the drain region D2a (hereinafter referred to as the first data write drain region) of the active portion A2a of the first data write transistor T2a can be spaced apart from the source region S2a (hereinafter referred to as the first data write source region) of the active portion A2a of the first data write transistor T2a in the first direction DR1. The first data write source region S2a can be the first electrode of the first data write transistor T2a, and the first data write drain region D2a can be the second electrode of the first data write transistor T2a.

[0140] According to some embodiments, the drain region D3a (hereinafter referred to as the first compensated drain region) of the active portion A3a of the first compensated transistor T3a can be spaced apart from the source region S3a (hereinafter referred to as the first compensated source region) of the active portion A3a of the first compensated transistor T3a in the first direction DR1. The first compensated source region S3a can be the first electrode of the first compensated transistor T3a, and the first compensated drain region D3a can be the second electrode of the first compensated transistor T3a.

[0141] According to some embodiments, the drain region D4a (hereinafter referred to as the first emitter control drain region) of the active portion A4a of the first emitter control transistor T4a may be spaced apart from the source region S4a (hereinafter referred to as the first emitter control source region) of the active portion A4a of the first emitter control transistor T4a in a direction opposite to the first direction DR1. The first emitter control source region S4a may be the first electrode of the first emitter control transistor T4a, and the first emitter control drain region D4a may be the second electrode of the first emitter control transistor T4a.

[0142] According to some embodiments, the drain region D5a (hereinafter referred to as the first initialization drain region) of the active portion A5a of the first initialization transistor T5a may be spaced apart from the source region S5a (hereinafter referred to as the first initialization source region) of the active portion A5a of the first initialization transistor T5a in a direction opposite to the first direction DR1. The first initialization source region S5a may be the first electrode of the first initialization transistor T5a, and the first initialization drain region D5a may be the second electrode of the first initialization transistor T5a.

[0143] According to some embodiments, the drain region D6a (hereinafter referred to as the first operation control drain region) of the active portion A6a of the first operation control transistor T6a may be spaced apart from the source region S6a (hereinafter referred to as the first operation control source region) of the active portion A6a of the first operation control transistor T6a in a direction opposite to the first direction DR1. The first operation control source region S6a may be the first electrode of the first operation control transistor T6a, and the first operation control drain region D6a may be the second electrode of the first operation control transistor T6a.

[0144] The first insulating layer may be positioned on the substrate SUB. The first insulating layer may include inorganic insulating materials and / or organic insulating materials.

[0145] Further reference Figure 9 The first conductive layer CTL1 can be positioned on the substrate SUB. The first conductive layer CTL1 can be positioned on the first insulating layer. The first conductive layer CTL1 may include a conductive material.

[0146] The first conductive layer CTL1 may include first gate electrodes to sixth gate electrodes G1a, G2a, G3a, G4a, G5a, and G6a spaced apart from each other. According to some embodiments, the first insulating layer may have a structure including insulating patterns corresponding to the first gate electrodes to the sixth gate electrodes G1a, G2a, G3a, G4a, G5a, and G6a, respectively.

[0147] The first gate electrode G1a can be stacked with the channel region C1-1a of the active portion A1-1a of the first-first driving transistor T1-1a and the channel region C1-2a of the active portion A1-2a of the first-second driving transistor T1-2a in the planar diagram. The first gate electrode G1a can be the gate electrode of the first-first driving transistor T1-1a and the gate electrode of the first-second driving transistor T1-2a.

[0148] According to some embodiments, the second gate electrode G2a may be spaced apart from the first gate electrode G1a in a direction opposite to the second direction DR2. The second gate electrode G2a may be superimposed on the channel region C2a of the active portion A2a of the first data write transistor T2a in a planar view. The second gate electrode G2a may be the gate electrode of the first data write transistor T2a.

[0149] According to some embodiments, the third gate electrode G3a may be spaced apart from the second gate electrode G2a in a direction opposite to the second direction DR2. The third gate electrode G3a may be stacked with the channel region C3a of the active portion A3a of the first compensation transistor T3a in a planar view. The third gate electrode G3a may be the gate electrode of the first compensation transistor T3a.

[0150] According to some embodiments, the fourth gate electrode G4a may be spaced apart from the third gate electrode G3a in a direction opposite to the second direction DR2. The fourth gate electrode G4a may be stacked with the channel region C4a of the active portion A4a of the first emitter control transistor T4a in a planar view. The fourth gate electrode G4a may be the gate electrode of the first emitter control transistor T4a.

[0151] According to some embodiments, the fifth gate electrode G5a may be spaced apart from the fourth gate electrode G4a in a direction opposite to the second direction DR2. The fifth gate electrode G5a may be stacked with the channel region C5a of the active portion A5a of the first initialization transistor T5a in a planar view. The fifth gate electrode G5a may be the gate electrode of the first initialization transistor T5a.

[0152] According to some embodiments, the sixth gate electrode G6a may be spaced apart from the first gate electrode G1a in the second direction DR2. The sixth gate electrode G6a may be stacked with the channel region C6a of the active portion A6a of the first operation control transistor T6a in a planar view. The sixth gate electrode G6a may be the gate electrode of the first operation control transistor T6a.

[0153] The second insulating layer may be positioned on the first conductive layer CTL1. The second insulating layer may include inorganic insulating materials and / or organic insulating materials.

[0154] Further reference Figure 10 The second conductive layer CTL2 can be positioned on the first conductive layer CTL1. The second conductive layer CTL2 can be positioned on the second insulating layer. The second conductive layer CTL2 may include a conductive material.

[0155] The second conductive layer CTL2 may include gate lines, emit control lines, a first initialization voltage transmission line ITL, a power transmission line PTL, a first connection line CL1, and first connection patterns to eighth connection patterns CP1, CP2, CP3, CP4, CP5, CP6, CP7, and CP8 spaced apart from each other. The gate lines may include a first data write gate line GWL, a first compensation gate line GCL, and a first initialization gate line GRL. The emit control lines may include a first emit control line EML1 and a second emit control line EML2.

[0156] The first data write gate line GWL, the first compensation gate line GCL, the first initialization gate line GRL, the first-first emitter control line EML1, and the second emitter control line EML2 can all extend in the first direction DR1 and can be spaced apart from each other in the second direction DR2.

[0157] Figure 4The data write gate signal GW can be provided to the first data write gate line GWL. A portion of the first data write gate line GWL can be superimposed on a portion of the second gate electrode G2a in a planar view. This portion of the first data write gate line GWL can be connected to this portion of the second gate electrode G2a through a first contact hole CNT1 that penetrates the underlying insulating layer (e.g., the second insulating layer).

[0158] Figure 4 The compensation gate signal GC can be provided to the first compensation gate line GCL. A portion of the first compensation gate line GCL can be stacked with a portion of the third gate electrode G3a in a planar view. This portion of the first compensation gate line GCL can be connected to this portion of the third gate electrode G3a through a second contact hole CNT2 that penetrates the underlying insulating layer (e.g., the second insulating layer).

[0159] Figure 4 The initialization gate signal GR can be provided to the first initialization gate line GRL. A portion of the first initialization gate line GRL can be superimposed on a portion of the fifth gate electrode G5a in a planar view. This portion of the first initialization gate line GRL can be connected to this portion of the fifth gate electrode G5a through a third contact hole CNT3 that penetrates the underlying insulating layer (e.g., the second insulating layer).

[0160] Figure 4 The first transmit control signal EM1 can be provided to the first-first transmit control line EML1. A portion of the first-first transmit control line EML1 can be superimposed on a portion of the fourth gate electrode G4a in a plan view. This portion of the first-first transmit control line EML1 can be connected to this portion of the fourth gate electrode G4a through a fourth contact hole CNT4 that penetrates the underlying insulating layer (e.g., the second insulating layer).

[0161] Figure 4 The second transmit control signal EM2 can be provided to the second transmit control line EML2. A portion of the second transmit control line EML2 can be superimposed on a portion of the sixth gate electrode G6a in a plan view. This portion of the second transmit control line EML2 can be connected to this portion of the sixth gate electrode G6a through a fifth contact hole CNT5 that penetrates the underlying insulating layer (e.g., the second insulating layer).

[0162] A portion of the first initialization voltage transmission line ITL can be superimposed on the first initialization source region S5a in the plan view. This portion of the first initialization voltage transmission line ITL can be connected to the first initialization source region S5a through a sixth contact hole CNT6 that penetrates the underlying insulating layers (e.g., the first insulating layer and the second insulating layer).

[0163] Power transmission line PTL can Figure 4The first power voltage ELVDD is transmitted to the first operation control source region S6a. The first connection line CL1 can electrically connect the first operation control transistor T6a, the first-first drive transistor T1-1a, and the second-first drive transistor T1-1b. (See later...) Figure 12 and Figure 13 The power transmission line PTL and the first connecting line CL1 together with the second connecting line CL2 are described in detail.

[0164] The first end of the first connection pattern CP1 can be superimposed on the first-first drive drain region D1-1a in the plan view. The first end of the first connection pattern CP1 can be connected to the first-first drive drain region D1-1a through a seventh contact hole CNT7 that penetrates the underlying insulating layer (e.g., the first insulating layer and the second insulating layer).

[0165] The second end of the first connection pattern CP1 can be superimposed on the first-second driving source region S1-2a in the plan view. The second end of the first connection pattern CP1 can be connected to the first-second driving source region S1-2a through an eighth contact hole CNT8 that penetrates the underlying insulating layer (e.g., the first insulating layer and the second insulating layer). Therefore, the first-first driving drain region D1-1a can be electrically connected to the first-second driving source region S1-2a through the first connection pattern CP1.

[0166] The second connection pattern CP2 can be superimposed on the first data writing source area S2a in the plan view. The second connection pattern CP2 can be connected to the first data writing source area S2a through a ninth contact hole CNT9 that penetrates the underlying insulating layers (e.g., the first insulating layer and the second insulating layer).

[0167] The third connection pattern CP3 can be superimposed on the first data write drain area D2a in the plan view. The third connection pattern CP3 can be connected to the first data write drain area D2a through a tenth contact hole CNT10 that penetrates the underlying insulating layers (e.g., the first insulating layer and the second insulating layer). According to some embodiments, the third connection pattern CP3 can be electrically connected to... Figure 4 The first electrode of the first-first capacitor CA1a. According to some embodiments, the first electrode of the first-first capacitor CA1a may be located on the third conductive layer CTL3.

[0168] The fourth connection pattern CP4 can be superimposed on the first compensation source region S3a in a plan view. The fourth connection pattern CP4 can be connected to the first compensation source region S3a through an eleventh contact hole CNT11 that penetrates the underlying insulating layers (e.g., the first and second insulating layers). According to some embodiments, the fourth connection pattern CP4 can be electrically connected to... Figure 4The second electrode of the first-first capacitor CA1a, the second electrode of the first-second capacitor CA2a, and the first gate electrode G1a. According to some embodiments, the second electrodes of the first-first capacitor CA1a and the second electrodes of the first-second capacitor CA2a can be positioned on the third conductive layer CTL3.

[0169] The fifth connection pattern CP5 can be superimposed on the first compensation leakage area D3a in the plan view. The fifth connection pattern CP5 can be connected to the first compensation leakage area D3a through the twelfth contact hole CNT12 that penetrates the underlying insulating layer (e.g., the first insulating layer and the second insulating layer).

[0170] The sixth connection pattern CP6 can be superimposed on the first emitter control drain area D4a in the plan view. The sixth connection pattern CP6 can be connected to the first emitter control drain area D4a through the thirteenth contact hole CNT13 that penetrates the underlying insulating layers (e.g., the first insulating layer and the second insulating layer).

[0171] The seventh connection pattern CP7 can be superimposed on the first emission control source region S4a in the plan view. The seventh connection pattern CP7 can be connected to the first emission control source region S4a through the fourteenth contact hole CNT14 that penetrates the underlying insulating layer (e.g., the first insulating layer and the second insulating layer).

[0172] The eighth connection pattern CP8 can be superimposed on the first initialization drain area D5a in the plan view. The eighth connection pattern CP8 can be connected to the first initialization drain area D5a through the fifteenth contact hole CNT15 that penetrates the underlying insulating layer (e.g., the first insulating layer and the second insulating layer).

[0173] The third insulating layer may be positioned on the second conductive layer CTL2. The third insulating layer may include inorganic insulating materials and / or organic insulating materials.

[0174] Further reference Figure 11 The third conductive layer CTL3 can be positioned on the second conductive layer CTL2. The third conductive layer CTL3 can be positioned on the third insulating layer. The third conductive layer CTL3 may include a conductive material.

[0175] The third conductive layer CTL3 may include a first data line DL1, an initialization voltage line VIL, a ninth connection pattern CP9, and a tenth connection pattern CP10 spaced apart from each other.

[0176] The first data line DL1 can be extended in the second direction DR2. Figure 4A first data voltage VDATA1 can be provided to a first data line DL1. A portion of the first data line DL1 can be superimposed on a second connection pattern CP2 in a plan view. This portion of the first data line DL1 can be connected to the second connection pattern CP2 through a sixteenth contact hole CNT16 that penetrates the underlying insulating layer (e.g., a third insulating layer). Therefore, the first data voltage VDATA1 can be provided to the first data write source region S2a through the first data line DL1 and the second connection pattern CP2.

[0177] The initialization voltage line VIL can extend in the second direction DR2 and can be spaced apart from the first data line DL1 in the first direction DR1. Figure 4 The initialization voltage VINT can be provided to the initialization voltage line VIL. A portion of the initialization voltage line VIL can be superimposed on a portion of the first initialization voltage transmission line ITL in the plan view. This portion of the initialization voltage line VIL can be connected to this portion of the first initialization voltage transmission line ITL through the seventeenth contact hole CNT17 that penetrates the underlying insulating layer (e.g., the third insulating layer). Therefore, the initialization voltage VINT can be provided to the first initialization source region S5a through the initialization voltage line VIL and the first initialization voltage transmission line ITL.

[0178] The first portion of the ninth connection pattern CP9 can be superimposed on the first-second drive drain area D1-2a in the plan view. The first portion of the ninth connection pattern CP9 can be connected to the first-second drive drain area D1-2a through the eighteenth contact hole CNT18 that penetrates the underlying insulating layer (e.g., from the first insulating layer to the third insulating layer).

[0179] The second portion of the ninth connection pattern CP9 can be superimposed on the fifth connection pattern CP5 in the plan view. The second portion of the ninth connection pattern CP9 can be connected to the fifth connection pattern CP5 through the nineteenth contact hole CNT19 that penetrates the underlying insulating layer (e.g., the third insulating layer). Therefore, the first-second drive drain regions D1-2a can be electrically connected to the first compensation drain region D3a through the ninth connection pattern CP9 and the fifth connection pattern CP5.

[0180] The third portion of the ninth connection pattern CP9 can be superimposed on the seventh connection pattern CP7 in the plan view. The third portion of the ninth connection pattern CP9 can be connected to the seventh connection pattern CP7 through the twentieth contact hole CNT20 that penetrates the underlying insulating layer (e.g., the third insulating layer). Therefore, the first-second drive drain regions D1-2a can be electrically connected to the first emission control source region S4a through the ninth connection pattern CP9 and the seventh connection pattern CP7.

[0181] The first end of the tenth connecting pattern CP10 can be superimposed on the sixth connecting pattern CP6 in the plan view. The first end of the tenth connecting pattern CP10 can be connected to the sixth connecting pattern CP6 through the twenty-first contact hole CNT21 that penetrates the underlying insulating layer (e.g., the third insulating layer).

[0182] The second end of the tenth connection pattern CP10 can be superimposed on the eighth connection pattern CP8 in the plan view. The second end of the tenth connection pattern CP10 can be connected to the eighth connection pattern CP8 through a twenty-second contact hole CNT22 that penetrates the underlying insulating layer (e.g., the third insulating layer). Therefore, the first emitter control drain region D4a can be electrically connected to the first initialization drain region D5a through the sixth connection pattern CP6, the tenth connection pattern CP10, and the eighth connection pattern CP8.

[0183] As mentioned above, it has been referred to Figures 7 to 11 An example of the arrangement structure of the first pixel circuit PC1 has been described, but this is an example and the embodiments are not limited thereto, and the arrangement structure of the first pixel circuit PC1 can be modified in various ways. In addition, the arrangement structure of each of the second to fourth pixel circuits PC2, PC3 and PC4 can be the same as (or substantially the same as) or similar to the arrangement structure of the first pixel circuit PC1 described above.

[0184] Figure 12 It is shown Figure 6 The layout diagram of the first pixel circuit to the fourth pixel circuit. Figure 13 and Figure 14 It is shown Figure 6 A magnified view of region A.

[0185] Figure 12 The stacked state of the substrate SUB, the first conductive layer CTL1, the second conductive layer CTL2, and the third conductive layer CTL3 is shown. For ease of description, Figure 13 and Figure 14 Selectively shown Figure 12 Some components.

[0186] In the following text, reference will be made to Figures 12 to 14 This describes an example of the arrangement of the first to fourth pixel circuits PC1, PC2, PC3, and PC4, which are adjacent to each other in a thin-film transistor array TA. (Refer to the above.) Figures 7 to 11 The description of the first pixel circuit PC1 can be applied equivalently (or substantially equivalently) or similarly to each of the second through fourth pixel circuits PC2, PC3, and PC4. Therefore, some repetitive descriptions can be omitted or simplified.

[0187] Reference Figure 12 and Figure 13The substrate SUB can also define the active portions of the transistors included in the second to fourth pixel circuits PC2, PC3 and PC4.

[0188] The first conductive layer CTL1 may also include the gate electrode of each of the transistors included in the second to fourth pixel circuits PC2, PC3 and PC4.

[0189] The second conductive layer CTL2 may also include a second data write gate line GWL', a second compensation gate line GCL', a second initialization gate line GRL', a first-second emitter control line EML1', a second initialization voltage transmission line ITL', a second-first connection line CL2-1, a second-second connection line CL2-2, and a connection pattern.

[0190] The third conductive layer CTL3 may also include a second data line DL2, a power voltage line VDL, a second-third connection line CL2-3, and a connection pattern.

[0191] The first data write gate line GWL can extend along the first direction DR1. The first data write gate line GWL can be electrically connected to the gate electrode of the first data write transistor T2a and the gate electrode of the second data write transistor T2b.

[0192] The second data write gate line GWL' may extend in the first direction DR1 and may be spaced apart from the first data write gate line GWL in the second direction DR2. The second data write gate line GWL' may be electrically connected to the gate electrode of the third data write transistor T2c and the gate electrode of the fourth data write transistor T2d.

[0193] The first compensation gate line GCL can extend along the first direction DR1. The first compensation gate line GCL can be electrically connected to the gate electrode of the first compensation transistor T3a and the gate electrode of the second compensation transistor T3b.

[0194] The second compensation gate line GCL' may extend in the first direction DR1 and may be spaced apart from the first compensation gate line GCL in the second direction DR2. The second compensation gate line GCL' may be electrically connected to the gate electrode of the third compensation transistor T3c and the gate electrode of the fourth compensation transistor T3d.

[0195] The first initialization gate line GRL can extend along the first direction DR1. The first initialization gate line GRL can be electrically connected to the gate electrode of the first initialization transistor T5a and the gate electrode of the second initialization transistor T5b.

[0196] The second initialization gate line GRL' may extend in the first direction DR1 and may be spaced apart from the first initialization gate line GRL in the second direction DR2. The second initialization gate line GRL' may be electrically connected to the gate electrode of the third initialization transistor T5c and the gate electrode of the fourth initialization transistor T5d.

[0197] The first-to-first emitter control line EML1 can extend along the first direction DR1. The first-to-first emitter control line EML1 can be electrically connected to the gate electrode of the first emitter control transistor T4a and the gate electrode of the second emitter control transistor T4b.

[0198] The first-second emitter control line EML1' can extend in the first direction DR1 and can be spaced apart from the first-first emitter control line EML1 in the second direction DR2. The first-second emitter control line EML1' can be electrically connected to the gate electrode of the third emitter control transistor T4c and the gate electrode of the fourth emitter control transistor T4d.

[0199] The second emitter control line EML2 can extend along the first direction DR1. The second emitter control line EML2 can be electrically connected to the gate electrode of the first operating control transistor T6a and the gate electrode of the second operating control transistor T6c.

[0200] The first initialization voltage transmission line ITL can be electrically connected to the source region of the active portion of the first initialization transistor T5a and the source region of the active portion of the second initialization transistor T5b.

[0201] The second initialization voltage transmission line ITL' may extend in the first direction DR1 and may be spaced apart from the first initialization voltage transmission line ITL in the second direction DR2. The second initialization voltage transmission line ITL' may be electrically connected to the source region of the active portion of the third initialization transistor T5c and the source region of the active portion of the fourth initialization transistor T5d.

[0202] The first data line DL1 can extend in the second direction DR2. The first data line DL1 can be electrically connected to the source region of the active portion of the first data write transistor T2a and the source region of the active portion of the third data write transistor T2c.

[0203] The second data line DL2 may extend in the second direction DR2 and may be spaced apart from the first data line DL1 in the first direction DR1. The second data line DL2 may be electrically connected to the source region of the active portion of the second data write transistor T2b and the source region of the active portion of the fourth data write transistor T2d.

[0204] The first end of the power transmission line PTL can be superimposed on the first operation control source region S6a in the plan view. The first end of the power transmission line PTL can be connected to the first operation control source region S6a through a twenty-third contact hole CNT23 that penetrates the underlying insulation layer (e.g., the first insulation layer and the second insulation layer).

[0205] In the plan view, the second end of the power transmission line PTL can be superimposed on the source region S6c (hereinafter referred to as the second operation control source region) of the active portion A6c of the second operation control transistor T6c. The second end of the power transmission line PTL can be connected to the second operation control source region S6c through a twenty-fourth contact hole CNT24 that penetrates the underlying insulating layers (e.g., the first insulating layer and the second insulating layer).

[0206] The power voltage line VDL can be extended in the second direction DR2. Figure 4 A first power voltage ELVDD can be supplied to the power voltage line VDL. A portion of the power voltage line VDL can be superimposed on the second end of the power transmission line PTL in the plan view. This portion of the power voltage line VDL can be connected to the second end of the power transmission line PTL through a 25th contact hole CNT25 that penetrates the underlying insulation layer (e.g., a third insulation layer). Therefore, the first power voltage ELVDD can be supplied to the first operation control source region S6a and the second operation control source region S6c through the power voltage line VDL and the power transmission line PTL.

[0207] The first connection line CL1 can electrically connect the first operation control transistor T6a, the first-first drive transistor T1-1a, and the second-first drive transistor T1-1b to each other. According to some embodiments, the first connection line CL1 can be located on the same layer (or substantially the same layer) as the gate lines GWL, GWL', GCL, GCL', GRL and GRL' and the emitter control lines EML1, EML1' and EML2.

[0208] The first end CL1a of the first connecting line CL1 can be superimposed on the first operation control drain area D6a in the plan view. The first end CL1a of the first connecting line CL1 can be connected to the first operation control drain area D6a through the twenty-sixth contact hole CNT26 that penetrates the underlying insulating layer (e.g., the first insulating layer and the second insulating layer).

[0209] The second end CL1b of the first connecting line CL1 can be superimposed on the first-first driving source region S1-1a in the plan view. The second end CL1b of the first connecting line CL1 can be connected to the first-first driving source region S1-1a through the twenty-seventh contact hole CNT27 that penetrates the underlying insulating layers (e.g., the first insulating layer and the second insulating layer). Therefore, the first operation control drain region D6a can be electrically connected to the first-first driving source region S1-1a through the first connecting line CL1.

[0210] The third end CL1c of the first connection line CL1 can be superimposed on the source region S1-1b (hereinafter referred to as the second-first driving source region) of the active portion A1-1b of the second-first driving transistor T1-1b in the plan view. The third end CL1c of the first connection line CL1 can be connected to the second-first driving source region S1-1b through a twenty-eighth contact hole CNT28 that penetrates the underlying insulating layers (e.g., the first insulating layer and the second insulating layer). Therefore, the first operation control drain region D6a can be electrically connected to the second-first driving source region S1-1b through the first connection line CL1.

[0211] The second connection line CL2 can electrically connect the second operation control transistor T6c, the third-first drive transistor T1-1c, and the fourth-first drive transistor T1-1d to each other.

[0212] According to some embodiments, the second connecting line CL2 may include a second-first connecting line CL2-1, a second-second connecting line CL2-2, and a second-third connecting line CL2-3. The second-third connecting line CL2-3 may be positioned on a different layer than the second-first connecting line CL2-1 and the second-second connecting line CL2-2.

[0213] According to some embodiments, the second-first connection line CL2-1 and the second-second connection line CL2-2 may be located on the same layer (or substantially the same layer) as the gate lines GWL, GWL', GCL, GCL', GRL and GRL' and the transmit control lines EML1, EML1' and EML2. According to some embodiments, the second-third connection line CL2-3 may be located on the same layer (or substantially the same layer) as the data lines DL1 and DL2 and the power voltage line VDL.

[0214] The first end CL2-1a of the second-first connection line CL2-1 can be superimposed on the drain region D6c (hereinafter referred to as the second operation control drain region) of the active portion A6c of the second operation control transistor T6c in a plan view. The first end CL2-1a of the second-first connection line CL2-1 can be connected to the second operation control drain region D6c through a twenty-ninth contact hole CNT29 that penetrates the underlying insulating layers (e.g., the first insulating layer and the second insulating layer).

[0215] The second-to-second connecting line CL2-2 can be spaced apart from the second-to-first connecting line CL2-1 on the second direction DR2.

[0216] The first end CL2-2a of the second-second connection line CL2-2 can be superimposed on the source region S1-1c of the active portion A1-1c of the third-first driving transistor T1-1c (hereinafter referred to as the third-first driving source region) in the plan view. The first end CL2-2a of the second-second connection line CL2-2 can be connected to the third-first driving source region S1-1c through the thirtieth contact hole CNT30 that penetrates the underlying insulating layers (e.g., the first insulating layer and the second insulating layer).

[0217] The second end CL2-2b of the second-second connection line CL2-2 can be superimposed on the source region S1-1d of the active portion A1-1d of the fourth-first driving transistor T1-1d (hereinafter referred to as the fourth-first driving source region) in the plan view. The second end CL2-2b of the second-second connection line CL2-2 can be connected to the fourth-first driving source region S1-1d through a thirty-first contact hole CNT31 that penetrates the underlying insulating layers (e.g., the first insulating layer and the second insulating layer).

[0218] The second-third connecting line CL2-3 can connect the second end CL2-1b of the second-first connecting line CL2-1 and the second end CL2-2b of the second-second connecting line CL2-2 to each other. The second-third connecting line CL2-3 can extend in the second direction DR2.

[0219] The first end CL2-3a of the second-third connecting line CL2-3 can be superimposed on the second end CL2-1b of the second-first connecting line CL2-1 in the plan view. The first end CL2-3a of the second-third connecting line CL2-3 can be connected to the second end CL2-1b of the second-first connecting line CL2-1 through a 32nd contact hole CNT32 that penetrates the underlying insulating layer (e.g., the third insulating layer).

[0220] The second end CL2-3b of the second-third connecting line CL2-3 can be superimposed on the second end CL2-2b of the second-second connecting line CL2-2 in the plan view. The second end CL2-3b of the second-third connecting line CL2-3 can be connected to the second end CL2-2b of the second-second connecting line CL2-2 through the thirty-third contact hole CNT33 that penetrates the underlying insulating layer (e.g., the third insulating layer).

[0221] Therefore, the second operation control drain area D6c can be electrically connected to the third-first drive source area S1-1c and the fourth-first drive source area S1-1d through the second-first connection line CL2-1, the second-third connection line CL2-3, and the second-second connection line CL2-2.

[0222] As described above, the first connection line CL1 can contact each of the first operational control drain region D6a, the first-first driving source region S1-1a, and the second-first driving source region S1-1b through a contact hole. The second-first connection line CL2-1 can contact the second operational control drain region D6c through a contact hole. The second-second connection line CL2-2 can contact each of the third-first driving source region S1-1c and the fourth-first driving source region S1-1d through a contact hole. According to some embodiments, the first connection line CL1, the second-first connection line CL2-1, and the second-second connection line CL2-2 can be positioned on the same layer (or substantially the same layer) as each other. Therefore, characteristic deviations between the driving transistors T1-1a, T1-1b, T1-1c, and T1-1d can be prevented or reduced.

[0223] In the plan view, the second-third connection line CL2-3 extending in the second direction DR2 may intersect at least one of the gate lines GWL, GWL', GCL, GCL', GRL or GRL', emitter control lines EML1, EML1' or EML2, and initialization voltage transmission lines ITL and ITL' extending in the first direction DR1. The second-third connection line CL2-3 may be positioned on a different layer from the intersecting lines.

[0224] According to some embodiments, such as Figure 13 As shown, the second-third connection line CL2-3 may intersect with the second emitter control line EML2, the second initialization voltage transmission line ITL', the second initialization gate line GRL', the first-second emitter control line EML1', the second compensation gate line GCL', and the second data write gate line GWL' in the plan view. In the plan view, the second-first connection line CL2-1 may not intersect with the gate lines GWL, GWL', GCL, GCL', GRL and GRL', emitter control lines EML1, EML1' and EML2, and initialization voltage transmission lines ITL and ITL' extending in the first direction DR1.

[0225] According to some embodiments, such as Figure 14As shown, the second-third connection line CL2-3 may intersect with the second initialization voltage transmission line ITL', the second initialization gate line GRL', the first-second emitter control line EML1', the second compensation gate line GCL', and the second data write gate line GWL' in the plan view. In the plan view, the second-first connection line CL2-1 may intersect with the second emitter control line EML2 extending in the first direction DR1.

[0226] exist Figure 14 In one embodiment, the second transmit control line EML2 may include a first extension portion EML2a, a second extension portion EML2b, and a bridge electrode BRE. Both the first extension portion EML2a and the second extension portion EML2b may extend in the first direction DR1.

[0227] The first extension portion EML2a can be stacked with the gate electrode of the first operation control transistor T6a in the plan view, and can be electrically connected to the gate electrode of the first operation control transistor T6a through a contact hole.

[0228] The second extension portion EML2b may be spaced apart from the first extension portion EML2a in the first direction DR1, and the bridge electrode BRE is located between the second extension portion EML2b and the first extension portion EML2a. The second extension portion EML2b may be stacked with the gate electrode of the second operation control transistor T6c in a plan view, and may be electrically connected to the gate electrode of the second operation control transistor T6c through a contact hole.

[0229] The bridge electrode BRE can be positioned on a different layer than the first extension EML2a, the second extension EML2b, and the second-first connection line CL2-1. According to some embodiments, the bridge electrode BRE can be positioned on the same layer (or substantially the same layer) as the data lines DL1 and DL2, the power voltage line VDL, and the second-third connection line CL2-3. The bridge electrode BRE can intersect the second-first connection line CL2-1 in a plan view.

[0230] The bridge electrode BRE can electrically connect the first extension portion EML2a and the second extension portion EML2b to each other. The first end of the bridge electrode BRE can be connected to the first extension portion EML2a through a thirty-fourth contact hole CNT34 that penetrates the underlying insulating layer (e.g., the third insulating layer). The second end of the bridge electrode BRE can be connected to the second extension portion EML2b through a thirty-fifth contact hole CNT35 that penetrates the underlying insulating layer (e.g., the third insulating layer).

[0231] Figure 14The diagram shows the second-first connection line CL2-1 intersecting one of the gate lines GWL, GWL', GCL, GCL', GRL and GRL', emitter control lines EML1, EML1' and EML2, and initialization voltage transmission lines ITL and ITL' extending in the first direction DR1 in a plan view. However, the embodiment is not limited to this; the second-first connection line CL2-1 may intersect two or more lines extending in the first direction DR1 in a plan view. In this case, each of the lines intersecting the second-first connection line CL2-1 may have a... Figure 14 The structure of the second transmit control line EML2 is similar.

[0232] Figure 15 It is schematically shown that includes Figure 3 A plan view of an example of the first to fourth pixel circuits in a thin-film transistor array. Figure 16 It is shown Figure 15 A magnified view of region B.

[0233] The following text will focus on the references above. Figures 6 to 13 The differences between the described embodiments are used to describe Figures 15 to 16 The embodiments described above may omit or simplify the references. Figures 6 to 13 The description repeats some of the same descriptions. Figure 15 It can correspond to Figure 6 ,and Figure 16 It can correspond to Figure 14 .

[0234] Reference Figure 15 The transistors T1c, T2c, T3c, T4c, and T5c of the third pixel circuit PC3 can be positioned symmetrically with respect to the first operation control transistor T6a and the transistors T1a, T2a, T3a, T4a, and T5a of the first pixel circuit PC1 (e.g., in a mirror image or arrangement). The transistors T1d, T2d, T3d, T4d, and T5d of the fourth pixel circuit PC4 can be arranged symmetrically with respect to the second operation control transistor T6c and the transistors T1b, T2b, T3b, T4b, and T5b of the second pixel circuit PC2 (e.g., in a mirror image or arrangement).

[0235] According to some embodiments, the first driving transistor T1a may be adjacent to the first operation control transistor T6a in a direction opposite to the second direction DR2. No other transistors may be positioned between the first driving transistor T1a and the first operation control transistor T6a. For example, the first driving transistor T1a, the first data write transistor T2a, the first compensation transistor T3a, the first emitter control transistor T4a, and the first initialization transistor T5a may be arranged sequentially along a direction opposite to the second direction DR2.

[0236] According to some embodiments, the third driving transistor T1c may be adjacent to the first operation control transistor T6a in the second direction DR2. No other transistors may be positioned between the third driving transistor T1c and the first operation control transistor T6a. For example, the third driving transistor T1c, the third data write transistor T2c, the third compensation transistor T3c, the third emitter control transistor T4c, and the third initialization transistor T5c may be arranged sequentially along the second direction DR2.

[0237] According to some embodiments, the first driving transistor T1a may be positioned between the first operation control transistor T6a and the first data write transistor T2a. The third driving transistor T1c may be positioned between the first operation control transistor T6a and the third data write transistor T2c.

[0238] According to some embodiments, the second driving transistor T1b may be adjacent to the second operation control transistor T6c in a direction opposite to the second direction DR2. No other transistors may be positioned between the second driving transistor T1b and the second operation control transistor T6c. For example, the second driving transistor T1b, the second data write transistor T2b, the second compensation transistor T3b, the second emitter control transistor T4b, and the second initialization transistor T5b may be arranged sequentially along a direction opposite to the second direction DR2.

[0239] According to some embodiments, the fourth driving transistor T1d may be adjacent to the second operation control transistor T6c on the second direction DR2. No other transistors may be positioned between the fourth driving transistor T1d and the second operation control transistor T6c. For example, the fourth driving transistor T1d, the fourth data write transistor T2d, the fourth compensation transistor T3d, the fourth emitter control transistor T4d, and the fourth initialization transistor T5d may be arranged sequentially along the second direction DR2.

[0240] According to some embodiments, the second driving transistor T1b can be positioned between the second operation control transistor T6c and the second data write transistor T2b. The fourth driving transistor T1d can be positioned between the second operation control transistor T6c and the fourth data write transistor T2d.

[0241] The first operating control transistor T6a can be connected to the first driving transistor T1a and the second driving transistor T1b via the first connection line CL1. The second operating control transistor T6c can be connected to the third driving transistor T1c and the fourth driving transistor T1d via the second connection line CL2.

[0242] like Figure 15As shown, when transistors T1c, T2c, T3c, T4c, and T5c of the third pixel circuit PC3 and transistors T1a, T2a, T3a, T4a, and T5a of the first pixel circuit PC1 are arranged in a mirror image or configuration, and transistors T1d, T2d, T3d, T4d, and T5d of the fourth pixel circuit PC4 and transistors T1b, T2b, T3b, T4b, and T5b of the second pixel circuit PC2 are arranged in a mirror image or configuration, the second operation control transistor T6c can be connected to the third driving transistor T1c and the fourth driving transistor T1d relatively more easily.

[0243] Reference Figure 16 The first connection line CL1 can electrically connect the first operation control transistor T6a, the first-first drive transistor T1-1a, and the second-first drive transistor T1-1b to each other. The first connection line CL1 can be referenced above. Figure 13 The first connecting line CL1 described is the same (or substantially the same).

[0244] The second connection line CL2 can electrically connect the second operating control transistor T6c, the third-first driving transistor T1-1c, and the fourth-first driving transistor T1-1d to each other. According to some embodiments, the second connection line CL2 can be positioned on the same layer (or substantially the same layer) as the first connection line CL1.

[0245] The first end CL2a of the second connecting line CL2 can be superimposed on the second operation control drain area D6c in the plan view. The first end CL2a of the second connecting line CL2 can be connected to the second operation control drain area D6c through the thirty-sixth contact hole CNT36 that penetrates the underlying insulating layers (e.g., the first insulating layer and the second insulating layer).

[0246] The second end CL2b of the second connecting line CL2 can be superimposed on the third-first driving source region S1-1c in the plan view. The second end CL2b of the second connecting line CL2 can be connected to the third-first driving source region S1-1c through the thirty-seventh contact hole CNT37 that penetrates the underlying insulating layer (e.g., the first insulating layer and the second insulating layer).

[0247] The third end CL2c of the second connecting line CL2 can be superimposed on the fourth-first driving source region S1-1d in the plan view. The third end CL2c of the second connecting line CL2 can be connected to the fourth-first driving source region S1-1d through a thirty-eighth contact hole CNT38 that penetrates the underlying insulating layer (e.g., the first insulating layer and the second insulating layer).

[0248] In the plan view, the second connection line CL2 may intersect at least one of the gate line, emitter control line, and initialization voltage transmission line extending in the first direction DR1. The second connection line CL2 may be positioned on a different layer from the intersecting line.

[0249] According to some embodiments, the second connecting line CL2 may intersect the second transmit control line EML2 in a plan view. The second transmit control line EML2 intersecting the second connecting line CL2 may include a first extension EML2a, a second extension EML2b, and a bridge electrode BRE.

[0250] Figure 17 This is a block diagram illustrating an electronic device according to some embodiments.

[0251] Reference Figure 17 According to some embodiments, electronic device 900 may include processor 910, memory device 920, storage device 930, input / output (“I / O”) device 940, power supply 950, and display device 960. Here, display device 960 may correspond to… Figure 1 The display device DD. Electronic device 900 may also include multiple ports for communicating with video cards, sound cards, memory cards, universal serial bus (“USB”) devices, etc. According to some embodiments, electronic device 900 may be implemented as a television set. According to some embodiments, electronic device 900 may be implemented as a smartphone. However, the embodiments are not limited thereto; according to some embodiments, electronic device 900 may be implemented as a cellular phone, video phone, smart tablet, smartwatch, tablet personal computer (“PC”), car navigation system, computer monitor, laptop computer, head-mounted display (e.g., mounted display) (“HMD”), etc.

[0252] Processor 910 can perform various computing functions. According to some embodiments, processor 910 may be a microprocessor, a central processing unit (“CPU”), an application processor (“AP”), etc. Processor 910 may be integrated with other components via address buses, control buses, data buses, etc. According to some embodiments, processor 910 may be integrated with an expansion bus, such as a peripheral component interconnect (“PCI”) bus.

[0253] The memory device 920 may store data for the operation of the electronic device 900. According to some embodiments, the memory device 920 may include at least one non-volatile memory device (such as an erasable programmable read-only memory (“EPROM”) device, an electrically erasable programmable read-only memory (“EEPROM”) device, a flash memory device, a phase-change random access memory (“PRAM”) device, a resistive random access memory (“RRAM”) device, a nano-floating gate memory (“NFGM”) device, a polymer random access memory (“PoRAM”) device, a magnetic random access memory (“MRAM”) device, a ferroelectric random access memory (“FRAM”) device, etc.) and / or at least one volatile memory device (such as a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, a mobile DRAM device, etc.

[0254] According to some embodiments, storage device 930 may include a solid-state drive (“SSD”) device, a hard disk drive (“HDD”) device, a CD-ROM device, etc. According to some embodiments, I / O device 940 may include input devices such as a keyboard, keypad, mouse device, touchpad, touch screen, etc., and output devices such as a printer, speaker, etc.

[0255] Power supply 950 can provide power for the operation of electronic device 900. Display device 960 can be integrated with other components via a bus or other communication link. According to some embodiments, display device 960 may be included in I / O device 940.

[0256] Although some aspects of embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Therefore, the invention is not limited to such embodiments, but rather to the broader scope of the appended claims and various modifications and equivalent arrangements as will be apparent to those skilled in the art.

Claims

1. A thin-film transistor array, characterized in that, The thin-film transistor array includes: A first gate line extends in a first direction; The first data line extends in a second direction that intersects the first direction; A second data line extends in the second direction, and the second data line is spaced apart from the first data line in the first direction; The first data write transistor is electrically connected to the first gate line and the first data line; The second data write transistor is electrically connected to the first gate line and the second data line, and the second data write transistor and the first data write transistor are arranged in the first direction. A first driving transistor is electrically connected to the first data writing transistor, and the first driving transistor and the first data writing transistor are arranged in the second direction; A second driving transistor is electrically connected to a second data writing transistor, the second driving transistor and the first driving transistor are arranged in the first direction, and the second driving transistor and the second data writing transistor are arranged in the second direction; and A first operation control transistor is electrically connected to the first driving transistor and the second driving transistor, and the first operation control transistor and the first driving transistor are arranged in the second direction.

2. The thin-film transistor array according to claim 1, characterized in that, The first data write transistor, the first drive transistor, and the first operation control transistor are arranged in a line along the second direction, and The second data writing transistor and the second driving transistor are arranged in a line along the second direction.

3. The thin-film transistor array according to claim 1, characterized in that, The thin-film transistor array further includes: A first compensation transistor is electrically connected to the first data write transistor and the first drive transistor, and the first compensation transistor and the first data write transistor are arranged in a direction opposite to the second direction. A first emitter control transistor is electrically connected to the first drive transistor and the first compensation transistor, the first emitter control transistor and the first compensation transistor being arranged in a direction opposite to the second direction; A first initialization transistor is electrically connected to a first emitter control transistor, and the first initialization transistor and the first emitter control transistor are arranged in a direction opposite to the second direction; The second compensation transistor is electrically connected to the second data write transistor and the second drive transistor, and the second compensation transistor and the second data write transistor are arranged in the direction opposite to the second direction; A second emitter control transistor is electrically connected to the second drive transistor and the second compensation transistor, the second emitter control transistor and the second compensation transistor being arranged in a direction opposite to the second direction; and A second initialization transistor is electrically connected to the second emitter control transistor, and the second initialization transistor and the second emitter control transistor are arranged in a direction opposite to the second direction. Wherein, the first initialization transistor, the first emitter control transistor, the first compensation transistor, the first data write transistor, the first drive transistor, and the first operation control transistor are arranged in a line along the second direction, and The second initialization transistor, the second emitter control transistor, the second compensation transistor, the second data write transistor, and the second drive transistor are arranged in a line along the second direction.

4. The thin-film transistor array according to claim 1, characterized in that, The thin-film transistor array further includes: A first connecting line electrically connects the drain region of the first operation control transistor, the source region of the first driving transistor, and the source region of the second driving transistor to each other, and The first connecting line and the first gate line are on the same layer.

5. The thin-film transistor array according to claim 1, characterized in that, The thin-film transistor array further includes: A second gate line extends in the first direction and is spaced apart from the first gate line in the second direction; A third data write transistor is electrically connected to the second gate line and the first data line, and the third data write transistor and the first operation control transistor are arranged in the second direction. A fourth data write transistor is electrically connected to the second gate line and the second data line, and the fourth data write transistor and the third data write transistor are arranged in the first direction; A third driving transistor is electrically connected to the third data writing transistor, and the third driving transistor and the first operation control transistor are arranged in the second direction; A fourth driving transistor, electrically connected to the fourth data write transistor, the fourth driving transistor and the third driving transistor being arranged in the first direction; and A second operation control transistor is electrically connected to the third and fourth drive transistors, and the second operation control transistor and the first operation control transistor are arranged in the first direction.

6. The thin-film transistor array according to claim 5, characterized in that, The second operation control transistor is located between the second driving transistor and the fourth driving transistor.

7. The thin-film transistor array according to claim 5, characterized in that, The first data write transistor, the first drive transistor, the first operation control transistor, the third data write transistor, and the third drive transistor are arranged in a line along the second direction, and The second data write transistor, the second drive transistor, the second operation control transistor, the fourth data write transistor, and the fourth drive transistor are arranged in a line along the second direction.

8. The thin-film transistor array according to claim 5, characterized in that, The third data write transistor is located between the first operation control transistor and the third drive transistor, and The fourth data writing transistor is located between the second operation control transistor and the fourth driving transistor.

9. The thin-film transistor array according to claim 5, characterized in that, The third driving transistor is located between the first operation control transistor and the third data write transistor, and The fourth driving transistor is located between the second operation control transistor and the fourth data write transistor.

10. The thin-film transistor array according to claim 5, characterized in that, The thin-film transistor array further includes: The second connection line electrically connects the drain region of the second operation control transistor, the source region of the third driving transistor, and the source region of the fourth driving transistor to each other.

11. The thin-film transistor array according to claim 10, characterized in that, The second connection line is on the same layer as the first gate line and the second gate line.

12. The thin-film transistor array according to claim 10, characterized in that, The thin-film transistor array further includes: A transmit control line, extending in the first direction, is configured to provide transmit control signals to the gate electrodes of the first and second operating control transistors. In the plan view, the second connecting line intersects with the transmission control line.

13. The thin-film transistor array according to claim 12, characterized in that, The launch control line includes: The first extension portion is superimposed on the gate electrode of the first operation control transistor in the plan view; A second extension portion, on the same layer as the first extension portion, spaced apart from the first extension portion in the first direction, and stacked with the gate electrode of the second operational control transistor in the plan view; and A bridge electrode, located on a different layer from the first and second extension portions, electrically connects the first and second extension portions to each other. In the plan view, the second connecting line intersects with the bridge electrode.

14. A thin-film transistor array, characterized in that, The thin-film transistor array includes: A first gate line extends in a first direction; A second gate line extends in the first direction, and the second gate line is spaced apart from the first gate line in a second direction that intersects the first direction; The first data line extends in the second direction; A second data line extends in the second direction, and the second data line is spaced apart from the first data line in the first direction; The first driving transistor is electrically connected to the first gate line and the first data line; The second driving transistor is electrically connected to the first gate line and the second data line, and the second driving transistor and the first driving transistor are arranged in the first direction. A third driving transistor is electrically connected to the second gate line and the first data line, and the third driving transistor and the first driving transistor are arranged in the second direction. A fourth driving transistor is electrically connected to the second gate line and the second data line. The fourth driving transistor and the third driving transistor are arranged in the first direction, and the fourth driving transistor and the second driving transistor are arranged in the second direction. A first operation control transistor is electrically connected to the first driving transistor and the second driving transistor, the first operation control transistor being located between the first driving transistor and the third driving transistor; and A second operation control transistor is electrically connected to the third driving transistor and the fourth driving transistor, with the second operation control transistor located between the second driving transistor and the fourth driving transistor.

15. A display device, characterized in that, The display device includes: The first light-emitting element, the second light-emitting element, the third light-emitting element, and the fourth light-emitting element are adjacent to each other; The first driving transistor is electrically connected to the first light-emitting element; The second driving transistor is electrically connected to the second light-emitting element, and the second driving transistor and the first driving transistor are arranged in a first direction; A third driving transistor is electrically connected to the third light-emitting element, and the third driving transistor and the first driving transistor are arranged in a second direction intersecting the first direction; A fourth driving transistor is electrically connected to the fourth light-emitting element. The fourth driving transistor and the third driving transistor are arranged in the first direction, and the fourth driving transistor and the second driving transistor are arranged in the second direction. A first operation control transistor is electrically connected to the first driving transistor and the second driving transistor, the first operation control transistor being disposed between the first driving transistor and the third driving transistor; and A second operation control transistor is electrically connected to the third driving transistor and the fourth driving transistor, and the second operation control transistor is disposed between the second driving transistor and the fourth driving transistor.

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