Inverted DBR-LED chip
By eliminating the electrode metal layer and using tilted isolation trenches and conductive openings, the problem of easy breakage of the passivation reflection structure in traditional flip-chip DBR-LED chips was solved, thereby improving the chip's reliability and brightness.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- FOSHAN NATIONSTAR SEMICONDUCTOR CO LTD
- Filing Date
- 2025-04-17
- Publication Date
- 2026-05-19
AI Technical Summary
In traditional flip-chip DBR-LED chips, the protrusion of the electrode metal layer makes the passivation reflection structure prone to breakage, affecting chip reliability.
The electrode metal layer is eliminated, and an inclined isolation trench and conductive opening are used. The N-type metal layer and the P-type metal layer directly contact the semiconductor layer and the current spreading layer through a passivation and reflection structure. Through holes are set in the passivation and reflection structure, and the metal layer extends into the isolation trench.
This effectively reduces the risk of passivation reflective structure breakage, simplifies the process flow, reduces manufacturing costs, and improves the voltage and brightness stability of the chip.
Smart Images
Figure CN224265410U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of semiconductor technology, specifically to a flip-chip DBR-LED chip. Background Technology
[0002] Figure 1 The diagram shows a cross-sectional view of a traditional flip-chip DBR-LED chip. A traditional flip-chip DBR-LED chip (where DBR refers to a distributed Bragg reflector) typically includes a substrate 1, and an epitaxial layer 2, a current spreading layer 3, an electrode metal layer 4, a passivation reflective structure 5, and a pad metal layer 6, all sequentially stacked on the substrate 1. The pad metal layer 6 passes through the passivation reflective structure 5 and connects to the electrode metal layer 4. However, because the electrode metal layer protrudes from the epitaxial layer or current spreading layer, and the trenches and openings etched on the epitaxial layer are often vertical, the passivation reflective structure is prone to breakage during the process of covering the electrode metal layer, vertical trenches, and vertical openings, thus affecting the chip's reliability. Utility Model Content
[0003] The purpose of this invention is to overcome the shortcomings of the prior art. This invention provides a flip-chip DBR-LED chip, which can effectively reduce the risk of passivation reflection structure breakage by eliminating the electrode metal layer and tilting the sidewalls with grooves and openings, thereby improving the reliability of the chip.
[0004] This utility model provides a flip-chip DBR-LED, which includes a substrate and an epitaxial layer disposed on the substrate. Isolation trenches are provided around the epitaxial layer, and the isolation trenches expose the substrate. The sidewalls of the isolation trenches slope to the surface of the substrate.
[0005] The epitaxial layer includes an N-type semiconductor layer, a light-emitting layer, and a P-type semiconductor layer sequentially stacked on the substrate. An N-type conductive opening is provided in the epitaxial layer. The N-type conductive opening extends from the surface of the P-type semiconductor layer into the N-type semiconductor layer, and the sidewall of the N-type conductive opening transitions obliquely into the N-type semiconductor layer.
[0006] A current spreading layer is stacked on the P-type semiconductor layer, and the current spreading layer avoids the isolation trench and the N-type conductive opening;
[0007] The surface of the isolation trench, the surface of the current spreading layer, and the surface of the N-type conductive opening are covered with a passivation and reflection structure; an N-type via is provided in the passivation and reflection structure on the N-type conductive opening, and the N-type via exposes the N-type semiconductor layer; a P-type via is provided in the passivation and reflection structure on the current spreading layer, and the P-type via exposes the current spreading layer.
[0008] The surface of the passivated reflective structure is formed with independent N-type metal layers and P-type metal layers. The N-type metal layer is connected to the N-type semiconductor layer through the N-type via and extends into the isolation trench. The P-type metal layer is connected to the current spreading layer through the P-type via and extends into the isolation trench.
[0009] Specifically, the horizontal length of the epitaxial layer is A, the horizontal distance from the center of the N-type via to the geometric center of the epitaxial layer is L1, the horizontal distance from the center of the P-type via to the geometric center of the epitaxial layer is L2, and the horizontal spacing between the N-type metal layer and the P-type metal layer is L3. Then:
[0010]
[0011] Specifically, one N-type through hole and one P-type through hole constitute a group of conductive through holes, and the number of groups of conductive through holes is 1 to 4.
[0012] Specifically, the horizontal cross-section of the N-type through hole is circular, square, or rectangular, and the horizontal cross-section of the P-type through hole is circular, square, or rectangular.
[0013] Specifically, the sidewall of the N-type via is inclined to the surface of the N-type semiconductor layer, and the inclination angle of the sidewall of the N-type via is in the range of 20° to 50°.
[0014] The sidewall of the P-type via is inclined to the surface of the current spreading layer, and the inclination angle of the sidewall of the P-type via is in the range of 20° to 50°.
[0015] Specifically, the projection of the N-type metal layer onto the epitaxial layer completely covers the N-type conductive opening.
[0016] Specifically, the inclination angle of the sidewall of the isolation trench is in the range of 40° to 60°, and the inclination angle of the sidewall of the N-type conductive opening is in the range of 40° to 60°.
[0017] Specifically, a current blocking layer is embedded in the P-type semiconductor layer, the upper surface of the current blocking layer is flush with the upper surface of the P-type semiconductor layer, the upper surface of the current blocking layer directly contacts the current spreading layer, and the current blocking layer completely covers the projection of the P-type via on the epitaxial layer.
[0018] Specifically, the passivated reflective structure consists of a first passivation layer, a distributed Bragg reflector, and a second passivation layer stacked sequentially from bottom to top, wherein the distributed Bragg reflector has 3 to 20 pairs of film layers.
[0019] Specifically, the N-type metal layer comprises, from bottom to top, a first Cr layer, a first AlTi layer, a first Ni layer, and a first Au layer stacked sequentially, and the P-type metal layer comprises, from bottom to top, a second Cr layer, a second AlTi layer, a second Ni layer, and a second Au layer stacked sequentially.
[0020] Compared with the prior art, the beneficial effects of this utility model are:
[0021] The flip-chip DBR-LED of this invention eliminates the traditional electrode metal layer, allowing the N-type metal layer to directly contact the N-type semiconductor layer through the passivation reflection structure, and the P-type metal layer to directly contact the current spreading layer through the passivation reflection structure. This avoids the risk of passivation reflection structure breakage caused by electrode metal layer protrusion. Moreover, the sidewalls of the isolation trench slope to the surface of the substrate, and the sidewalls of the N-type conductive opening slope to the N-type semiconductor layer, reducing the vertical steep walls and effectively reducing the risk of passivation reflection structure breakage. Attached Figure Description
[0022] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0023] Figure 1 This is a schematic diagram of the cross-sectional structure of a traditional flip-chip DBR-LED;
[0024] Figure 2 This is a schematic diagram of the first cross-sectional structure of the flip-chip DBR-LED in this embodiment of the present invention;
[0025] Figure 3 This is a schematic diagram of the second cross-sectional structure of the flip-chip DBR-LED in this embodiment of the present invention;
[0026] Figure 4 This is a schematic diagram of the distribution structure of N-type and P-type through holes in Example 1;
[0027] Figure 5 This is a schematic diagram of the distribution structure of N-type and P-type through holes in Example 2;
[0028] Figure 6 This is a schematic diagram of the distribution structure of N-type and P-type through holes in Comparative Example 1;
[0029] Figure 7 This is a schematic diagram of the distribution structure of N-type and P-type through holes in Comparative Example 2.
[0030] In the attached figures, 10 is the substrate; 20 is the epitaxial layer; 21 is the N-type semiconductor layer; 22 is the light-emitting layer; 23 is the P-type semiconductor layer; 30 is the current spreading layer; 40 is the passivation and reflection structure; 41 is the first passivation layer; 42 is the distributed Bragg reflector; 43 is the second passivation layer; 51 is the N-type metal layer; 52 is the P-type metal layer; 60 is the current blocking layer; 71 is the N-type pit; 72 is the P-type pit; 100 is the isolation trench; 200 is the N-type conductive opening; 310 is the N-type via; and 320 is the P-type via. Detailed Implementation
[0031] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present utility model.
[0032] This invention provides a flip-chip DBR-LED. Figure 2 The diagram shows a first cross-sectional view of a flip-chip DBR-LED chip in an embodiment of the present invention. The flip-chip DBR-LED chip includes a substrate 10 and an epitaxial layer 20 disposed on the substrate 10. An isolation trench 100 is disposed around the epitaxial layer 20, and the isolation trench 100 exposes the substrate 10. The sidewalls of the isolation trench 100 slope to the surface of the substrate 10.
[0033] The epitaxial layer 20 includes an N-type semiconductor layer 21, a light-emitting layer 22, and a P-type semiconductor layer 23 sequentially stacked on the substrate 10. An N-type conductive opening 200 is provided in the epitaxial layer 20. The N-type conductive opening 200 extends from the surface of the P-type semiconductor layer 23 into the N-type semiconductor layer 21, and the sidewall of the N-type conductive opening 200 transitions obliquely into the N-type semiconductor layer 21.
[0034] A current spreading layer 30 is stacked on the P-type semiconductor layer 23, and the current spreading layer 30 avoids the isolation trench 100 and the N-type conductive opening 200.
[0035] The surfaces of the isolation trench 100, the current spreading layer 30, and the N-type conductive opening 200 are covered with a passivation and reflection structure 40; an N-type via 310 is provided in the passivation and reflection structure 40 on the N-type conductive opening 200, and the N-type via 310 exposes the N-type semiconductor layer 21; a P-type via 320 is provided in the passivation and reflection structure 40 on the current spreading layer 30, and the P-type via 320 exposes the current spreading layer 30;
[0036] The surface of the passivated reflective structure 40 is formed with an independent N-type metal layer 51 and a P-type metal layer 52. The N-type metal layer 51 is connected to the N-type semiconductor layer 21 through the N-type via 310 and extends into the isolation trench 100. The P-type metal layer 52 is connected to the current spreading layer 30 through the P-type via 320 and extends into the isolation trench 100.
[0037] The flip-chip DBR-LED of this invention eliminates the traditional electrode metal layer, allowing the N-type metal layer 51 to directly contact the N-type semiconductor layer 21 through the passivation and reflection structure 40, and the P-type metal layer 52 to directly contact the current spreading layer 30 through the passivation and reflection structure 40. This avoids the risk of breakage of the passivation and reflection structure 40 due to electrode metal layer protrusion. Moreover, eliminating the traditional electrode metal layer not only reduces the use of precious metals, photoresists, and other materials, but also simplifies the process flow, thereby effectively reducing the chip manufacturing cost.
[0038] In the flip-chip DBR-LED of this invention, the sidewalls of the isolation trench 100 are inclined to the surface of the substrate 10, and the sidewalls of the N-type conductive opening 200 are inclined to the N-type semiconductor layer 21. This reduces the steep vertical walls, making it easier for the passivation reflection structure 40 to be stably attached to the inclined walls, and also effectively reducing the risk of breakage of the passivation reflection structure 40.
[0039] In addition, both the N-type metal layer 51 and the P-type metal layer 52 extend into the isolation trench 100, which not only has a larger heat dissipation area, but also provides a certain degree of protection for the passivation reflection structure 40.
[0040] In some specific embodiments, please refer to Figure 2 The length of the epitaxial layer 20 in the horizontal direction is A, the horizontal distance from the center of the N-type via 310 to the geometric center of the epitaxial layer 20 is L1, the horizontal distance from the center of the P-type via 320 to the geometric center of the epitaxial layer 20 is L2, and the horizontal spacing between the N-type metal layer 51 and the P-type metal layer 52 is L3. Then:
[0041]
[0042] By constraining the N-type via 310 and the P-type via 320 to appropriate positions and controlling the horizontal spacing between the N-type metal layer 51 and the P-type metal layer 52, it is possible to ensure voltage stability and brightness stability after the removal of the electrode metal layer from the chip. Otherwise, voltage increase and brightness decrease are likely to occur.
[0043] Preferred, While ensuring chip voltage and brightness, it is also easy to process.
[0044] Furthermore, one N-type via 310 and one P-type via 320 constitute a group of conductive vias, and the number of groups of conductive vias is 1 to 4. Under the same L1, L2, and L3 conditions, as the number of groups of conductive vias increases, the chip voltage will gradually decrease, but the brightness will also decrease. The appropriate number of groups of conductive vias can be selected according to the specific voltage and brightness requirements.
[0045] In some specific embodiments, the horizontal cross-sectional shape of the N-type via 310 is circular, square, or rectangular, and the horizontal cross-sectional shape of the P-type via 320 is also circular, square, or rectangular, which can be selected according to specific needs. Preferably, the horizontal cross-sectional shape of both the N-type via 310 and the P-type via 320 is circular. Compared to other shapes, a circle has a larger area, which facilitates the connection of the N-type metal layer 51 to the N-type semiconductor layer 21 and also facilitates the connection of the P-type metal layer 52 to the current spreading layer 30.
[0046] In some specific embodiments, please refer to Figure 2 The sidewall of the N-type via 310 transitions at an angle to the surface of the N-type semiconductor layer 21. The angle range of the sidewall of the N-type via 310 is 20° to 50°, which is the range of angles at which the sidewall of the N-type via 310 deviates from the vertical plane. Optionally, the angle of the sidewall of the N-type via 310 can be 20°, 25°, 30°, 35°, 40°, 45°, or 50°, which is beneficial for improving the coverage effect of the N-type metal layer 51 at the corner and increasing the chip's thrust value. The sidewall of the P-type via 320 is inclined to the surface of the current spreading layer 30. The inclination angle of the sidewall of the P-type via 320 is in the range of 20° to 50°. This is the range of angles at which the sidewall of the P-type via 320 deviates from the vertical plane. Optionally, the inclination angle of the sidewall of the P-type via 320 can be 20°, 25°, 30°, 35°, 40°, 45° or 50°, which is beneficial to improve the coverage effect of the P-type metal layer 52 at the corner and to improve the push value of the chip.
[0047] In some specific embodiments, please refer to Figure 2The projection of the N-type metal layer 51 onto the epitaxial layer 20 completely covers the N-type conductive opening 200, which can ensure the current absorption efficiency.
[0048] In some specific embodiments, the inclination angle of the sidewall of the isolation trench 100 is in the range of 40° to 60°. This is the range of angles at which the sidewall of the isolation trench 100 deviates from the vertical plane. Optionally, the inclination angle of the sidewall of the isolation trench 100 can be 40°, 45°, 50°, 55°, or 60°, which is beneficial for covering the passivation reflective structure 40. This not only reduces the risk of breakage when covering the passivation reflective structure 40, but also reduces the risk of the passivation reflective structure 40 chipping during the cleaving process. The inclination angle of the sidewall of the N-type conductive opening 200 is in the range of 40° to 60°. This is the range of angles at which the sidewall of the N-type conductive opening 200 deviates from the vertical plane. Optionally, the inclination angle of the sidewall of the N-type conductive opening 200 can be 40°, 45°, 50°, 55°, or 60°, which is beneficial for covering the passivation reflective structure 40 and can reduce the risk of breakage when covering the passivation reflective structure 40.
[0049] Figure 3 This diagram shows a second cross-sectional view of a flip-chip DBR-LED according to an embodiment of the present invention. A current blocking layer 60 is embedded in the P-type semiconductor layer 23. The upper surface of the current blocking layer 60 is flush with the upper surface of the P-type semiconductor layer 23, and directly contacts the current spreading layer 30. The current blocking layer 60 completely covers the projection of the P-type via 320 onto the epitaxial layer 20. The current blocking layer 60, embedded in the P-type semiconductor layer 23, maintains the flatness of the upper surface of the P-type semiconductor layer 23, allowing the current spreading layer 30 to be smoothly stacked on the P-type semiconductor layer 23. This allows the passivation reflection structure 40 to be covered on the flat current spreading layer 30, reducing the risk of breakage when covering the passivation reflection structure 40. Furthermore, the current blocking layer 60 reduces vertical current transmission, allowing the current to be fully spread in the current spreading layer 30 before being injected into the P-type semiconductor layer 23, which helps improve the brightness of the chip.
[0050] Specifically, the current blocking layer 60 is made of silicon dioxide, which has good insulation properties and can effectively block the vertical transmission of current, reducing the current density in and around the P-type via 320, alleviating the current congestion effect, and allowing more current to spread laterally, which is beneficial to improving the brightness of the chip.
[0051] In some specific embodiments, please refer to Figure 2 and Figure 3The passivated reflective structure 40 consists of a first passivation layer 41, a distributed Bragg reflector 42, and a second passivation layer 43 stacked sequentially from bottom to top. The distributed Bragg reflector 42 has 3 to 20 pairs of film layers. The first passivation layer 41 and the second passivation layer 43 are both made of silicon dioxide, which has good insulation properties and high light transmittance. The distributed Bragg reflector 42 is composed of pairs of silicon dioxide layers and titanium dioxide layers. The reflectivity of the distributed Bragg reflector 42 increases with the increase of the number of film layer pairs, and an appropriate number of film layer pairs can be selected according to specific needs. Preferably, there are 10 to 20 pairs of reflective silicon dioxide layers and reflective titanium dioxide layers. The high reflectivity bandwidth of 10 to 20 pairs of film layers ranges from 420 to 550 nm, and the reflectivity ranges from 85% to 99.5%, making it widely applicable.
[0052] In some specific embodiments, the N-type metal layer 51 comprises, from bottom to top, a first Cr layer, a first AlTi stack, a first Ni layer, and a first Au layer stacked sequentially; the P-type metal layer 52 comprises, from bottom to top, a second Cr layer, a second AlTi stack, a second Ni layer, and a second Au layer stacked sequentially. The Cr layer enhances adhesion, the AlTi stack improves structural stability, the Ni layer effectively protects the underlying AlTi stack, and the Au layer improves welding contact.
[0053] Specifically, the first AlTi stack has 3 to 5 pairs, and the second AlTi stack has 3 to 5 pairs, which can effectively improve the compactness of the film and release internal stress.
[0054] In some specific embodiments, the substrate 10 is a sapphire patterned substrate 10, which is beneficial to improving the light output power and luminous efficiency of the chip; the current spreading layer 30 is made of ITO, which has high conductivity, high visible light transmittance, high mechanical hardness and good chemical stability.
[0055] In some specific embodiments, please refer to Figure 2 The upper ends of the N-type metal layer 51 and the P-type metal layer 52 are flush, which facilitates coplanar soldering during flip-chip DBR-LED chip packaging.
[0056] Specifically, the N-type metal layer 51 has an N-type recess 71 located directly above the N-type through hole 310; the P-type metal layer 52 has a P-type recess 72 located directly above the P-type through hole 320; during welding, the N-type recess 71 and the P-type recess 72 can provide more contact area, which is beneficial to enhancing the welding contact effect.
[0057] Furthermore, the N-type recess 71 is provided with a first solder layer, and the P-type recess 72 is provided with a second solder layer. Pre-setting the solder can improve the efficiency of subsequent eutectic welding.
[0058] This invention relates to a flip-chip DBR-LED that eliminates the traditional electrode metal layer. The N-type metal layer 51 passes through the passivation and reflection structure 40 to directly contact the N-type semiconductor layer 21, and the P-type metal layer 52 passes through the passivation and reflection structure 40 to directly contact the current spreading layer 30. This avoids the risk of breakage of the passivation and reflection structure 40 due to electrode metal layer protrusion. Furthermore, eliminating the traditional electrode metal layer not only reduces the use of precious metals and photoresist but also simplifies the manufacturing process, effectively reducing chip fabrication costs. In addition, the N-type via 310 and P-type via 320 reach the epitaxial layer 2. The horizontal distance between the geometric centers is subject to specific constraints, which control the horizontal spacing between the N-type metal layer 51 and the P-type metal layer 52. This helps ensure voltage stability and brightness stability after the removal of the electrode metal layer from the chip. Furthermore, the sidewalls of both the N-type via 310 and the P-type via 320 are inclined, which helps improve the coverage effect of the N-type metal layer 51 and the P-type metal layer 52 at the corners and increases the chip's thrust value. Moreover, both the N-type metal layer 51 and the P-type metal layer 52 extend into the isolation trench 100, which not only provides a larger heat dissipation area but also provides some protection for the passivation reflection structure 40.
[0059] In the flip-chip DBR-LED of this invention, the sidewalls of the isolation trench 100 are inclined to the surface of the substrate 10, and the sidewalls of the N-type conductive opening 200 are inclined to the N-type semiconductor layer 21. This reduces the steep vertical walls, making it easier for the passivation reflection structure 40 to be stably attached to the inclined walls, and also effectively reducing the risk of breakage of the passivation reflection structure 40.
[0060] Furthermore, the current blocking layer 60 is embedded in the P-type semiconductor layer 23, maintaining the flatness of the upper surface of the P-type semiconductor layer 23. This allows the current spreading layer 30 to be flatly stacked on the P-type semiconductor layer 23, enabling the passivation reflection structure 40 to be covered on the flat current spreading layer 30. This helps reduce the risk of breakage when covering the passivation reflection structure 40. The current blocking layer 60 reduces vertical current transmission, allowing the current to be fully spread in the current spreading layer 30 before being injected into the P-type semiconductor layer 23, which helps improve the brightness of the chip. The passivation reflection structure 40 consists of a first passivation layer 41, a distributed Bragg reflector 42, and a second passivation layer 43. Its high reflectivity bandwidth ranges from 420 to 550 nm, and its reflectivity ranges from 85% to 99.5%, exhibiting excellent reflection effects. The N-type metal layer 51 and the P-type metal layer 52 have essentially the same film structure, possessing good adhesion properties, good structural stability, and ease of soldering. Combined with the N-type recess 71 and the P-type recess 72, they can provide more contact area, which helps to further enhance the soldering contact effect.
[0061] Example 1
[0062] Figure 4 This diagram illustrates the distribution structure of N-type and P-type vias in Embodiment 1. The horizontal spacing between the N-type and P-type metal layers satisfies... Configure a set of conductive vias: one N-type via and one P-type via.
[0063] satisfy
[0064] Example 2
[0065] Figure 5 This diagram illustrates the distribution structure of N-type and P-type vias in Embodiment 2. The horizontal spacing between the N-type and P-type metal layers satisfies... Two sets of conductive vias are provided: two N-type vias and two P-type vias.
[0066] satisfy
[0067] Comparative Example 1
[0068] Figure 6 This diagram illustrates the distribution structure of N-type and P-type vias in Comparative Example 1. The horizontal spacing between the N-type and P-type metal layers satisfies... Two sets of conductive vias are provided: two N-type vias and two P-type vias.
[0069] satisfy
[0070] Comparative Example 2
[0071] Figure 7The diagram shows the distribution structure of N-type and P-type vias in Comparative Example 2. The horizontal spacing between the N-type and P-type metal layers satisfies... Four sets of conductive vias are provided: four N-type vias and four P-type vias.
[0072] Two sets of conductive vias satisfy the following conditions:
[0073] The other two sets of conductive vias satisfy the requirements.
[0074] Comparison of voltage and brightness results
[0075]
[0076] (1) Compared with traditional chips, the brightness of the chips in Examples 1 and 2 is effectively improved, and the chip voltage increase is minimal. This indicates that by constraining the N-type and P-type vias to specific positions and controlling the horizontal spacing between the N-type and P-type metal layers, the desired effect can be achieved.
[0077]
[0078] It can effectively improve chip brightness. Although the chip voltage increases slightly, the advantage of improved chip brightness is obvious.
[0079] (2) Compared with Example 1, the chip voltage of Example 2 decreased slightly, while the chip brightness decreased significantly. This indicates that under the same L1, L2 and L3 conditions, as the number of conductive vias increases, the chip brightness is more likely to decrease and the decrease is more significant, while the chip voltage does not change significantly.
[0080] (3) Compared with Example 2, the chip voltage of Comparative Example 1 increased significantly, while the chip brightness decreased slightly. This indicates that the proximity of N-type and P-type vias is beneficial to reducing chip voltage.
[0081] (4) Compared with Example 2, the chip voltage of Comparative Example 2 was slightly increased, while the chip brightness was significantly decreased. This indicates that increasing the chip voltage... The conductive vias can cause the chip brightness to drop significantly, while the chip voltage changes little.
[0082] The foregoing has provided a detailed description of a flip-chip DBR-LED chip according to the embodiments of this utility model. Specific examples have been used to illustrate the principle and implementation of this utility model. The description of the above embodiments is only for the purpose of helping to understand the method and core idea of this utility model. At the same time, for those skilled in the art, there will be changes in the specific implementation and application scope based on the idea of this utility model. Therefore, the content of this specification should not be construed as a limitation of this utility model.
Claims
1. A flip-chip DBR-LED, characterized in that, The flip-chip DBR-LED includes a substrate and an epitaxial layer disposed on the substrate. Isolation trenches are disposed around the epitaxial layer, and the isolation trenches expose the substrate. The sidewalls of the isolation trenches slope to the surface of the substrate. The epitaxial layer includes an N-type semiconductor layer, a light-emitting layer, and a P-type semiconductor layer sequentially stacked on the substrate. An N-type conductive opening is provided in the epitaxial layer. The N-type conductive opening extends from the surface of the P-type semiconductor layer into the N-type semiconductor layer, and the sidewall of the N-type conductive opening transitions obliquely into the N-type semiconductor layer. A current spreading layer is stacked on the P-type semiconductor layer, and the current spreading layer avoids the isolation trench and the N-type conductive opening; The surface of the isolation trench, the surface of the current spreading layer, and the surface of the N-type conductive opening are covered with a passivation and reflection structure; an N-type via is provided in the passivation and reflection structure on the N-type conductive opening, and the N-type via exposes the N-type semiconductor layer; a P-type via is provided in the passivation and reflection structure on the current spreading layer, and the P-type via exposes the current spreading layer. The surface of the passivated reflective structure is formed with independent N-type metal layers and P-type metal layers. The N-type metal layer is connected to the N-type semiconductor layer through the N-type via, and the N-type metal layer extends into the isolation trench. The P-type metal layer is connected to the current spreading layer through the P-type via, and the P-type metal layer extends into the isolation trench.
2. The flip-chip DBR-LED chip as described in claim 1, characterized in that, The horizontal length of the epitaxial layer is A, the horizontal distance from the center of the N-type via to the geometric center of the epitaxial layer is L1, the horizontal distance from the center of the P-type via to the geometric center of the epitaxial layer is L2, and the horizontal spacing between the N-type metal layer and the P-type metal layer is L3. Then:
3. The flip-chip DBR-LED chip as described in claim 2, characterized in that, One N-type through hole and one P-type through hole constitute a group of conductive through holes, and the number of groups of conductive through holes is 1 to 4.
4. The flip-chip DBR-LED chip as described in claim 1, characterized in that, The horizontal cross-section of the N-type through hole is circular, square, or rectangular, and the horizontal cross-section of the P-type through hole is circular, square, or rectangular.
5. The flip-chip DBR-LED chip as described in claim 1, characterized in that, The sidewall of the N-type via is inclined to the surface of the N-type semiconductor layer, and the inclination angle of the sidewall of the N-type via is in the range of 20° to 50°. The sidewall of the P-type via is inclined to the surface of the current spreading layer, and the inclination angle of the sidewall of the P-type via is in the range of 20° to 50°.
6. The flip-chip DBR-LED chip as described in claim 1, characterized in that, The projection of the N-type metal layer onto the epitaxial layer completely covers the N-type conductive opening.
7. The flip-chip DBR-LED chip as described in claim 1, characterized in that, The inclination angle of the sidewall of the isolation trench is in the range of 40° to 60°, and the inclination angle of the sidewall of the N-type conductive opening is in the range of 40° to 60°.
8. The flip-chip DBR-LED chip as described in claim 1, characterized in that, A current blocking layer is embedded in the P-type semiconductor layer. The upper surface of the current blocking layer is flush with the upper surface of the P-type semiconductor layer. The upper surface of the current blocking layer directly contacts the current spreading layer. The current blocking layer completely covers the projection of the P-type via on the epitaxial layer.
9. The flip-chip DBR-LED chip as described in claim 1, characterized in that, The passivated reflective structure consists of a first passivation layer, a distributed Bragg reflector, and a second passivation layer stacked sequentially from bottom to top. The distributed Bragg reflector has 3 to 20 pairs of film layers.
10. The flip-chip DBR-LED chip as described in claim 1, characterized in that, The N-type metal layer comprises, from bottom to top, a first Cr layer, a first AlTi layer, a first Ni layer, and a first Au layer stacked sequentially, and the P-type metal layer comprises, from bottom to top, a second Cr layer, a second AlTi layer, a second Ni layer, and a second Au layer stacked sequentially.