Semiconductor device

Abstract

A semiconductor device includes a semiconductor substrate layer and a liner layer. The semiconductor substrate layer includes a metal interconnect feature embedded in the semiconductor substrate layer, and a liner layer on the metal interconnect feature. The semiconductor device further includes an etch stop layer and a dielectric layer. The etch stop layer is located on the liner layer and the semiconductor substrate layer, and the dielectric layer is located on the etch stop layer. The semiconductor device also includes a via structure exposing the metal interconnect feature through the dielectric layer, the etch stop layer, and the liner layer, where the via structure has an hourglass profile. The metal interconnect feature extends in a first direction, the via structure has an enlarged bottom critical dimension along a second direction, and the first direction is perpendicular to the second direction.

Description

Technical Field

[0001] Some embodiments disclosed herein relate to a semiconductor device. Background Technology

[0002] As consumer devices become smaller in response to consumer demand, the size of individual components in these devices must also decrease. The semiconductor devices that make up the main components of devices such as mobile phones, computer tablets and the like have been compressed to smaller and smaller sizes, and the corresponding pressure on individual components (such as transistors, resistors, capacitors, etc.) will also decrease.

[0003] One enabling technique used in the manufacturing process of semiconductor devices is to form vias or holes that pass through several layers to provide interlayer conductivity against the underlying conductive layer.

[0004] However, as miniaturization reaches a certain level, previously relatively simple processes become increasingly complex. Pitch reduction is an important miniaturization method, but it brings many challenges, such as thinner isolation spaces and increased concerns about leakage. Thus, advancements in the formation of bottom-aligned vias are necessary to reduce contact resistance and prevent leakage due to small isolation spaces, and further improvements are needed to meet desired design standards so as to continue the development towards increasingly smaller devices. Utility Model Content

[0005] Some embodiments disclosed herein are semiconductor devices including a semiconductor substrate layer and a pad layer. The semiconductor substrate layer includes metal interconnect features embedded therein, and the pad layer is located on the metal interconnect features. The semiconductor device further includes an etch stop layer and a dielectric layer. The etch stop layer is located on the pad layer and the semiconductor substrate layer, and the dielectric layer is located on the etch stop layer. The semiconductor device also includes a via structure that exposes the metal interconnect features through the dielectric layer, the etch stop layer, and the pad layer, wherein the via structure has an hourglass-shaped profile. The metal interconnect features extend in a first direction, and the via structure has an enlarged bottom critical dimension along a second direction, with the first direction perpendicular to the second direction.

[0006] Another embodiment of this disclosure is a semiconductor device including a semiconductor substrate layer and a pad layer. The semiconductor substrate layer includes metal interconnect features embedded therein, and the pad layer is located on the metal interconnect features. The semiconductor device further includes an etch stop layer and a dielectric layer. The etch stop layer is located on the pad layer and the semiconductor substrate layer, wherein the etch stop layer has a stepped structure at the edge of the pad layer. The dielectric layer is located on the etch stop layer. The semiconductor device also includes a via structure that exposes the metal interconnect features through the dielectric layer, the etch stop layer, and the pad layer, wherein the via structure has an hourglass-shaped profile.

[0007] Another embodiment of this disclosure is a semiconductor device including a semiconductor substrate layer and a pad layer. The semiconductor substrate layer includes metal interconnect features embedded therein, and the pad layer is located on the metal interconnect features. The semiconductor device further includes an etch stop layer and a dielectric layer. The etch stop layer is located on the pad layer and the semiconductor substrate layer, and the dielectric layer is located on the etch stop layer. The semiconductor device also includes a via structure that exposes the metal interconnect features through the dielectric layer, the etch stop layer, and the pad layer, wherein the via structure has an hourglass-shaped profile. Attached Figure Description

[0008] Some embodiments of this disclosure are best understood when read in conjunction with the accompanying drawings, based on the following detailed description. It should be emphasized that, in accordance with standard industry practice, the various features are not drawn to scale and are for illustrative purposes only. In practice, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.

[0009] Figure 1 This describes the process flow for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0010] Figure 2A , Figure 2B and Figure 2C Cross-sectional and top views are shown of sequentially operating process stages according to some embodiments of the present disclosure;

[0011] Figure 3A and Figure 3B A cross-sectional view showing the sequential operation of process stages according to some embodiments of this disclosure;

[0012] Figure 4A and Figure 4B A cross-sectional view showing the sequential operation of process stages according to some embodiments of this disclosure;

[0013] Figure 5A and Figure 5B A cross-sectional view showing the sequential operation of process stages according to some embodiments of this disclosure;

[0014] Figure 6A and Figure 6B A cross-sectional view showing the sequential operation of process stages according to some embodiments of this disclosure;

[0015] Figure 7A and Figure 7B A cross-sectional view showing the sequential operation of process stages according to some embodiments of this disclosure;

[0016] Figure 8A , Figure 8B and Figure 8CCross-sectional and top views are shown of sequentially operating process stages according to some embodiments of the present disclosure;

[0017] Figure 9A , Figure 9B , Figure 10 , Figure 11A , Figure 11B , Figure 12A and Figure 12B Examples of bottom self-aligned through-holes according to some embodiments of this disclosure are described.

[0018] [Symbol Explanation]

[0019] 100: Process Flow

[0020] 200: Structure

[0021] 201:Substrate

[0022] 202: Dielectric layer

[0023] 203: Barrier Layer

[0024] 204: First Pad

[0025] 205: Second Pad

[0026] 206: Metal layer

[0027] 210, 220, 230, 1102, 1202: Metal interconnect characteristics

[0028] 301: Cap layer / Cobalt layer

[0029] 401, 1104: First etch stop layer

[0030] 402, 1105: Stepped structure

[0031] 501: Second Etching Stop Layer

[0032] 601: Low-k dielectric layer

[0033] 701, 702, 703: Through-hole grooves

[0034] 801, 802, 803, 1101, 1201: Bottom self-aligning through holes

[0035] 804, 806: Bottom section

[0036] 805: Bottom

[0037] 810, 820: Top metal interconnect features

[0038] 901, 902, 911, 1001: Close-up views

[0039] 903, 913: Hourglass-shaped outline

[0040] 1002: Sidewall

[0041] 1002a: First sidewall portion

[0042] 1002b: Second sidewall portion

[0043] 1003, 1005: Top surface

[0044] 1004: Waist plane

[0045] 1203, 1204: Outline

[0046] A, B: Angles

[0047] d1, d2: Critical dimensions

[0048] h1, h2: Thickness

[0049] S110, S120, S130, S140, S150: Operation

[0050] W1, W2: Width

[0051] x, y, z: Direction

[0052] AA', BB', YY': plane Detailed Implementation

[0053] It should be understood that the following disclosure provides many different embodiments or instances for implementing various features of this disclosure. Specific embodiments or instances of elements and configurations are described below to simplify some embodiments of this disclosure. Of course, these specific instances are merely examples and are not intended to be limiting. For example, the dimensions of a component are not limited to the disclosed range or values, but may depend on process conditions and / or the desired nature of the apparatus. Furthermore, the formation of a first feature above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features can be formed between the first and second features so that the first and second features do not need to be in direct contact. For simplicity and clarity, various features may be drawn arbitrarily at different scales.

[0054] Additionally, for ease of description, spatially relative terms (such as "below," "under," "bottom," "above," "upper," and the like) may be used in some embodiments of this disclosure to describe the relationship between one component or feature and another, as illustrated in the accompanying drawings. Besides the orientations depicted in the drawings, the spatially relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and therefore the spatially relative descriptive terms used in some embodiments of this disclosure may be interpreted accordingly. Furthermore, the term "made of" may mean "comprising" or "consisting of."

[0055] Conventionally, current leakage between the via layer and the metal layer caused by small isolation gaps is controlled using precise critical dimension (CD) control in lithography and etching processes. However, unavoidable variations in critical dimension uniformity, overlap, and stability can also lead to leakage between the via layer and the metal layer. In some instances, vias are elliptical in the non-critical leakage direction to reduce contact resistance. However, due to variations in critical dimension uniformity, overlap, and stability, as well as lithography size constraints, the process window is insufficient to maintain leakage margin and meet low contact resistance requirements. Some embodiments disclosed herein provide an improved via structure and method of forming thereof, thereby reducing contact resistance and preventing leakage. For example, a bottom self-aligned via (BSAV) structure can align the bottom of the via with the underlying metal interconnect layer in a dual damascene process and architecture, such that the critical dimension of the via bottom can be aligned with the critical dimension of the underlying metal interconnect layer.

[0056] In some embodiments of this disclosure, self-aligned dual damascene vias are formed. Those skilled in the art will understand that some embodiments disclosed herein can be applied to the formation of other structures, including dual damascene structures that do not serve as via openings between metal layers.

[0057] Figure 1 This describes a process flow 100 for manufacturing a semiconductor device according to some embodiments of the present disclosure. Figure 2A , Figure 2B and Figure 2C This diagram shows a cross-sectional view illustrating the sequential operation of process stages in manufacturing a semiconductor device according to some embodiments of this disclosure. Operation S110 is described as follows... Figure 2A , Figure 2B and Figure 2C The structure shown is 200. Figure 2C The top view of structure 200 is shown. Figure 2A Show along Figure 2CThe cross-sectional view of structure 200 cut by plane BB' is shown. Figure 2B Show along Figure 2C The cross-sectional view of structure 200 cut by plane AA' is shown.

[0058] In some embodiments, structure 200 is a semiconductor substrate layer including substrate 201. Substrate 201 may include all underlying layers, devices, bonding surfaces, and other features.

[0059] In some embodiments, dielectric layer 202 is deposited on the top surface of substrate 201. In some instances, dielectric layer 202 is a silicon oxide layer.

[0060] In some embodiments, structure 200 further includes a plurality of metal interconnect features (e.g., metal interconnect feature 210, metal interconnect feature 220, and / or metal interconnect feature 230) embedded in structure 200. In some embodiments, the plurality of metal interconnect features (e.g., metal interconnect feature 210, metal interconnect feature 220, and / or metal interconnect feature 230) are formed using a process including photolithography, etching, and deposition. In some embodiments, the plurality of metal interconnect features (e.g., metal interconnect feature 210, metal interconnect feature 220, and / or metal interconnect feature 230) are electrodes of a capacitor, resistor, or a portion thereof. Alternatively, the plurality of metal interconnect features (e.g., metal interconnect feature 210, metal interconnect feature 220, and / or metal interconnect feature 230) may be doped regions (such as source or drain) or gate electrodes (such as the metal gate of a fin field-effect transistor). In some embodiments, the plurality of metal interconnect features (e.g., metal interconnect feature 210, metal interconnect feature 220, and / or metal interconnect feature 230) are silicide features disposed on respective source, drain, or gate electrodes.

[0061] In some embodiments, such as Figure 2CAs shown, a plurality of metal interconnect features (e.g., metal interconnect features 210, 220, and / or 230) include a first metal interconnect feature 210 extending along direction x, a second metal interconnect feature 220 extending along direction x, and a third metal interconnect feature 230 extending along direction x. Direction x is a non-critical leakage direction. In some embodiments, the plurality of metal interconnect features (e.g., metal interconnect features 210, 220, and / or 230) are equidistant from each other along direction y. Direction y, perpendicular to direction x, is a critical leakage direction. Direction z is perpendicular to both direction x and direction y. In some embodiments, the plurality of metal interconnect features (e.g., metal interconnect features 210, 220, and / or 230) are formed in dielectric layer 202 using suitable techniques. The plurality of metal interconnect features (e.g., metal interconnect features 210, 220, and / or 230) may be in electrical contact with substrate 201, including any or all underlying layers, devices, bonding surfaces, and / or other features of substrate 201.

[0062] In some embodiments, such as Figure 2A As shown, along the direction y, the first metal interconnect feature 210 has a width W1, and the second metal interconnect feature 220 has a width W2. In some embodiments, the width W1 is greater than the width W2.

[0063] In some embodiments, such as Figure 2A As shown, the width of the third metal interconnect feature 230 along the direction y is equal to the width W2 of the second metal interconnect feature 220.

[0064] In some embodiments, such as Figure 2A and Figure 2B As shown, each of the plurality of metal interconnect features (e.g., metal interconnect feature 210, metal interconnect feature 220, and / or metal interconnect feature 230) includes a metal layer 206. For example, the metal layer 206 includes aluminum (Al), copper (Cu), tungsten (W), combinations thereof, and / or the like. In some embodiments, the metal layer 206 is further surrounded by a barrier layer 203. The barrier layer 203 prevents diffusion of the metal layer 206 and provides material adhesion for the metal layer 206. The barrier layer 203 may include titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), combinations thereof, and / or the like. In some instances, the thickness of the barrier layer 203 ranges from about 0.1 nanometers (nm) to about 4 nanometers. In some instances, the thickness of the barrier layer 203 ranges from about 0.3 nanometers to about 2 nanometers.

[0065] In some embodiments, each of the plurality of metal interconnect features (e.g., metal interconnect feature 210, metal interconnect feature 220, and / or metal interconnect feature 230) further includes a first pad 204 and a second pad 205 formed between the metal layer 206 and the barrier layer 203. In some embodiments, the first pad 204 is formed on the barrier layer 203, and the second pad 205 is subsequently formed on the first pad 204.

[0066] In some embodiments, the first pad 204 is a cobalt (Co) layer. In some instances, the thickness of the first pad 204 ranges from about 0.05 nanometers to about 2 nanometers. In some instances, the thickness of the first pad 204 ranges from about 0.1 nanometers to about 1 nanometer.

[0067] In some embodiments, the second pad 205 is a ruthenium (Ru) layer. In some instances, the thickness of the second pad 205 ranges from about 0.05 nanometers to about 2 nanometers. In some instances, the thickness of the second pad 205 ranges from about 0.1 nanometers to about 1 nanometer.

[0068] It should be noted that, although Figure 2A , Figure 2B and Figure 2C The section and top view of structure 200 illustrate a portion of structure 200, but those skilled in the art will recognize many variations, substitutions and modifications.

[0069] Return to reference Figure 1 In some embodiments, during operation S120, a cobalt (Co) layer is deposited on multiple metal interconnect features using a suitable deposition technique.

[0070] Figure 3A and Figure 3B A cross-sectional view is shown of a process stage in which a cap layer is formed in sequential operations according to some embodiments of the present disclosure.

[0071] like Figure 3A and Figure 3B As shown, a cap layer 301 is deposited on the first metal interconnect feature 210, the second metal interconnect feature 220, and the third metal interconnect feature 230. In some embodiments, the cap layer 301 is made of cobalt. In some embodiments, the cobalt layer 301 (which may be interchangeably referred to as the cap layer) covers the metal layer 206 of multiple metal interconnect features (e.g., metal interconnect feature 210, metal interconnect feature 220, and / or metal interconnect feature 230). In some instances, the cobalt layer 301 is a raised cap layer that covers only the first metal interconnect feature 210, the second metal interconnect feature 220, and / or the third metal interconnect feature 230.

[0072] In some embodiments, the thickness of the cobalt layer 301 ranges from about 0.2 nanometers to about 5 nanometers. In some embodiments, the thickness of the cobalt layer 301 ranges from about 0.5 nanometers to about 3 nanometers, such that the contact resistance (R) of the bottom self-aligned via is... c This can be minimized, thereby improving the performance of semiconductor devices. In some instances, if the thickness of the cobalt layer 301 is greater than 5 nanometers, the bottom self-aligned vias formed later will be deeper and therefore more difficult to completely fill. In some instances, if the thickness of the cobalt layer 301 is less than 0.2 nanometers, the cobalt layer 301 will provide insufficient leakage prevention between the via layer and the metal layer. If the thickness of the cobalt layer is greater than the disclosed range, the layer may be unnecessarily thick and may not provide any improvement in leakage prevention, while increasing the manufacturing cost of the semiconductor device.

[0073] Return to reference Figure 1 In some embodiments, during operation S130, a first etch stop layer 401 is subsequently formed on the cap layer or cobalt layer 301 and the dielectric layer 202. In some embodiments, the cap layer 301 is made of a material that has different etch selectivity to certain etch solutions compared to the first etch stop layer 401. In some embodiments, the cap layer 301 has high selectivity to etch solutions having a pH in the range of about 5 to about 6.8.

[0074] Figure 4A and Figure 4B A cross-sectional view is shown of a process stage in which a first etch stop layer is formed in a sequential operation according to some embodiments of the present disclosure.

[0075] like Figure 4A and Figure 4B As shown, a first etch stop layer 401 is deposited on the cobalt layer 301 and the dielectric layer 202. In some embodiments, the first etch stop layer 401 is conformally formed on the cobalt layer 301 and the dielectric layer 202. For example, the first etch stop layer 401 covers a portion of the top surface of the cobalt layer 301 and the dielectric layer 202 exposed by the cobalt layer 301.

[0076] In some embodiments, the first etch stop layer 401 has a stepped structure 402 around the edge of the cobalt layer 301. For example, the stepped structure 402 limits the bottom critical size of the subsequently formed bottom self-aligned via, thereby reducing the risk of short circuit between the bottom self-aligned via and the adjacent third metal interconnect feature 230, and preventing current leakage between the second metal interconnect feature 220 and the adjacent third metal interconnect feature 230.

[0077] In some embodiments, the first etch stop layer 401 is an aluminum-based etch stop layer. For example, in some embodiments, the first etch stop layer 401 is an aluminum nitride (AlN) layer. In other embodiments, the first etch stop layer 401 is an aluminum oxynitride (AlON) layer, an aluminum oxide (Al2O3) layer, a combination thereof, and / or the like. In some embodiments, the first etch stop layer 401 is hafnium oxide (HfO). x ) layer, zirconium oxide (ZrO) x Layers, combinations thereof, and / or their similarities.

[0078] In some embodiments, the thickness of the first etch stop layer 401 is between about 0.2 nanometers and about 5 nanometers. In some embodiments, the thickness of the first etch stop layer 401 is between about 0.5 nanometers and about 3 nanometers.

[0079] Return to reference Figure 1 In some embodiments, during operation S140, a low-k dielectric layer with via trenches is formed on the cobalt layer 301 and the dielectric layer 202.

[0080] Figure 5A and Figure 5B A cross-sectional view is shown of a process stage in which a second etch stop layer is formed in a sequential operation according to some embodiments of the present disclosure.

[0081] In some embodiments, such as Figure 5A and Figure 5B As shown, a second etch stop layer 501 is subsequently formed on the first etch stop layer 401 before the low-k dielectric layer is formed. For example, the second etch stop layer 501 is conformally formed on the first etch stop layer 401. In some instances, the second etch stop layer 501 is a SiOC-based etch stop layer. In some embodiments, the second etch stop layer 501 is deposited using any suitable technique, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or epitaxial growth. In some embodiments, the second etch stop layer 501 comprises an oxide layer comprising carbon, oxygen, silicon, other suitable materials, or combinations thereof.

[0082] Figure 6A and Figure 6B A cross-sectional view is shown of a process stage in which a low-k dielectric layer is formed in a sequential operation according to some embodiments of the present disclosure.

[0083] In some embodiments, such as Figure 6A and Figure 6BAs shown, a low-k dielectric layer 601 is subsequently formed on the second etch stop layer 501. In some instances, the second etch stop layer 501 has a lower etch rate than the low-k dielectric layer 601 in subsequent etch processes to form via trenches in the low-k dielectric layer 601.

[0084] Figure 7A and Figure 7B A cross-sectional view is shown illustrating a process stage in forming via trenches in a sequentially operated low-k dielectric layer 601 according to some embodiments of the present disclosure.

[0085] like Figure 7A and Figure 7B As shown, in some embodiments, the low-k dielectric layer 601 and the second etch stop layer 501 are subsequently etched using a first etch process to form via trenches (e.g., via trench 701, via trench 702, and / or via trench 703). In some instances, the first etch process etches through the low-k dielectric layer 601 and the second etch stop layer 501. The first etch process may terminate at the first etch stop layer 401. For example, the first etch process forms a first via trench 701 to expose a portion of the first etch stop layer 401 on the top surface of the first metal interconnect feature 210. In another instance, the first etch process forms a second via trench 702 to expose a portion of the first etch stop layer 401 on the top surface of the second metal interconnect feature 220. In yet another instance, the first etch process forms a third via trench 703 to expose a portion of the first etch stop layer 401 on the top surface of the third metal interconnect feature 230.

[0086] In some embodiments, the first etching process is any suitable etching process, such as plasma dry etching. In some embodiments, the first etching process uses CH-based etching. x F y CF x Plasma of Cl2 or BCl3.

[0087] In some embodiments, prior to performing the first etching process, a photomask for the first etching process is formed on top of the low-k dielectric layer 601 to transfer design patterns corresponding to multiple metal interconnect features (e.g., metal interconnect feature 210, metal interconnect feature 220, and / or metal interconnect feature 230) to the low-k dielectric layer 601. In some embodiments, the photomask is removed after performing the first etching process.

[0088] Return to reference Figure 1 In some embodiments, during operation S150, a bottom self-aligned via (BSAV) structure is formed by etching a first etch stop layer 401 and a cobalt layer 301 to expose metal interconnect features.

[0089] Figure 8A , Figure 8B and Figure 8C The diagram shows a cross-sectional view and a top view illustrating the process stages of forming bottom self-aligned vias (e.g., bottom self-aligned via 801, bottom self-aligned via 802 and / or bottom self-aligned via 803) in sequential operations according to some embodiments of the present disclosure. Figure 8C A top view showing a bottom self-aligned through-hole (e.g., bottom self-aligned through-hole 801, bottom self-aligned through-hole 802, and / or bottom self-aligned through-hole 803). Figure 8A Show along Figure 8C The cross-sectional view of the bottom self-aligned through-hole (e.g., bottom self-aligned through-hole 801, bottom self-aligned through-hole 802 and / or bottom self-aligned through-hole 803) cut by the plane YY' shown. Figure 8B Show along Figure 8C The cross-sectional view of the bottom self-aligned through-hole (e.g., bottom self-aligned through-hole 801, bottom self-aligned through-hole 802 and / or bottom self-aligned through-hole 803) cut by the XX' plane is shown.

[0090] In some embodiments, such as Figure 8A , Figure 8B and Figure 8C As shown, a second etching process is then used to etch the first etch stop layer 401 and the cobalt layer 301 to form bottom self-aligned vias (e.g., bottom self-aligned via 801, bottom self-aligned via 802, and / or bottom self-aligned via 803). In some instances, the second etching process etches downwards through the first etch stop layer 401 and the cobalt layer 301. The second etching process may terminate at multiple metal interconnect features (e.g., metal interconnect feature 210, metal interconnect feature 220, and / or metal interconnect feature 230). For example, the second etching process forms a first bottom self-aligned via 801 to expose the top surface of the first metal interconnect feature 210. In another instance, the second etching process forms a second bottom self-aligned via 802 to expose the top surface of the second metal interconnect feature 220. In yet another instance, the second etching process forms a third bottom self-aligned via 803 to expose the top surface of the third metal interconnect feature 230.

[0091] In some embodiments, the second etching process is a wet etching process, wherein a chemical solution is applied to the first etch stop layer 401 and the cobalt layer 301.

[0092] In some embodiments, the chemical solution comprises a hydrofluoric acid (HF)-based cleaning solution, a solvent-based cleaning solution, any combination thereof, and / or the like.

[0093] In some embodiments, the first etch stop layer 401 is an aluminum-based etch stop layer. In some embodiments, the etch selectivity of the cobalt layer 301 and the first etch stop layer 401 is adjusted by using an etch solution with a specific pH range. For example, the pH of the chemical solution is between about 5 and about 6.8. In some instances, the cobalt etch rate is increased to improve the etch selectivity of cobalt relative to the aluminum-based etch stop layer.

[0094] In some embodiments, such as Figure 8C As shown, the first bottom self-aligned through-hole 801 has an elliptical shape in the top view. In some embodiments, such as Figure 8C As shown, the second bottom self-aligned through-hole 802 has an elliptical shape in the top view. In some embodiments, such as Figure 8C As shown, the third bottom self-aligned through-hole 803 has an elliptical shape in the top view.

[0095] For illustrative purposes, such as Figure 8C As shown, top metal interconnect features (e.g., top metal interconnect feature 810 and / or top metal interconnect feature 820) extending in the y-direction are shown at the top of bottom self-aligned vias (e.g., bottom self-aligned via 801, bottom self-aligned via 802 and / or bottom self-aligned via 803). The area where the top metal interconnect features (e.g., top metal interconnect feature 810 and / or top metal interconnect feature 820) intersect with metal interconnect features (e.g., metal interconnect feature 210, metal interconnect feature 220 and / or metal interconnect feature 230) can limit the critical dimensions of the bottom self-aligned vias (e.g., bottom self-aligned via 801, bottom self-aligned via 802 and / or bottom self-aligned via 803) in both the x-direction and y-direction.

[0096] In some embodiments, such as Figure 8A As shown, along the critical leakage direction y, the first bottom self-aligned through-hole 801 has an enlarged critical dimension at its bottom. In some embodiments, such as Figure 8C As shown, along the non-critical leakage direction x, the first bottom self-aligned via 801 also has an enlarged critical size. In other words, the critical size of the bottom self-aligned via above the wider metal interconnect feature (e.g., metal interconnect feature 210 is wider than metal interconnect feature 220 in direction y) has an enlarged critical size in both the non-critical leakage direction x and the critical leakage direction y.

[0097] In some embodiments, such as Figure 8A and Figure 8C As shown, the second bottom self-aligned through-hole 802 has an enlarged critical dimension only at the bottom 805 of the bottom self-aligned through-hole 802 along the non-critical leakage direction x.

[0098] In some embodiments, such as Figure 8B As shown, along the non-critical leakage direction x, the third bottom self-aligned via 803 has an enlarged critical dimension at its bottom. In other words, the critical dimension of the bottom self-aligned via above the second metal interconnect feature 220 has an enlarged critical dimension only along the non-critical leakage direction x.

[0099] Alternatively, in some embodiments, the first bottom self-aligned through-hole 801 has a circular shape in the top view. In some embodiments, the second bottom self-aligned through-hole 802 has a circular shape in the top view. In some embodiments, the third bottom self-aligned through-hole 803 has a circular shape in the top view.

[0100] In some embodiments, such as Figure 8A As shown, the first bottom self-aligned through-hole 801 has an hourglass-shaped profile. For example, the first bottom self-aligned through-hole 801 has an enlarged bottom portion 804. In some embodiments, such as Figure 8B As shown, the third bottom self-aligned through-hole 803 has an hourglass-shaped profile. For example, the third bottom self-aligned through-hole 803 has an enlarged bottom portion 806.

[0101] like Figure 8A and Figure 8B As shown, an advantageous feature of the bottom self-aligned via with an enlarged bottom portion is that the enlarged bottom portion helps to reduce the contact resistance (R) of the bottom self-aligned via. c This improves the performance of semiconductor devices. For example... Figure 8A and Figure 8B As shown, another advantageous feature of bottom self-aligned vias with an enlarged bottom portion is that the enlarged bottom portion restricts the alignment of the bottom critical dimension (CD) of the bottom self-aligned via with the top critical dimension of the corresponding metal interconnect feature. This improves the tolerance for variations in the critical dimension of the bottom self-aligned via and the requirements for overlap control. Therefore, leakage margin can be increased, thereby expanding the process window for manufacturing semiconductor devices.

[0102] Figure 9A Examples of through holes along the y-direction are shown according to some embodiments of this disclosure.

[0103] like Figure 9AThe diagram illustrates a close-up view 901 of a first bottom self-aligned through-hole 801 and a close-up view 902 of a second bottom self-aligned through-hole 802. In some embodiments, as illustrated in close-up view 901, the first bottom self-aligned through-hole 801 has an hourglass-shaped profile 903. In other words, the first bottom self-aligned through-hole 801 has a critically enlarged dimension along the y-direction. In some embodiments, as illustrated in close-up view 902, the second bottom self-aligned through-hole 802 does not have a critically enlarged dimension along the y-direction.

[0104] Figure 9B Examples of bottom self-aligned through-holes along direction x are shown according to some embodiments of this disclosure.

[0105] like Figure 9B The diagram shows a close-up view 911 illustrating a third bottom self-aligned via 803. In some embodiments, as illustrated in close-up view 911, the third bottom self-aligned via 803 has an hourglass-shaped profile 913. In other words, the third bottom self-aligned via 803 has an enlarged critical dimension along the x-direction.

[0106] Figure 10 Examples of bottom self-aligned through-holes along the direction y are shown according to some embodiments of this disclosure.

[0107] like Figure 10 The diagram shows a close-up view 1001 illustrating a first bottom self-aligned through-hole 801. In some embodiments, as illustrated in close-up view 1001, the first bottom self-aligned through-hole 801 has an hourglass-shaped profile 903. For example, each sidewall 1002 of the hourglass-shaped profile 903 has a first sidewall portion 1002a and a second sidewall portion 1002b.

[0108] In some embodiments, the first sidewall portion 1002a and the second sidewall portion 1002b meet at the interface between the first etch stop layer 401 and the cobalt layer 301.

[0109] The first sidewall portion 1002a forms an angle A with the waist plane 1004 of the first metal interconnect feature 210. The second sidewall portion 1002b forms an angle B with the top surface 1003 of the first metal interconnect feature 210. In some embodiments, angle A is between about 95° and about 140°. In some embodiments, angle A is between about 100° and about 125°. In some embodiments, angle B is between about 30° and less than about 90°. In some embodiments, angle B is between about 45° and about 75°. At angles outside the disclosed range, there may not be sufficient current leakage protection or the contact resistance Rc may be too high.

[0110] like Figure 10As shown, the hourglass-shaped profile 903 has a waist plane 1004 where the first sidewall portion 1002a and the second sidewall portion 1002b meet. In some embodiments, the waist plane 1004 is located where the first etch stop layer 401 meets the cobalt layer 301. In some embodiments, the hourglass pattern is formed by the difference in etch selectivity between the first etch stop layer 401 and the cobalt layer 301, or by adjusting the parameters of the etch solution when etching the first etch stop layer 401 and the cobalt layer. In some embodiments, when etching the cobalt layer 301, an etch solution having a pH range between about 5 and about 6.8 is used. This etch solution provides higher Co selectivity for the etch stop layer.

[0111] The distance between the low-k dielectric layer 601, defined by thickness h1, and the waist plane 1004 and the top surface 1005 is controlled by the thickness of the low-k dielectric layer 601. In some embodiments, the thickness h1 ranges from about 16 nanometers to about 50 nanometers. The distance between the waist plane 1004 and the top surface 1003 of the first metal interconnect feature 210, defined by thickness h2, is controlled by the thickness of the cobalt layer 301. In some embodiments, the thickness h2 ranges from about 1 nanometer to about 6 nanometers.

[0112] In some embodiments, the ratio between thickness h1 and thickness h2 is between about 2.67 and about 50. For example, as the ratio between thickness h1 and thickness h2 decreases, the contact resistance (R) of the bottom self-aligned via 801 increases. c The value decreases. At ratios outside the disclosed range, there may not be sufficient current leakage protection or the contact resistance Rc may be too high.

[0113] The widths of the first bottom self-aligned via 801 and the bottom self-aligned via 803 decrease from the top surface of the low-k dielectric layer 601 to the minimum width at the waist plane 1004, and the width of the bottom portion of the bottom self-aligned via 801 and the bottom self-aligned via 803 increases from the waist plane 1004 through the cobalt layer 301 to the metal layer.

[0114] In some embodiments, such as Figure 10 As shown, the critical dimension d1 of the bottom self-aligned via 801 along the waist plane 1004 is smaller than the critical dimension d2 of the bottom self-aligned via 801 along the top surface 1003 of the first metal interconnect feature 210.

[0115] Figure 11A and Figure 11B Examples of bottom self-aligned through-holes according to some embodiments of this disclosure are shown.

[0116] like Figure 11A and Figure 11BAs shown, in some embodiments, due to lithography alignment variations, the bottom self-aligned via 1101 formed on top of the metal interconnect feature 1102 is shifted in the y-direction. For example, the bottom self-aligned via 1101 is shifted by several nanometers in the y-direction. However, the aluminum nitride layer (first etch stop layer 1104) has a stepped structure 1105 around the edge of the cobalt layer, and as a result, the bottom critical size of the bottom self-aligned via 1101 is limited by the stepped structure 1105. Figure 11B for Figure 11A The detailed view illustrates that the bottom critical dimension of the bottom self-aligned via 1101 tapers at the bottom of the bottom self-aligned via 1101. This reduces the risk of short circuits between the bottom self-aligned via 1101 and the adjacent metal interconnect feature 1103, and prevents leakage current between the metal interconnect feature 1102 and the adjacent metal interconnect feature 1103.

[0117] Figure 12A and Figure 12B Examples of bottom self-aligned through-holes according to some embodiments of this disclosure are shown.

[0118] like Figure 12A and Figure 12B As shown, in some embodiments, a bottom self-aligned via 1201 formed on top of the metal interconnect feature 1202 is aligned with the metal interconnect feature 1202. In some embodiments, after a first dry etching process, the bottom self-aligned via 1201 has a first profile 1203, such as... Figure 12B As shown. For example, the top critical dimension (CD) of profile 1203 is 14.6 nm, and the bottom critical dimension of profile 1203 is 11.4 nm. In some embodiments, the bottom self-aligned via 1201 has a second profile 1204 after the first dry etching process, thereby enlarging the top critical dimension. For example, the top critical dimension (CD) of the second profile 1204 is 17.7 nm, and the bottom critical dimension of the second profile 1204 is 12.2 nm. Figure 12B A comparison of the bottom dimensions between the first profile 1203 and the second profile 1204 shows that the top critical dimension of profile 1203 is amplified by 3.1 nanometers using the first dry etching process, while the bottom critical dimension of profile 1203 is amplified by 0.8 nanometers. Therefore, the bottom critical dimension is significantly less sensitive to variations in the first dry etching process compared to the top critical dimension. That is, the bottom self-aligned via helps reduce the sensitivity of the bottom critical dimension to the dry etching process used to amplify the top critical dimension. As a result, the bottom self-aligned via has improved tolerance to variations in critical dimensions and overlap. Therefore, leakage margin and process window are improved.

[0119] In some embodiments, the conductive metal layer ( Figure 8A , Figure 8B or Figure 8C (Not shown) are formed in bottom self-aligned vias (e.g., bottom self-aligned via 801, bottom self-aligned via 802, and / or bottom self-aligned via 803) to provide electrical connections between a plurality of metal interconnect features (e.g., metal interconnect features 210, 220, and / or 230) and other semiconductor devices subsequently formed on top of the bottom self-aligned vias (e.g., bottom self-aligned via 801, bottom self-aligned via 802, and / or bottom self-aligned via 803). Other semiconductor devices may include electrodes of capacitors, resistors, or portions of resistors, doped regions (such as source or drain), gate electrodes (such as the metal gate of a fin field-effect transistor), and / or silicide features disposed on the respective source, drain, or gate. The conductive metal layer may be made of a conductive material, including aluminum (Al), copper (Cu), tungsten (W), corresponding alloys, combinations thereof, and / or other suitable conductive materials.

[0120] The novel self-aligned via structure and manufacturing method disclosed in this disclosure provide an improved bottom self-aligned via structure and its formation method, thereby reducing contact resistance and preventing current leakage and short circuits compared to prior art and configurations. Some embodiments of this disclosure provide an improved bottom self-aligned via structure that increases tolerance to variations in the critical size of the bottom self-aligned via. Therefore, leakage margin can be increased, thereby expanding the process window for manufacturing semiconductor devices.

[0121] Some embodiments disclosed herein represent a method of manufacturing a semiconductor device. The method includes providing a semiconductor substrate layer, the semiconductor substrate layer including metal interconnect features embedded in the semiconductor substrate layer, and depositing a pad layer on the metal interconnect features. The method further includes depositing an etch stop layer on the pad layer and the semiconductor substrate layer, and forming a dielectric layer with via trenches on the etch stop layer to expose the etch stop layer. The method also includes etching the etch stop layer and the pad layer to form via structures to expose the metal interconnect features, wherein the via structures have an hourglass profile. In one embodiment, the metal interconnect features extend in a first direction, and the via structures have an enlarged bottom critical dimension along a second direction, wherein the first direction is perpendicular to the second direction. In one embodiment, the via structures have an enlarged bottom critical dimension along the first direction. In one embodiment, the etch stop layer is an aluminum-based etch stop layer. In one embodiment, the pad layer is a cobalt (Co) layer, and the thickness of the cobalt layer is between 0.5 nanometers and 3 nanometers. In one embodiment, the semiconductor substrate layer further includes a barrier layer and a substrate, wherein the barrier layer is formed between the metal interconnect features and the substrate. In one embodiment, the hourglass profile has a waist plane, the distance between the waist plane and the top surface of the dielectric layer is a first distance, the distance between the waist plane and the top surface of the metal interconnect feature is a second distance, and the ratio between the first distance and the second distance is between 2.67 and 50. In one embodiment, the first distance is between 16 nanometers and 50 nanometers, and the second distance is between 1 nanometer and 6 nanometers. In one embodiment, a wet etching process is used to etch the etch stop layer and the pad layer using a chemical solution with a pH value between 5 and 6.8. In one embodiment, the bottom critical size of the via structure is less sensitive to changes in the first dry etching process compared to the top critical size of the via structure. In one embodiment, the sidewall of the hourglass profile has a first sidewall portion above the waist plane and a second sidewall portion below the waist plane, wherein the first sidewall portion forms a first angle with the top surface of the metal interconnect feature and the second sidewall portion forms a second angle with the top surface of the metal interconnect feature 210, wherein the first angle is between 95° and 140° and the second angle is between 30° and 90°.

[0122] Another embodiment of this disclosure is a method of manufacturing a semiconductor device. The method includes providing a semiconductor substrate layer, the semiconductor substrate layer including metal interconnect features embedded in the semiconductor substrate layer, and depositing a pad layer on the metal interconnect features. The method further includes depositing an etch stop layer on the pad layer and the semiconductor substrate layer, wherein the etch stop layer has a stepped structure at the edge of the pad layer, and forming a dielectric layer with via trenches on the etch stop layer to expose the etch stop layer. The method also includes etching the etch stop layer and the pad layer to form via structures 801 / 802 / 803 to expose the metal interconnect features. In one embodiment, the via structures have an hourglass profile. In one embodiment, the hourglass profile has a waist plane, the distance between the waist plane and the top surface of the dielectric layer is a first distance, the distance between the waist plane and the top surface of the metal interconnect feature is a second distance, and the ratio between the first distance and the second distance is between 2.67 and 50. In one embodiment, the first distance is between 16 nanometers and 50 nanometers, and the second distance is between 1 nanometer and 6 nanometers. In one embodiment, the backing layer is a cobalt (Co) layer, and the etch stop layer and the cobalt layer for forming the via structure are etched using a wet etching process with a chemical solution having a pH value between 5 and 6.8. In one embodiment, the bottom critical dimension of the via structure is less sensitive to changes in the first dry etching process compared to the top critical dimension of the via structure.

[0123] Another embodiment of this disclosure is a semiconductor device including a semiconductor substrate layer and a pad layer. The semiconductor substrate layer includes metal interconnect features embedded therein, and the pad layer is located on the metal interconnect features. The semiconductor device further includes an etch stop layer and a dielectric layer. The etch stop layer is located on the pad layer and the semiconductor substrate layer, and the dielectric layer is located on the etch stop layer. The semiconductor device also includes a via structure that exposes the metal interconnect features through the dielectric layer, the etch stop layer, and the pad layer, wherein the via structure has an hourglass profile. In one embodiment, the hourglass profile has a waist plane, the distance between the waist plane and the top surface of the dielectric layer is a first distance, the distance between the waist plane and the top surface of the metal interconnect feature is a second distance, and the ratio between the first distance and the second distance is between 2.67 and 50. In one embodiment, the etch stop layer has a stepped structure at the edge of the pad layer.

[0124] Some embodiments disclosed herein represent a method of manufacturing a semiconductor device. The method includes providing a semiconductor substrate layer including a first metal interconnect feature and a second metal interconnect feature extending in a first direction and embedded therein. The first metal interconnect feature is wider than the second metal interconnect feature along a second direction, and the first direction is perpendicular to the second direction. A pad layer is deposited on the first and second metal interconnect features. The method further includes depositing an etch stop layer on the pad layer and the semiconductor substrate layer, and forming a dielectric layer with via trenches on the etch stop layer to expose the etch stop layer. The method also includes etching the etch stop layer and the pad layer to form via structures to expose the first and second metal interconnect features, wherein each of the via structures has an hourglass profile.

[0125] Another embodiment of this disclosure is a semiconductor device including a semiconductor substrate layer and a pad layer. The semiconductor substrate layer includes metal interconnect features embedded in the semiconductor substrate layer, and the pad layer is located on the metal interconnect features. The semiconductor device further includes an etch stop layer and a dielectric layer. The etch stop layer is located on the pad layer and the semiconductor substrate layer, and the dielectric layer is located on the etch stop layer. The semiconductor device also includes a via structure that exposes the metal interconnect features through the dielectric layer, the etch stop layer, and the pad layer, wherein the via structure has an hourglass profile. The metal interconnect features extend in a first direction, and the via structure has an enlarged bottom critical dimension along a second direction, and the first direction is perpendicular to the second direction. In some embodiments, the via structure has an enlarged bottom critical dimension along the first direction. In some embodiments, the thickness of the pad layer is between 0.5 nanometers and 3 nanometers. In some embodiments, the semiconductor substrate layer further includes a barrier layer and a substrate, wherein the barrier layer is located between the metal interconnect features and the substrate. In some embodiments, the hourglass profile has a waist plane, the distance between the waist plane and the top surface of the dielectric layer is a first distance, the distance between the waist plane and the top surface of the metal interconnect feature is a second distance, and the ratio between the first distance and the second distance is between 2.67 and 50. In one embodiment, the first distance is between 16 nanometers and 50 nanometers, and the second distance is between 1 nanometer and 6 nanometers. In one embodiment, the sidewalls of the hourglass profile have a first sidewall portion above the waist plane and a second sidewall portion below the waist plane. The first sidewall portion has a first angle with the top surface of the metal interconnect feature, and the second sidewall portion has a second angle with the top surface of the metal interconnect feature, wherein the first angle is between 95° and 140°, and the second angle is between 30° and 90°.

[0126] Another embodiment of this disclosure is a semiconductor device including a semiconductor substrate layer and a pad layer. The semiconductor substrate layer includes metal interconnect features embedded therein, and the pad layer is located on the metal interconnect features. The semiconductor device further includes an etch stop layer and a dielectric layer. The etch stop layer is located on the pad layer and the semiconductor substrate layer, wherein the etch stop layer has a stepped structure at the edge of the pad layer. The dielectric layer is located on the etch stop layer. The semiconductor device also includes a via structure that exposes the metal interconnect features through the dielectric layer, the etch stop layer, and the pad layer, wherein the via structure has an hourglass-shaped profile.

[0127] The foregoing outlines the features of several embodiments or examples to enable those skilled in the art to better understand the nature of some embodiments disclosed herein. Those skilled in the art should understand that some embodiments of this disclosure can be readily used as the basis for designing or modifying other processes and structures to achieve the same purpose and / or attain the same advantages as the embodiments or examples introduced in some embodiments of this disclosure. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of some embodiments of this disclosure, and that various changes, substitutions, and modifications can be made by those skilled in the art without departing from the spirit and scope of some embodiments of this disclosure.

Claims

1. A semiconductor device, characterized in that, Include: A semiconductor substrate layer, including a metal interconnect feature embedded in the semiconductor substrate layer; A pad layer is located on the metal interconnect feature; An etch stop layer is located on the pad layer and the semiconductor substrate layer; A dielectric layer is located on the etch stop layer; and A via structure that exposes the metal interconnect feature through the dielectric layer, the etch stop layer and the pad layer, wherein the via structure has an hourglass profile, wherein the metal interconnect feature extends in a first direction, the via structure has an enlarged bottom critical dimension along a second direction, and the first direction is perpendicular to the second direction.

2. The semiconductor device as claimed in claim 1, characterized in that, in: The through-hole structure has an enlarged bottom critical dimension along the first direction.

3. The semiconductor device as claimed in claim 1, characterized in that, in: The thickness of the liner layer ranges from 0.5 nanometers to 3 nanometers.

4. The semiconductor device as claimed in claim 1, characterized in that, in: The semiconductor substrate layer further includes a barrier layer and a substrate, wherein the barrier layer is located between the metal interconnect feature and the substrate.

5. The semiconductor device as claimed in claim 1, characterized in that, in: The hourglass shape has a waist plane. The distance between the waist plane and a top surface of the dielectric layer is a first distance. The distance between the waist plane and the top surface of the metal interconnect feature is a second distance, and The ratio between the first distance and the second distance is between 2.67 and 50.

6. The semiconductor device as claimed in claim 5, characterized in that, in: The first distance is between 16 nanometers and 50 nanometers, and The second distance is in the range of 1 nanometer to 6 nanometers.

7. The semiconductor device as claimed in claim 5, characterized in that, in: The hourglass-shaped profile has a first sidewall portion above the waist plane and a second sidewall portion below the waist plane, and The first sidewall portion has a first angle with the top surface of the metal interconnect feature, and the second sidewall portion has a second angle with the top surface of the metal interconnect feature, wherein the first angle is between 95° and 140°, and the second angle is between 30° and 90°.

8. A semiconductor device, characterized in that, Include: A semiconductor substrate layer, including a metal interconnect feature embedded in the semiconductor substrate layer; A pad layer is located on the metal interconnect feature; An etch stop layer is located on the pad layer and the semiconductor substrate layer, wherein the etch stop layer has a stepped structure at an edge of the pad layer; A dielectric layer is located on the etch stop layer; and A via structure that exposes the metal interconnect features through the dielectric layer, the etch stop layer and the pad layer, wherein the via structure has an hourglass-shaped profile.

9. A semiconductor device, characterized in that, Include: A semiconductor substrate layer, including a metal interconnect feature embedded in the semiconductor substrate layer; A pad layer is located on the metal interconnect feature; An etch stop layer is located on the pad layer and the semiconductor substrate layer; A dielectric layer is located on the etch stop layer; and A via structure that exposes the metal interconnect features through the dielectric layer, the etch stop layer and the pad layer, wherein the via structure has an hourglass-shaped profile.

10. The semiconductor device as claimed in claim 9, characterized in that, in: The hourglass shape has a waist plane. The distance between the waist plane and a top surface of the dielectric layer is a first distance. The distance between the waist plane and the top surface of the metal interconnect feature is a second distance, and The ratio between the first distance and the second distance is between 2.67 and 50.

Images