Heat dissipation cover and chip packaging structure

Abstract

The utility model relates to a heat dissipation cover and a chip packaging structure. The heat dissipation cover comprises an upper heat dissipation cover which comprises an upper surface and a lower surface which are oppositely distributed; the lower supporting frame is vertically connected to the end portion of the upper heat dissipation cover, the upper heat dissipation cover and the lower supporting frame define a vacuum shell inner cavity, the side face of the lower supporting frame is provided with a liquid injection opening communicated with the vacuum shell inner cavity, and the vacuum shell inner cavity is used for containing a chip; the liquid injection port is used for injecting cooling liquid into the inner cavity of the vacuum shell; and the vacuum capillary heat dissipation pipe is located on the upper surface of the upper heat dissipation cover, the vacuum capillary heat dissipation pipe extends in the direction perpendicular to the upper surface of the upper heat dissipation cover, and the vacuum capillary heat dissipation pipe is communicated with an inner cavity of the vacuum shell. According to the utility model, the heat dissipation performance is improved and the heat accumulation in the chip is reduced by combining the phase change of the cooling liquid with the heat dissipation mode of the micro-channel in the chip.

Description

Technical Field

[0001] This utility model relates to the field of integrated circuit manufacturing technology, and in particular to a heat sink and chip packaging structure. Background Technology

[0002] As the integration density and frequency of packaging structures continue to increase, heat dissipation becomes increasingly important. Heat accumulation within the packaging structure can cause excessively high temperatures in the functional chips, devices, and other electronic components, affecting their performance and potentially shortening the lifespan of the packaging structure. In semiconductor packaging structures, a heat sink is used to cover the chip's surface away from the substrate, and this heat sink is bonded to the chip using a thermal interface material (TIM). Current packaging structures primarily employ two heat dissipation paths: one is along the chip-thermal interface material-heat sink path, dissipating heat upwards into the air; the other is along the chip-conductive bump-substrate-PCB circuit board path, dissipating heat downwards into the air.

[0003] The main method to improve the heat dissipation performance of the packaging structure is to reduce thermal resistance. Methods to reduce thermal resistance primarily include increasing the thermal conductivity of the material, shortening the heat conduction path, and increasing the heat dissipation area. A heat sink is placed over the chip, so that the heat sink and the substrate together form a closed space to accommodate the chip. In this case, the heat dissipation area is mainly the area of ​​the active surface of the chip. Considering wafer manufacturing costs, increasing the chip area is generally not used to reduce thermal resistance. Simultaneously, because the stability of the thermal interface material gradually decreases under thermal cycling (the higher the thermal conductivity of the thermal interface material, the worse the stability), and the thickness of the thermal interface material cannot be made very thin in actual operation, the thermal resistance of the thermal interface material is relatively high. With the development of chip stacking technology, the increased heat conduction path within the chip also leads to increased thermal resistance, causing heat to accumulate inside the chip.

[0004] Therefore, improving the heat dissipation performance of the packaging structure and reducing the accumulation of heat inside the chip, thereby improving the performance of the packaging structure, is a technical problem that urgently needs to be solved. Summary of the Invention

[0005] This invention provides a heat dissipation cover and a chip packaging structure to improve the heat dissipation performance of the packaging structure, reduce the accumulation of heat inside the chip, and thus improve the performance of the packaging structure.

[0006] According to some embodiments, the present invention provides a heat dissipation cover, comprising:

[0007] The upper heat dissipation cover includes an upper surface and a lower surface that are relatively distributed.

[0008] The lower support frame is vertically connected to the lower surface end of the upper heat sink cover, and the upper heat sink cover and the lower support frame together form a vacuum housing cavity. The side of the lower support frame has a liquid injection port that communicates with the vacuum housing cavity. The vacuum housing cavity is used to accommodate the chip, and the liquid injection port is used to inject coolant into the vacuum housing cavity.

[0009] A vacuum capillary heat dissipation tube is located on the upper surface of the upper heat dissipation cover. The vacuum capillary heat dissipation tube extends in a direction perpendicular to the upper surface of the upper heat dissipation cover and communicates with the inner cavity of the vacuum housing.

[0010] In some embodiments, the upper heat dissipation cover has a vacuum capillary structure layer, one end of which is connected to the vacuum capillary heat dissipation tube and the other end is connected to the inner cavity of the vacuum housing.

[0011] In some embodiments, it also includes:

[0012] A flow channel partition, located in the inner cavity of the vacuum housing and used for mounting on the chip, the flow channel partition includes a plate body and a flow channel opening penetrating the plate body, the flow channel opening includes an upper end facing the upper heat sink and a lower end opposite to the upper end, and the width of the upper end of the flow channel opening is greater than the width of the lower end of the flow channel opening.

[0013] In some embodiments, the plate is funnel-shaped, and the width of the surface of the plate facing the upper heat dissipation cover is greater than the width of the surface of the plate away from the upper heat dissipation cover.

[0014] In some embodiments, it also includes:

[0015] Heat dissipation fins are connected to the upper surface of the upper heat dissipation cover, and the heat dissipation fins are distributed around the outer periphery of the plurality of vacuum capillary heat dissipation tubes.

[0016] In some embodiments, a plurality of the vacuum capillary heat dissipation tubes are arranged in a staggered pattern on the upper surface of the upper heat dissipation cover.

[0017] According to other embodiments, the present invention also provides a chip packaging structure, comprising:

[0018] The chip includes a front and a back side that are relatively distributed.

[0019] A heat sink includes an upper heat sink, a lower support frame, and a vacuum capillary heat sink. The upper heat sink includes an upper surface and a lower surface that are distributed opposite to each other. The lower support frame is vertically connected to the end of the upper heat sink, and the upper heat sink and the lower support frame together form a vacuum housing cavity. The side of the lower support frame has a liquid injection port that communicates with the vacuum housing cavity. The chip is located in the vacuum housing cavity, and the liquid injection port is used to inject coolant into the vacuum housing cavity. The vacuum capillary heat sink is located on the upper surface of the upper heat sink and extends in a direction perpendicular to the top surface of the upper heat sink, and the vacuum capillary heat sink communicates with the vacuum housing cavity.

[0020] In some embodiments, the upper heat dissipation cover has a vacuum capillary structure layer, one end of which is connected to the vacuum capillary heat dissipation tube and the other end is connected to the inner cavity of the vacuum housing.

[0021] In some embodiments, the chip has a microchannel that extends through the chip and communicates with the inner cavity of the housing.

[0022] In some embodiments, the heat sink further includes:

[0023] A flow channel partition is located in the inner cavity of the vacuum housing and is attached to the back side of the chip. The flow channel partition includes a plate body and a flow channel opening that penetrates the plate body. The flow channel opening exposes the back side of the chip. The flow channel opening includes an upper end facing the upper heat sink and a lower end opposite to the upper end. The width of the upper end of the flow channel opening is greater than the width of the lower end of the flow channel opening.

[0024] In some embodiments, the plate is funnel-shaped, and the width of the surface of the plate facing the upper heat dissipation cover is greater than the width of the surface of the plate away from the upper heat dissipation cover, and there is a gap between the plate and the upper heat dissipation cover.

[0025] In some embodiments, the microchannel includes:

[0026] A current collector is located on the back side of the chip;

[0027] A heat dissipation channel is located inside the chip and communicates with the inner cavity of the vacuum housing. The heat dissipation channel penetrates the chip in a direction parallel to the back of the chip and communicates with the current collection hole.

[0028] In some embodiments, a plurality of the current collection holes are arranged in a two-dimensional array on the back side of the chip along a first direction and a second direction, both the first direction and the second direction being parallel to the back side of the chip, and the first direction intersecting the second direction;

[0029] A portion of the heat dissipation channels extend along the first direction and are spaced apart along the second direction, while another portion of the heat dissipation channels extend along the second direction and are spaced apart along the first direction, and each heat dissipation channel communicates with a plurality of flow collection holes arranged along its extension direction.

[0030] In some embodiments, the flow collecting hole is funnel-shaped, and the width of the end of the flow collecting hole facing the flow channel partition is greater than the width of the end of the flow collecting hole away from the flow channel partition.

[0031] In some embodiments, the front side of the chip includes a functional area and an edge area located outside the functional area, the edge area having trenches distributed around the periphery of the functional area; the chip packaging structure further includes:

[0032] A solder layer continuously covers the side surface of the chip, a portion of the edge region of the chip, and at least a portion of the inner wall of the trench.

[0033] In some embodiments, it also includes:

[0034] A packaging substrate, wherein the front side of the chip is disposed facing the top surface of the packaging substrate;

[0035] A packaging base is located on the top surface of the packaging substrate. The packaging base includes a base housing and a device receiving cavity penetrating the base housing. The chip is located in the device receiving cavity and is electrically connected to the packaging substrate.

[0036] In some embodiments, the packaging base further includes:

[0037] An extension is perpendicularly connected to the sidewall of the device receiving cavity, the edge region of the chip is located on the extension, and the heat dissipation layer is connected to the sidewall of the device receiving cavity;

[0038] Positioning posts are connected to the base housing and are distributed around the outer periphery of the device receiving cavity.

[0039] The heat dissipation cap and chip packaging structure provided by this utility model, by setting an upper heat dissipation cap, a lower support frame and a vacuum capillary heat dissipation tube located on the upper heat dissipation cap, the upper heat dissipation cap and the lower support frame together form a vacuum shell cavity, and the vacuum capillary heat dissipation tube communicates with the vacuum shell cavity. The side of the lower support frame has a liquid injection port, so that coolant can be injected through the liquid injection port. The coolant enters the vacuum shell cavity and can absorb the heat generated by the chip located in the vacuum shell cavity. Since the vacuum shell cavity and the vacuum capillary heat dissipation tube are both vacuum environments, the coolant is easily vaporized in the vacuum shell cavity after being heated and rises along the vacuum capillary heat dissipation tube. After reaching the top of the vacuum capillary heat dissipation tube, it re-liquefies due to the temperature difference and heat exchange with the external environment. The coolant is then collected into the microchannels inside the chip through multiple current collection components, thereby realizing the cyclic heat dissipation of the chip through coolant. This invention utilizes a combination of coolant phase change and microfluidic channels within the chip for heat dissipation. Both its thermal conductivity and transient response efficiency are tens to hundreds of times higher than those of heat dissipation materials such as pure copper, thereby improving heat dissipation performance, reducing heat accumulation within the chip, and enhancing the performance of the packaging structure. The heat sink provided by this invention is entirely a mechanical structure with no electrical components, thus improving the reliability of its heat dissipation function.

[0040] In some embodiments of this invention, microchannels are provided inside the chip and communicate with the inner cavity of the vacuum shell within the heat sink. This allows the coolant to flow directly through the chip's interior along the microchannels, further increasing the chip's heat dissipation area and bringing the coolant closer to the heat source surface, resulting in lower thermal resistance and improved heat dissipation. Furthermore, the liquid phase change cooling method utilizing coolant circulation almost negligibles contact thermal resistance issues, leading to even superior heat dissipation performance. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in the embodiments of this utility model, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0042] Figure 1 This is a schematic diagram of the structure of the heat dissipation cover in a specific embodiment of this utility model;

[0043] Figure 2 This is a schematic diagram of the support frame and capillary heat dissipation tubes in a specific embodiment of this utility model when no coolant is injected;

[0044] Figure 3 This is a schematic diagram of the structure of the support frame and capillary heat dissipation tube when injecting coolant in a specific embodiment of this utility model;

[0045] Figure 4 This is a schematic diagram of the arrangement of capillary heat dissipation tubes in a specific embodiment of this utility model;

[0046] Figure 5 This is a schematic diagram of the flow channel baffle in a specific embodiment of this utility model;

[0047] Figure 6 This is a partial top view of the flow channel baffle in a specific embodiment of this utility model;

[0048] Figure 7 This is a schematic diagram of the chip packaging structure in a specific embodiment of this utility model;

[0049] Figure 8 This is a cross-sectional schematic diagram of the chip in a specific embodiment of this utility model;

[0050] Figure 9 This is a schematic diagram of the back side of the chip in a specific embodiment of this utility model;

[0051] Figure 10 This is a schematic diagram of the front structure of the chip in a specific embodiment of this utility model;

[0052] Figure 11 This is a top view of the packaging base in a specific embodiment of this utility model;

[0053] Figure 12 This is a bottom view of the packaging base in a specific embodiment of this utility model;

[0054] Figure 13 This is a partial schematic diagram of the chip, packaging base, and substrate in a specific embodiment of this utility model. Detailed Implementation

[0055] The specific embodiments of the heat sink and chip packaging structure provided by this utility model will be described in detail below with reference to the accompanying drawings.

[0056] This specific embodiment provides a heat dissipation cover. Figure 1 This is a schematic diagram of the heat dissipation cover in a specific embodiment of this utility model. Figure 2 This is a schematic diagram of the support frame and capillary heat dissipation tubes in a specific embodiment of this utility model when no coolant is injected. Figure 3 This is a schematic diagram of the supporting frame and capillary heat dissipation tubes during the injection of coolant in a specific embodiment of this utility model. (See diagram for example.) Figure 1 , Figure 2 and Figure 3As shown, the heat dissipation cover includes:

[0057] The upper heat dissipation cover 10 includes an upper surface and a lower surface 102 that are distributed opposite to each other;

[0058] The lower support frame 11 is vertically connected to the lower surface end of the upper heat dissipation cover 10, and the upper heat dissipation cover 10 and the lower support frame together form a vacuum housing cavity 15. The side of the lower support frame 11 has a liquid injection port that communicates with the vacuum housing cavity 15. The vacuum housing cavity 15 is used to accommodate the chip, and the liquid injection port is used to inject coolant into the vacuum housing cavity 15.

[0059] A vacuum capillary heat dissipation tube 12 is located on the upper surface of the upper heat dissipation cover 10. The vacuum capillary heat dissipation tube 12 extends in a direction perpendicular to the upper surface of the upper heat dissipation cover 10, and the vacuum capillary heat dissipation tube 12 communicates with the inner cavity 15 of the vacuum housing.

[0060] Specifically, such as Figure 1 , Figure 2 and Figure 3As shown, the upper heat sink 10 has a plate-like structure, and the lower support frame 11 is perpendicularly connected to the edge of the lower surface 102 of the upper heat sink 10 along the Z-axis direction. This allows the lower support frame 11 and the upper heat sink 10 to together enclose a vacuum housing cavity 15 for accommodating the chip and the coolant, facilitating the fixing of the heat sink to the packaging substrate during the packaging process. The Z-axis direction intersects perpendicularly with the upper surface of the upper heat sink 10. The coolant is injected into the vacuum housing cavity 15 through the injection port. After the coolant filling is completed, the injection port is closed, so that both the vacuum housing cavity 15 and the vacuum capillary heat sink 12 are in a vacuum state. When the heat sink is placed on the chip, the heat generated by the chip causes the coolant in the vacuum housing cavity 15 to vaporize in the vacuum environment, forming a gas or a gas-liquid mixture. The gas or gas-liquid mixture rises into the vacuum capillary heat sink 12 and is transported upwards along the vacuum capillary heat sink 12. As the gas or gas-liquid mixture is transported upwards along the vacuum capillary heat sink 12, or after reaching the top of the vacuum capillary heat sink 12, due to the temperature difference between the inside and outside of the vacuum capillary heat sink 12, the gas or gas-liquid mixture in the vacuum environment exchanges heat with the cooler surrounding air and re-liquefies. Under the action of gravity and the pressure difference caused by the temperature difference, it flows back along the vacuum capillary heat sink 12 into the inner cavity 15 of the vacuum housing, thereby realizing the circulating heat dissipation of the chip through the coolant. This specific embodiment achieves chip heat dissipation through the phase change of the coolant. Both its thermal conductivity and transient response efficiency are tens or even hundreds of times higher than those of heat dissipation materials such as pure copper, thereby improving the heat dissipation performance of the heat sink cover and reducing the accumulation of heat inside the chip. Moreover, the coolant circulates within the heat sink cover, realizing the recycling of the coolant, which helps to reduce the heat dissipation cost of the chip.

[0061] In one example, the upper heat dissipation cover 10 and the lower support frame 11 may be made of thermally conductive materials such as copper to further improve the heat dissipation performance of the heat dissipation cover.

[0062] In some embodiments, the upper heat dissipation cover 10 has a vacuum capillary structure layer 14, one end of which is connected to the vacuum capillary heat dissipation tube 12 and the other end is connected to the inner cavity 15 of the vacuum housing.

[0063] Specifically, the vacuum capillary heat dissipation tube 12 is connected to the inner cavity 15 of the vacuum housing through the vacuum capillary structure layer 14, so that the coolant in the inner cavity 15 of the vacuum housing, after absorbing the heat generated by the chip and vaporizing to form a gas or gas-liquid mixture, can enter the vacuum capillary heat dissipation tube 12 through the vacuum capillary structure layer 14. After the gas or gas-liquid mixture undergoes heat exchange with the cooler air and re-liquefies, it flows back to the inner cavity 15 of the vacuum housing along the vacuum capillary heat dissipation tube 12 under the action of gravity and the pressure difference caused by the temperature difference.

[0064] In one example, the vacuum capillary structure layer 14 includes multiple interconnected vacuum capillary channels, for example, multiple interconnected vacuum capillary channels forming a mesh structure, and the bottom of each vacuum capillary heat dissipation tube 12 is connected to at least one vacuum capillary channel. In this specific embodiment, "multiple" refers to two or more channels.

[0065] Figure 5 This is a schematic diagram of the flow channel baffle in a specific embodiment of this utility model. Figure 6 This is a partial top view of the flow channel baffle in a specific embodiment of this utility model. Figure 6 yes Figure 5 A partial top view of the area within the dashed box. In some embodiments, such as... Figure 1 , Figure 5 and Figure 6 As shown, the heat dissipation cover also includes:

[0066] A flow channel partition 16 is located in the inner cavity 15 of the vacuum housing and is used to mount the chip. The flow channel partition 16 includes a plate body 61 and a flow channel opening 60 penetrating the plate body 61. The flow channel opening 60 includes an upper end facing the upper heat sink 10 and a lower end opposite to the upper end. The width of the upper end of the flow channel opening 60 is greater than the width of the lower end of the flow channel opening.

[0067] In some embodiments, the plate 61 is funnel-shaped, and the width of the surface of the plate 61 facing the top cover 10 is greater than the width of the surface of the plate 61 away from the top cover 10.

[0068] Specifically, the plate 61 in the flow channel baffle 16 is disposed below the upper heat dissipation cover 10 and has a gap with the upper heat dissipation cover 10, and the flow channel opening 60 is used to expose the chip. After the coolant in the vacuum housing cavity 15 absorbs the heat generated by the chip and vaporizes to form the gas or the gas-liquid mixture, it can be transported upward to the vacuum capillary heat dissipation tube 12. During the upward transport along the vacuum capillary heat dissipation tube 12 or after reaching the top of the vacuum capillary heat dissipation tube 12, the gas or the gas-liquid mixture re-liquefies to form the coolant. The flow channel baffle 16 can collect the re-liquefied coolant through the flow channel opening 60 and converge the coolant onto the chip. That is, the flow channel baffle 16 can collect the re-liquefied coolant formed in the vacuum capillary heat dissipation tube 12, so that the re-liquefied coolant can fully contact the chip to achieve efficient heat dissipation through circulation. By setting the plate 61 in a funnel shape, and making the width of the surface of the plate 61 facing the upper heat dissipation cover 10 (i.e., the first surface 161 of the plate 61) greater than the width of the surface of the plate 61 away from the upper heat dissipation cover 10 (i.e., the second surface 162 of the plate 61), it helps to increase the space in the inner cavity 15 of the vacuum housing for accommodating the coolant, thereby further increasing the heat dissipation effect of the heat dissipation cover.

[0069] In some embodiments, the heat sink further includes:

[0070] Heat dissipation fins are connected to the upper surface of the upper heat dissipation cover 10, and the heat dissipation fins are distributed around the outer periphery of the plurality of vacuum capillary heat dissipation tubes 12.

[0071] Specifically, by integrating the heat dissipation fins on the upper surface of the upper heat dissipation cover 10, the heat dissipation area of ​​the heat dissipation cover is further increased. The heat dissipation effect of the heat dissipation cover can be further enhanced by combining the heat dissipation through the air duct of the heat dissipation fins with the phase change liquid cooling of the vacuum capillary heat dissipation tube 12.

[0072] Figure 4 This is a schematic diagram of the arrangement of capillary heat dissipation tubes in a specific embodiment of the present invention. In some embodiments, a plurality of the vacuum capillary heat dissipation tubes 12 are arranged in a staggered pattern on the upper surface of the upper heat dissipation cover 10, such as... Figure 4 As shown.

[0073] Specifically, the multiple vacuum capillary heat dissipation tubes 12 are arranged in a differential pattern on the upper surface of the upper heat dissipation cover 10. For example, the multiple vacuum capillary heat dissipation tubes 12 are arranged at intervals along the X-axis and Y-axis directions on the upper surface of the upper heat dissipation cover 10, and adjacent rows of vacuum capillary heat dissipation tubes 12 along the Y-axis direction are staggered, thereby enhancing the turbulence effect between the multiple vacuum capillary heat dissipation tubes 12, and further improving the heat dissipation performance of the vacuum capillary heat dissipation tubes 12. In this specific embodiment, "multiple" refers to two or more. The X-axis direction and the Y-axis direction are both parallel to the upper surface of the upper heat dissipation cover 10, and the X-axis direction intersects the Y-axis direction perpendicularly.

[0074] This specific embodiment also provides a chip packaging structure. Figure 7 This is a schematic diagram of the chip packaging structure in a specific embodiment of this utility model. A schematic diagram of the heat sink in the chip packaging structure can be found in [reference needed]. Figures 1-6 .like Figures 1-7 As shown, the chip packaging structure includes:

[0075] Chip 70, including a front and a back side that are relatively distributed;

[0076] The heat sink includes an upper heat sink 10, a lower support frame 11, and a vacuum capillary heat sink 12. The upper heat sink 10 includes an upper surface and a lower surface 102 that are distributed opposite to each other. The lower support frame 11 is vertically connected to the end of the upper heat sink 10, and the upper heat sink 10 and the lower support frame 11 together form a vacuum housing cavity 15. The side of the lower support frame 11 has a liquid injection port that communicates with the vacuum housing cavity 15. The chip 70 is located in the vacuum housing cavity 15. The liquid injection port is used to inject coolant into the vacuum housing cavity 15. The vacuum capillary heat sink 12 is located on the upper surface of the upper heat sink 10. The vacuum capillary heat sink 12 extends in a direction perpendicular to the top surface of the upper heat sink 10, and the vacuum capillary heat sink 12 communicates with the vacuum housing cavity 15.

[0077] This specific embodiment is illustrated using an example where the chip packaging structure includes only one chip 70. In other embodiments, the chip packaging structure may include multiple chips arranged in a flat arrangement or multiple chips stacked together, with the upper heat sink 10 covering the multiple chips arranged in a flat arrangement or covering the surface of the uppermost chip in a multi-layer stacked chip structure.

[0078] In some embodiments, the upper heat dissipation cover 10 has a vacuum capillary structure layer 14, one end of which is connected to the vacuum capillary heat dissipation tube 12 and the other end is connected to the inner cavity 15 of the vacuum housing.

[0079] In some embodiments, the chip 70 has a microchannel penetrating the chip 70, and the microchannel is in communication with the inner cavity 15 of the vacuum housing.

[0080] Specifically, by providing a microchannel penetrating the chip 70, the coolant can enter the microchannel from the inner cavity 15 of the vacuum housing. This not only further increases the heat dissipation area of ​​the chip 70, allowing the chip 70 to dissipate heat from its front, back, sides, and the inner wall of the microchannel as a whole, but also further shortens the distance between the coolant and the chip 70, thereby further improving the heat dissipation effect of the chip 70.

[0081] In some embodiments, such as Figure 5 , Figure 6 and Figure 7 As shown, the heat dissipation cover also includes:

[0082] A flow channel partition 16 is located in the inner cavity 15 of the vacuum housing and is attached to the back side of the chip 70. The flow channel partition 16 includes a plate body 61 and a flow channel opening 60 penetrating the plate body 61. The flow channel opening 60 exposes the back side of the chip 70. The flow channel opening 60 includes an upper end facing the upper heat sink 10 and a lower end opposite to the upper end. The width of the upper end of the flow channel opening 60 is greater than the width of the lower end of the flow channel opening 60.

[0083] In some embodiments, the plate 61 is funnel-shaped, and the width of the surface of the plate 61 facing the upper heat dissipation cover 10 is greater than the width of the surface of the plate 61 away from the upper heat dissipation cover 10, and there is a gap between the plate 61 and the upper heat dissipation cover 10.

[0084] Specifically, along the Z-axis, the flow channel partition 16 is disposed between the chip 70 and the upper heat sink 10, and there is a gap between the flow channel partition 16 and the upper heat sink 10, meaning that the flow channel partition 16 and the upper heat sink 10 do not contact each other. After the coolant in the vacuum housing cavity 15 absorbs the heat generated by the chip 70 and vaporizes to form the gas or the gas-liquid mixture, it can be transported upwards to the vacuum capillary heat sink 12. During the upward transport along the vacuum capillary heat sink 12 or after reaching the top of the vacuum capillary heat sink 12, the gas or the gas-liquid mixture re-liquefies to form the coolant. The flow channel baffle 16 can collect the reliquefied coolant through the flow channel opening 60, and concentrate the coolant on the back side of the chip 70 and in the microchannels within the chip 70. In other words, the flow channel baffle 16 can collect the reliquefied coolant formed within the vacuum capillary heat sink 12, allowing the reliquefied coolant to fully contact the chip 70 for efficient heat dissipation. By setting the plate 61 in a funnel shape, and ensuring that the width of the surface of the plate 61 facing the upper heat sink 10 is greater than the width of the surface of the plate 61 away from the upper heat sink 10, the space within the vacuum housing cavity 15 for accommodating the coolant is increased, thereby further enhancing the heat dissipation effect of the heat sink.

[0085] In one example, the coolant filling the vacuum housing cavity 15 is at a level not lower than (i.e., higher than or flush with) the back of the chip 70 to prevent dry burning.

[0086] Figure 8 This is a cross-sectional schematic diagram of the chip in a specific embodiment of this utility model. Figure 9 This is a schematic diagram of the back side of the chip in a specific embodiment of this utility model. Figure 10 This is a schematic diagram of the front structure of the chip in a specific embodiment of this utility model. In some embodiments, such as... Figure 8 , Figure 9 and Figure 10 As shown, the microchannel includes:

[0087] A current collector 82 is located on the back side of the chip 70;

[0088] A heat dissipation channel 81 is located inside the chip 70 and communicates with the inner cavity 15 of the vacuum housing. The heat dissipation channel 81 penetrates the chip 70 in a direction parallel to the back surface of the chip 70, and the heat dissipation channel 81 communicates with the current collection hole 82.

[0089] In some embodiments, a plurality of the current collection holes 82 are arranged in a two-dimensional array on the back surface of the chip 70 along a first direction and a second direction, both the first direction and the second direction being parallel to the back surface of the chip 70, and the first direction intersecting the second direction;

[0090] A portion of the heat dissipation channels 81 extend along the first direction and are spaced apart along the second direction, while another portion of the heat dissipation channels 81 extend along the second direction and are spaced apart along the first direction, and each heat dissipation channel 81 communicates with a plurality of flow collection holes 82 arranged along its extension direction.

[0091] The following description uses the X-axis as the first direction and the Y-axis as the second direction as an example. The microchannel includes multiple flow-collecting holes 82 extending from the back of the chip 70 along the Z-axis into the interior of the chip 70. The flow-collecting holes 82 do not penetrate the chip 70 along the Z-axis to avoid contaminating the device structure on the front side of the chip 70 with coolant. Multiple heat dissipation channels 81 are arranged in a grid pattern inside the chip 70 along the X-axis and Y-axis, and are interconnected. The heat dissipation channels 81 are straight channels. Multiple flow-collecting holes 82 are arranged in a two-dimensional array along the X-axis and Y-axis. A portion of the heat dissipation channels 81 extend along the X-axis and are spaced apart along the Y-axis, while another portion extends along the Y-axis and is spaced apart along the X-axis. Each heat dissipation channel 81 communicates with multiple flow-collecting holes 82 arranged along its extension direction. Along the Z-axis, the bottom surface of the flow collector 82 is lower than the heat dissipation channel 81, meaning that the heat dissipation channel 81 is connected to the flow collector 82 from the side, which helps to improve the transfer efficiency of the coolant and further improve the heat dissipation effect of the chip packaging structure.

[0092] In some embodiments, the flow collecting hole 82 is funnel-shaped, and the width of the end of the flow collecting hole 82 facing the flow channel partition 16 is greater than the width of the end of the flow collecting hole 82 away from the flow channel partition 16.

[0093] Specifically, the width of the end of the current collection hole 82 facing the flow channel partition 16 is greater than the width of the end of the current collection hole 82 away from the flow channel partition 16, making the current collection hole 82 funnel-shaped. This not only helps to simplify the manufacturing process of the current collection hole 82, but also helps to further improve the heat dissipation effect of the chip.

[0094] In some embodiments, the front side of the chip 70 includes a functional area and an edge area located outside the functional area, the edge area having trenches 84 distributed around the outer periphery of the functional area; the chip packaging structure further includes:

[0095] A solder layer 85 continuously covers the side surface of the chip 70, a portion of the edge area of ​​the chip 70, and at least a portion of the inner wall of the trench 84.

[0096] Specifically, the front side of the chip includes a functional area and an edge area located outside the functional area. Multiple conductive bumps 83 are disposed in the functional area for electrical connection with the packaging substrate. A trench 84 is disposed in the edge area of ​​the front side of the chip 70, and the trench 84 is distributed around the outer periphery of the functional area. A solder layer 85 continuously covers the side surface of the chip 70, a portion of the edge area of ​​the chip 70, and at least a portion of the inner wall of the trench 84. On the one hand, the heat dissipation layer 85 further enhances the side heat dissipation effect of the chip 70, and the trench 84 enhances the connection strength between the heat dissipation layer 85 and the chip 70. On the other hand, the trench 84 also prevents solder from flowing into the functional area of ​​the chip 70 when connecting the lower support frame 11 and the packaging base. In one example, the solder layer 85 is a copper layer and a solder layer covering the surface of the copper layer.

[0097] Figure 11 This is a top view of the packaging base in a specific embodiment of this utility model. Figure 12 This is a bottom view of the packaging base in a specific embodiment of this utility model. Figure 13 This is a partial schematic diagram of the chip, packaging base, and substrate in a specific embodiment of this utility model. In some embodiments, such as Figure 7 , Figure 11 , Figure 12 and Figure 13 As shown, the chip packaging structure further includes:

[0098] The chip 70 is disposed with its front side facing the top surface of the packaging substrate 72.

[0099] The packaging base 71 is located on the top surface of the packaging substrate 72. The packaging base 71 includes a base housing 711 and a device receiving cavity 712 that penetrates the base housing 711. The chip 70 is located in the device receiving cavity 712 and is electrically connected to the packaging substrate 72.

[0100] In some embodiments, the packaging base further includes:

[0101] The extension 714 is perpendicularly connected to the sidewall of the device receiving cavity 712, the edge region of the chip 70 is located on the extension 714, and the heat dissipation layer 85 is connected to the sidewall of the device receiving cavity 712.

[0102] Positioning posts 713 are connected to the base housing 711 and are distributed around the outer periphery of the device receiving cavity 712.

[0103] Specifically, the packaging substrate 72 includes a top surface and a bottom surface that are distributed opposite each other along the Z-axis direction, and the packaging base 71 is connected to the top surface of the packaging substrate 72. The chip packaging structure also includes a passive device 130, which is located on the packaging base 72, and the base housing 711 in the packaging base 71 covers the passive device 130 and part of the top surface of the packaging substrate 72. The passive device 130 can be a resistor or a capacitor. The packaging base 71 also includes a device receiving cavity 712 that extends through the base housing 711 along the Z-axis direction, and the chip 70 is mounted to the surface of the packaging substrate 72 through the device receiving cavity 712. For example, the chip 70 is flip-chip mounted on the top surface of the packaging substrate 72, and the conductive bumps 83 on the front side of the chip 70 are electrically connected to the packaging substrate 72. The extension 714 is perpendicularly connected to the sidewall of the device receiving cavity 712, such that the extension 714 and the sidewall of the device receiving cavity 712 together form an L-shaped structure. The edge area of ​​the chip 70 is located on the extension 714, and the solder layer 85 is connected to the sidewall of the device receiving cavity 712, thereby isolating the vacuum housing cavity 15 from the functional area on the front of the chip 70. A plurality of positioning posts 713 are connected to the base housing 711 and distributed around the outer periphery of the device receiving cavity 712, used to define the position of the chip 70 within the device receiving cavity 712 and also to protect the chip 70.

[0104] The heat sink and chip packaging structure provided in this specific embodiment, by setting an upper heat sink, a lower support frame, and a vacuum capillary heat dissipation tube located on the upper heat sink, the upper heat sink and the lower support frame together form a vacuum shell cavity, and the vacuum capillary heat dissipation tube communicates with the vacuum shell cavity. The side of the lower support frame has a liquid injection port, so that coolant can be injected through the liquid injection port. The coolant enters the vacuum shell cavity and can absorb the heat generated by the chip located in the vacuum shell cavity. Since the vacuum shell cavity and the vacuum capillary heat dissipation tube are both vacuum environments, the coolant is easily vaporized in the vacuum shell cavity after being heated and rises along the vacuum capillary heat dissipation tube. After reaching the top of the vacuum capillary heat dissipation tube, it re-liquefies due to the temperature difference and heat exchange with the air. The coolant is then collected into the microchannels inside the chip through multiple current collection components, thereby realizing the cyclic heat dissipation of the chip through coolant. This invention utilizes a combination of coolant phase change and microfluidic channels within the chip for heat dissipation. Both its thermal conductivity and transient response efficiency are tens to hundreds of times higher than those of heat dissipation materials such as pure copper, thereby improving heat dissipation performance, reducing heat accumulation within the chip, and enhancing the performance of the packaging structure. The heat sink provided in this specific embodiment is entirely a mechanical structure with no electrical components, thus improving the reliability of its heat dissipation function.

[0105] In some embodiments of this specific implementation, microchannels are formed inside the chip and communicate with the inner cavity of the vacuum shell within the heat sink. This allows the coolant to flow directly through the chip's interior along the microchannels, further increasing the chip's heat dissipation area and bringing the coolant closer to the heat source surface, resulting in lower thermal resistance and thus further improving the chip's heat dissipation performance. Moreover, the liquid phase change heat dissipation method utilizing coolant circulation almost negligibles contact thermal resistance issues, leading to even superior heat dissipation performance.

[0106] It should be noted that the terms "comprising" and "having," and their variations, used in this utility model document are intended to cover non-exclusive inclusion. The terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence, unless explicitly indicated by the context; it should be understood that such use of data can be interchanged where appropriate. The term "one or more" depends at least in part on the context and can be used to describe features, structures, or characteristics in a singular sense, or in a plural sense to describe combinations of features, structures, or characteristics. The term "based on" can be understood as not necessarily intended to express an exclusive set of factors, but can instead, also at least in part on the context, allow for the presence of other factors that are not necessarily explicitly described. Furthermore, embodiments and features in embodiments of this utility model can be combined with each other without conflict. In addition, descriptions of well-known components and technologies have been omitted in the above description to avoid unnecessarily obscuring the concepts of this utility model. In the various embodiments described above, each embodiment focuses on the differences from other embodiments; similar / identical parts between embodiments can be referred to mutually.

[0107] The above description is only a preferred embodiment of the present utility model. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present utility model, and these improvements and modifications should also be considered within the protection scope of the present utility model.

Claims

1. A heat dissipation cover, characterized in that, include: The upper heat dissipation cover includes an upper surface and a lower surface that are relatively distributed. The lower support frame is vertically connected to the lower surface end of the upper heat sink cover, and the upper heat sink cover and the lower support frame together form a vacuum housing cavity. The side of the lower support frame has a liquid injection port that communicates with the vacuum housing cavity. The vacuum housing cavity is used to accommodate the chip, and the liquid injection port is used to inject coolant into the vacuum housing cavity. A vacuum capillary heat dissipation tube is located on the upper surface of the upper heat dissipation cover. The vacuum capillary heat dissipation tube extends in a direction perpendicular to the upper surface of the upper heat dissipation cover and communicates with the inner cavity of the vacuum housing.

2. The heat dissipation cover according to claim 1, characterized in that, The upper heat dissipation cover has a vacuum capillary structure layer inside, one end of which is connected to the vacuum capillary heat dissipation tube and the other end is connected to the inner cavity of the vacuum housing.

3. The heat dissipation cover according to claim 1, characterized in that, Also includes: A flow channel partition, located in the inner cavity of the vacuum housing and used for mounting on the chip, the flow channel partition includes a plate body and a flow channel opening penetrating the plate body, the flow channel opening includes an upper end facing the upper heat sink and a lower end opposite to the upper end, and the width of the upper end of the flow channel opening is greater than the width of the lower end of the flow channel opening.

4. The heat dissipation cover according to claim 3, characterized in that, The plate is funnel-shaped, and the width of the surface of the plate facing the upper heat dissipation cover is greater than the width of the surface of the plate away from the upper heat dissipation cover.

5. The heat dissipation cover according to claim 1, characterized in that, Also includes: Heat dissipation fins are connected to the upper surface of the upper heat dissipation cover, and the heat dissipation fins are distributed around the outer periphery of the plurality of vacuum capillary heat dissipation tubes.

6. The heat dissipation cover according to claim 1, characterized in that, Multiple vacuum capillary heat dissipation tubes are arranged in a staggered pattern on the upper surface of the upper heat dissipation cover.

7. A chip packaging structure, characterized in that, include: The chip includes a front and a back side that are relatively distributed. A heat sink includes an upper heat sink, a lower support frame, and a vacuum capillary heat sink. The upper heat sink includes an upper surface and a lower surface that are distributed opposite to each other. The lower support frame is vertically connected to the end of the upper heat sink, and the upper heat sink and the lower support frame together form a vacuum housing cavity. The side of the lower support frame has a liquid injection port that communicates with the vacuum housing cavity. The chip is located in the vacuum housing cavity, and the liquid injection port is used to inject coolant into the vacuum housing cavity. The vacuum capillary heat sink is located on the upper surface of the upper heat sink and extends in a direction perpendicular to the top surface of the upper heat sink, and the vacuum capillary heat sink communicates with the vacuum housing cavity.

8. The chip packaging structure according to claim 7, characterized in that, The upper heat dissipation cover has a vacuum capillary structure layer inside, one end of which is connected to the vacuum capillary heat dissipation tube and the other end is connected to the inner cavity of the vacuum housing.

9. The chip packaging structure according to claim 7, characterized in that, The chip has a microchannel that runs through the chip and the microchannel is connected to the inner cavity of the vacuum housing.

10. The chip packaging structure according to claim 9, characterized in that, The heat sink also includes: A flow channel partition is located in the inner cavity of the vacuum housing and is attached to the back side of the chip. The flow channel partition includes a plate body and a flow channel opening that penetrates the plate body. The flow channel opening exposes the back side of the chip. The flow channel opening includes an upper end facing the upper heat sink and a lower end opposite to the upper end. The width of the upper end of the flow channel opening is greater than the width of the lower end of the flow channel opening.

11. The chip packaging structure according to claim 10, characterized in that, The plate is funnel-shaped, and the width of the surface of the plate facing the upper heat dissipation cover is greater than the width of the surface of the plate away from the upper heat dissipation cover. There is a gap between the plate and the upper heat dissipation cover.

12. The chip packaging structure according to claim 10, characterized in that, The microchannels include: A current collector is located on the back side of the chip; A heat dissipation channel is located inside the chip and communicates with the inner cavity of the vacuum housing. The heat dissipation channel penetrates the chip in a direction parallel to the back of the chip and communicates with the current collection hole.

13. The chip packaging structure according to claim 12, characterized in that, The plurality of the current collection holes are arranged in a two-dimensional array on the back side of the chip along a first direction and a second direction, both of which are parallel to the back side of the chip and intersect the second direction. A portion of the heat dissipation channels extend along the first direction and are spaced apart along the second direction, while another portion of the heat dissipation channels extend along the second direction and are spaced apart along the first direction, and each heat dissipation channel communicates with a plurality of flow collection holes arranged along its extension direction.

14. The chip packaging structure according to claim 12, characterized in that, The flow collecting hole is funnel-shaped, and the width of the end of the flow collecting hole facing the flow channel partition is greater than the width of the end of the flow collecting hole away from the flow channel partition.

15. The chip packaging structure according to claim 12, characterized in that, The front side of the chip includes a functional area and an edge area located outside the functional area, and the edge area has grooves distributed around the periphery of the functional area. The chip packaging structure also includes: A solder layer continuously covers the side surface of the chip, a portion of the edge region of the chip, and at least a portion of the inner wall of the trench.

16. The chip packaging structure according to claim 15, characterized in that, Also includes: A packaging substrate, wherein the front side of the chip is disposed facing the top surface of the packaging substrate; A packaging base is located on the top surface of the packaging substrate. The packaging base includes a base housing and a device receiving cavity penetrating the base housing. The chip is located in the device receiving cavity and is electrically connected to the packaging substrate.

17. The chip packaging structure according to claim 16, characterized in that, The packaging base also includes: An extension is perpendicularly connected to the sidewall of the device receiving cavity, the edge region of the chip is located on the extension, and the solder layer is connected to the sidewall of the device receiving cavity; Positioning posts are connected to the base housing and are distributed around the outer periphery of the device receiving cavity.

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