Electronic package and substrate structure thereof
By introducing parallel conductive modules into the substrate structure and utilizing shunt vias and circuit design, the problem of excessively long current paths caused by the distribution of power solder balls was solved, resulting in reduced resistance and improved circuit stability, thus meeting the requirements of high integration and miniaturization in semiconductor packaging.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- SILICONWARE PRECISION IND CO LTD
- Filing Date
- 2025-04-25
- Publication Date
- 2026-05-22
AI Technical Summary
In the prior art, the distribution of power solder balls in ball grid array semiconductor devices results in excessively long current paths and high resistance, which may cause circuit damage and make it difficult to meet the requirements of high integration and miniaturization.
Parallel conductive modules are introduced into the substrate structure, and the power circuit is branched by shunt holes and shunt lines to reduce resistance. This includes the design of conductive holes and shunt holes, connecting contact pads and wiring layers to form multiple parallel conductive modules to optimize power distribution.
By using a parallel conductive module design, the resistance of the power supply circuit is reduced, the efficiency of power supply is improved, circuit damage is avoided, and the requirements of high integration and miniaturization are met.
Smart Images
Figure CN224267273U_ABST
Abstract
Description
Technical Field
[0001] This application relates to a semiconductor structure, and more particularly to an electronic package and its substrate structure. Background Technology
[0002] With the booming development of the electronics industry, today's electronic products are trending towards thinner, lighter, smaller, and more functional designs, leading to the development of various packaging types in semiconductor packaging technology. To meet the demands for high integration and miniaturization in semiconductor devices, the industry largely adopts flip-chip packaging structures. Furthermore, whether electronic products can achieve the ideal of being lightweight, thin, short, small, and fast depends on the development of chips with high memory capacity, wide bandwidth, and low voltage requirements. However, whether chips can continuously improve memory capacity and operating frequency while reducing voltage requirements depends on the degree of integration of electronic circuitry on the chip, as well as the density of input / output connectors (I / O connectors) used to provide the medium for transmitting signals and power to electronic circuits.
[0003] Taking Ball Grid Array (BGA) semiconductor devices as an example, chip designs are increasingly featuring high I / O counts. Because signals need to be routed out of densely populated solder ball areas, signal solder balls are often located on the outer edge of the chip, forcing power supply solder balls to be arranged towards the inner edge. However, if the power supply pins are too far apart, the current path will be too long, resulting in high resistance and excessive voltage, potentially damaging the circuit.
[0004] Therefore, overcoming the various problems of the aforementioned conventional technologies has become an urgent issue for the industry. Utility Model Content
[0005] To address the problems of the prior art, this application provides a substrate structure, comprising: a substrate body having a crystal placement region defined on one surface thereon; a plurality of contact pads disposed within the crystal placement region; and at least one parallel conductive module disposed within the substrate body and connected to at least one of the contact pads.
[0006] This application further provides an electronic package, including: a substrate structure comprising a substrate body with a die-placement area defined on its surface, a plurality of contact pads disposed in the die-placement area, and at least one parallel conductive module disposed in the substrate body and connected to at least one of the contact pads; and an electronic component disposed in the die-placement area of the substrate structure and electrically connected to the plurality of contact pads.
[0007] As mentioned above, the electronic packaging components and their substrate structures are substrates with or without a core layer.
[0008] As described above in the electronic package and its substrate structure, part of the contact pad is used for signal transmission, part of the contact pad is used for power supply, and the parallel conductive module is used to provide power and is electrically connected to the contact pad used for power supply.
[0009] As described above, the electronic package and its substrate structure include a first shunt line, a second shunt line, a conductive hole, and at least one shunt hole.
[0010] As described above in the electronic package and its substrate structure, the conductive hole has two opposing ends, the shunt hole is adjacent to the conductive hole and has two opposing ends, and the conductive hole and the shunt hole are connected to the first shunt line at one end on the same side, and the conductive hole and the shunt hole are connected to the second shunt line at the other end on the other side.
[0011] As described above in the electronic package and its substrate structure, the first shunt line is connected to the contact pad, and the second shunt line is connected to the wiring layer within the substrate body.
[0012] As described above, the electronic package and its substrate structure have multiple parallel conductive modules formed in the substrate body.
[0013] As described above in the electronic package and its substrate structure, the distance between a contact pad connected to one of the parallel conductive modules and the edge of the die-placement area is different from the distance between another contact pad connected to another parallel conductive module and the edge of the die-placement area.
[0014] As described above in the electronic package and its substrate structure, the multiple parallel conductive modules each have a different number of shunt holes.
[0015] As described above in the electronic package and its substrate structure, the number of shunt holes in the parallel conductive module connected to the contact pad at a distance farther from the edge of the die-placement area is greater than the number of shunt holes in the parallel conductive module connected to the contact pad at a distance closer to the edge of the die-placement area.
[0016] Therefore, the electronic package and its substrate structure of this application mainly form parallel conductive modules in the substrate body, so as to increase the channels by increasing the power supply circuit by increasing the number of branches and thereby reducing the resistance. Attached Figure Description
[0017] Figure 1 This is a cross-sectional schematic diagram of the first embodiment of the substrate structure of this application.
[0018] Figure 2 This is a top view schematic diagram of the first embodiment of the substrate structure of this application.
[0019] Figure 3 This is a cross-sectional schematic diagram of the second embodiment of the substrate structure of this application.
[0020] Figure 4 This is a cross-sectional schematic diagram of the electronic package of this application.
[0021] Explanation of reference numerals in the attached figures
[0022] 1,2 Substrate Structure
[0023] 10 substrate body
[0024] 10a surface
[0025] 100 insulation layer
[0026] 101 Wiring Layer
[0027] 11 Contact pad
[0028] 12 parallel conductive modules
[0029] 121 First Diversion Line
[0030] 122 Second Diversion Line
[0031] 123 Conductive holes
[0032] 124 flow dividers
[0033] 3 Electronic Packages
[0034] 30 Electronic components
[0035] 31 Conductive bumps
[0036] 32 Conductive elements
[0037] D Crystal Placement Area
[0038] S, M distance. Detailed Implementation
[0039] The following specific embodiments illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification.
[0040] It should be understood that the structures, proportions, sizes, etc., depicted in the accompanying drawings are merely for illustrative purposes to aid those skilled in the art in understanding and reading the content disclosed herein, and are not intended to limit the scope of this application. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effectiveness and purpose of this application, should still fall within the scope of the technical content disclosed herein. Furthermore, the terms such as "above" and "a" used in this specification are merely for clarity of description and are not intended to limit the scope of this application. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of this application's implementation.
[0041] Please see Figure 1 and Figure 2 This is a cross-sectional view and a top view of the first embodiment of the substrate structure of this application.
[0042] The substrate structure 1 of this application is, for example, a packaging substrate for carrying a semiconductor chip, which includes a substrate body 10, a plurality of contact pads 11 and at least one parallel conductive module 12.
[0043] The substrate body 10 is, for example, a substrate with a core layer or a coreless substrate. The substrate body 10 has the plurality of contact pads 11 arranged on its surface 10a, and a crystal placement area D is defined on the surface 10a, and the plurality of contact pads 11 are disposed in the crystal placement area D.
[0044] In this embodiment, the substrate body 10 includes an insulating layer 100 and a wiring layer 101 connecting the insulating layer 100. The wiring layer 101 may be, for example, a fan-out type redistribution layer (RDL), and a plurality of contact pads 11 are formed on the outermost wiring layer 101. The die placement region D is used to place electronic components such as semiconductor chips or passive components thereon.
[0045] Furthermore, the wiring layer 101 is made of copper, and the insulating layer 100 is a dielectric material such as polybenzoxazole (PBO), polyimide (PI), or prepreg (PP).
[0046] The parallel conductive module 12 is disposed in the substrate body 10, with one end connected to at least one of the contact pads 11 and the other end connected to the wiring layer 101. Some of the contact pads 11 are used for signal transmission, and some of the contact pads 11 are used for power supply. The parallel conductive module 12 is designed to provide power and is electrically connected to the contact pads 11 used for power supply.
[0047] The parallel conductive module 12 includes a first shunt line 121, a second shunt line 122, a conductive hole 123, and at least one shunt hole 124.
[0048] In one embodiment, the conductive via 123 and the shunt via 124 may be formed as conductive blind vias. The conductive via 123 has two opposing ends, and the shunt via 124 is adjacent to the conductive via 123 and has two opposing ends. The conductive via 123 and the shunt via 124 are connected to the first shunt line 121 at one end on the same side, and the conductive via 123 and the shunt via 124 are connected to the second shunt line 122 at the other end on the other side. Further, the first shunt line 121 is connected to the contact pad 11 (e.g., through a conductive blind via), and the second shunt line 122 is connected to the wiring layer 101 within the substrate body 10. Accordingly, by adding more channels (shunt holes 124) to the original single power supply trace, the resistance of the entire power supply circuit is increased, thereby reducing the resistance. This allows the contact pad 11 used for power supply to be connected to the parallel conductive module 12, and the resistance can be reduced through the shunt holes 124 of the parallel conductive module 12, thus avoiding power supply problems.
[0049] Furthermore, the substrate body 10 may form multiple parallel conductive modules 12, wherein the distance S between a contact pad 11 connected to one parallel conductive module 12 and the edge of the crystal placement area D is different from the distance M between another contact pad 11 connected to another parallel conductive module 12 and the edge of the crystal placement area D (e.g., Figure 2 As shown), for example, the distance S is less than the distance M, so that the position of the contact pad 11 can be configured according to actual needs.
[0050] Please also refer to Figure 3 This is a cross-sectional schematic diagram of the second embodiment of the substrate structure 2 of this application. This embodiment is largely the same as the first embodiment, with the main difference being that this embodiment has multiple parallel conductive modules 12 in the substrate body 10, and each of these parallel conductive modules 12 has a different number of shunt holes 124. For example, each of the multiple parallel conductive modules 12 may have one, two, three, or more shunt holes 124, which can be modified according to actual power requirements. The corresponding... Figure 2 The number of shunt holes 124 in the parallel conductive module 12 connected to the contact pad 11 at a distance M from the edge of the crystal placement area D is greater than the number of shunt holes 124 in the parallel conductive module 12 connected to the contact pad 11 at a distance S from the edge of the crystal placement area D. Therefore, even if the pins of the power supply are distributed far apart, resulting in a longer current path, the resistance can still be reduced by increasing the number of shunt holes 124 to increase the number of branches in the entire power supply circuit.
[0051] Please see Figure 4This is a cross-sectional schematic diagram of the electronic package 3 of this application, which mainly involves placing electronic components 30 on the aforementioned substrate structure 1 and electrically connecting the electronic components 30 to the substrate structure 1.
[0052] The electronic component 30 is an active component, a passive component, or a combination thereof, and is disposed in the crystal placement area of the substrate structure 1. The active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor, and an inductor.
[0053] In this embodiment, the electronic component 30 is a semiconductor chip, which is disposed on the multiple contact pads 11 in a flip-chip manner through multiple conductive bumps 31 such as solder material and is electrically connected to the parallel conductive module 12.
[0054] In addition, multiple conductive elements 32 can be disposed on another surface of the substrate structure 1 so that the electronic package 3 can be electrically connected to an external device through the multiple conductive elements 32.
[0055] In summary, the electronic package and its substrate structure of this application mainly form parallel conductive modules in the substrate body, so as to increase the channels by increasing the number of channels in the power supply circuit and thereby reducing the resistance.
[0056] The above embodiments are used to illustrate the principles and effects of this application, and are not intended to limit this application. Those skilled in the art can modify the above embodiments without departing from the spirit and scope of this application. Therefore, the scope of protection of this application should be as set forth in the claims.
Claims
1. A substrate structure, characterized in that, include: A substrate body has a crystal placement region defined on one of its surfaces; Multiple contact pads are disposed within the crystal placement area; as well as At least one parallel conductive module is disposed within the substrate body and connected to at least one of the contact pads.
2. The substrate structure as described in claim 1, characterized in that, The substrate body can be a substrate with a core layer or a substrate without a core layer.
3. The substrate structure as described in claim 1, characterized in that, Part of the contact pad is used for signal transmission, part of the contact pad is used for power supply, and the parallel conductive module is used to provide power and is electrically connected to the contact pad used for power supply.
4. The substrate structure as described in claim 1, characterized in that, The parallel conductive module includes a first shunt line, a second shunt line, a conductive hole, and at least one shunt hole.
5. The substrate structure as described in claim 4, characterized in that, The conductive hole has two opposite ends, and the shunt hole is adjacent to the conductive hole and has two opposite ends. The conductive hole and the shunt hole are connected to the first shunt line at one end on the same side, and the conductive hole and the shunt hole are connected to the second shunt line at the other end on the other side.
6. The substrate structure as described in claim 4, characterized in that, The first shunt line is connected to the contact pad, and the second shunt line is connected to the wiring layer within the substrate body.
7. The substrate structure as described in claim 4, characterized in that, Multiple parallel conductive modules are formed in the substrate body.
8. The substrate structure as described in claim 7, characterized in that, The distance between a contact pad connected to one of the parallel conductive modules and the edge of the crystal placement area is different from the distance between another contact pad connected to another parallel conductive module and the edge of the crystal placement area.
9. The substrate structure as described in claim 7, characterized in that, Multiple parallel conductive modules each have a different number of shunt holes.
10. The substrate structure as described in claim 7, characterized in that, The number of shunt holes in the parallel conductive module connected to the contact pad at a greater distance from the edge of the crystal placement area is greater than the number of shunt holes in the parallel conductive module connected to the contact pad at a closer distance from the edge of the crystal placement area.
11. An electronic package, characterized in that, include: A substrate structure includes a substrate body with a crystal placement area defined on its surface, a plurality of contact pads disposed in the crystal placement area, and at least one parallel conductive module disposed in the substrate body and connected to at least one of the contact pads. as well as Electronic components are disposed in the crystal placement area of the substrate structure and electrically connected to the plurality of contact pads.
12. The electronic package as claimed in claim 11, characterized in that, The substrate body can be a substrate with a core layer or a substrate without a core layer.
13. The electronic package as claimed in claim 11, characterized in that, Part of the contact pad is used for signal transmission, part of the contact pad is used for power supply, and the parallel conductive module is used to provide power and is electrically connected to the contact pad used for power supply.
14. The electronic package as claimed in claim 11, characterized in that, The parallel conductive module includes a first shunt line, a second shunt line, a conductive hole, and at least one shunt hole.
15. The electronic package as claimed in claim 14, characterized in that, The conductive hole has two opposing ends, and the shunt hole is adjacent to the conductive hole and has two opposing ends. The conductive hole and the shunt hole are connected to the first shunt line at one end on the same side, and the conductive hole and the shunt hole are connected to the second shunt line at the other end on the other side.
16. The electronic package as claimed in claim 14, characterized in that, The first shunt line is connected to the contact pad, and the second shunt line is connected to the wiring layer within the substrate body.
17. The electronic package as claimed in claim 14, characterized in that, Multiple parallel conductive modules are formed in the substrate body.
18. The electronic package as claimed in claim 17, characterized in that, The distance between a contact pad connected to one of the parallel conductive modules and the edge of the crystal placement area is different from the distance between another contact pad connected to another parallel conductive module and the edge of the crystal placement area.
19. The electronic package as claimed in claim 17, characterized in that, Multiple parallel conductive modules each have a different number of shunt holes.
20. The electronic package as claimed in claim 17, characterized in that, The number of shunt holes in the parallel conductive module connected to the contact pad at a greater distance from the edge of the crystal placement area is greater than the number of shunt holes in the parallel conductive module connected to the contact pad at a closer distance from the edge of the crystal placement area.