Semiconductor structure

Abstract

The utility model discloses a semiconductor structure, which comprises a plurality of active regions arranged on a substrate, a plurality of gate structures extending along a first direction and intersecting with the active regions, and dividing each active region into a middle part and two end parts. The plurality of bit line structures extend across the active region in the second direction and are electrically connected with the middle part of the active region. The bit line structures include a first bit line structure on the outer side and a second bit line structure on the inner side. The first plug structures and the second plug structures are alternately arranged on the outer side of the first bit line structure at intervals in the second direction, the bottoms of the first plug structures are lower than the bottoms of the second plug structures, the contact area between the bottoms of the first plug structures and the ends of the active region is large, and the electric connection quality can be improved.

Description

Technical Field

[0001] This utility model relates to a semiconductor structure, and more particularly to a semiconductor structure with a plug structure. Background Technology

[0002] Dynamic random access memory (DRAM) is a type of volatile memory that includes an array region consisting of multiple memory cells and a peripheral area consisting of control circuitry. Each memory cell consists of a transistor and a capacitor electrically connected to the transistor. The transistor controls the storage and release of charge in the capacitor to store data. The control circuitry addresses each memory cell and controls data access to each cell via word lines (WL) and bit lines (BL) that span the array region and are electrically connected to each memory cell.

[0003] To achieve higher chip density, memory cell structures have evolved towards three-dimensional designs, such as those employing buried word lines and stacked capacitors. Stacked capacitor technology involves placing the capacitors of the memory cell above the substrate and using plug and connection pad structures to achieve vertical electrical connections with transistors in the substrate. This saves substrate area occupied by the capacitors and allows for easier increases in capacitance by increasing the height of the capacitor's electrode plates. However, some technical challenges remain that require further improvement. Utility Model Content

[0004] The purpose of this invention is to provide a semiconductor structure with plug structures of different depths, which can improve the contact quality between the plug structure and the active region of the transistor.

[0005] This invention provides a semiconductor structure including a substrate comprising multiple active regions. Multiple gate structures extend along a first direction and intersect the active regions, dividing each active region into a central portion and two end portions. Multiple bit line structures extend along a second direction and are electrically connected to the central portion of the active regions, wherein the first direction and the second direction are perpendicular to each other, and each bit line structure includes an outer first bit line structure and an inner second bit line structure. Multiple first plug structures and second plug structures are alternately and spaced apart along the second direction outside the first bit line structures and are electrically connected to the end portions, wherein the bottom of the first plug structure is lower than the bottom of the second plug structure.

[0006] This invention provides a semiconductor structure including a substrate with multiple active regions. Multiple gate structures extend along a first direction and intersect the active regions. Multiple spacers are disposed on the gate structures. Multiple first plug structures and second plug structures are alternately arranged between the spacers along a second direction and are electrically connected to the active regions, wherein the bottom of the first plug structure is lower than the bottom of the second plug structure.

[0007] This invention provides a semiconductor structure including a substrate comprising multiple active regions. Multiple gate structures extend along a first direction and intersect the active regions. Multiple bit line structures extend along a second direction and are electrically connected to the active regions, wherein the first direction and the second direction are perpendicular to each other, and each bit line structure includes an outer first bit line structure and an inner second bit line structure. At least one first plug structure is disposed outside the first bit line structure. Multiple third plug structures are disposed inside the first bit line structure and between the second bit line structures and arranged with the first plug structures along the first direction, wherein in a cross-sectional view, the bottom of the first plug structure is lower than the bottom of the third plug structure, and the width of the first plug structure is greater than the width of the third plug structure. Attached Figure Description

[0008] Figures 1 to 16 The diagram illustrates the structure of a semiconductor structure according to an embodiment of the present invention during the manufacturing process, wherein... Figure 1 , Figure 7 and Figure 12 This is a floor plan. Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 8 and Figure 13 This is a cross-sectional view of the semiconductor structure taken along the tangent line AA in the plan view. Figure 6 , Figure 9 and Figure 14This is a cross-sectional view of the semiconductor structure taken along the BB tangent in the plan view. Figure 10 and Figure 15 This is a cross-sectional view of the semiconductor structure taken along the CC tangent in the planar view. Figure 11 and Figure 16 This is a cross-sectional view of the semiconductor structure taken along the DD tangent in the planar diagram.

[0009] The reference numerals in the attached figures are explained as follows:

[0010] PR surrounding area

[0011] AR array area

[0012] 100 substrate

[0013] 102 Active Zone

[0014] 104 Isolation Structure

[0015] 106 gate structure

[0016] 108 Insulation Pad

[0017] 122 Semiconductor Layer

[0018] 124 Interface Layer

[0019] 126 Metal Layer

[0020] 128 Hard Mask Layers

[0021] 132 Gate dielectric layer

[0022] 134 Metal Layer

[0023] 136 polycrystalline silicon layers

[0024] 138 Insulating Cover

[0025] 142 First Insulation Layer

[0026] 144 Second Insulation Layer

[0027] 152 Third Insulation Layer

[0028] 154 Dielectric Layer

[0029] 156 Spacers

[0030] 162 Contact Material Layer

[0031] 164 Barrier Layer

[0032] 166 conductive layer

[0033] 172 Insulation Materials

[0034] 174 Etching Stop Layer

[0035] 176 Support layer

[0036] 108a silicon oxide layer

[0037] 108b silicon nitride layer

[0038] 108c silicon oxide layer

[0039] 144s gap

[0040] AA tangent

[0041] BB tangent

[0042] BE bottom electrode

[0043] BL bitline structure

[0044] BL1 First Line Structure

[0045] BL2 Second Bit Line Structure

[0046] CAP capacitor structure

[0047] CC tangent

[0048] D1 First Direction

[0049] D2 Second Direction

[0050] D3 third direction

[0051] D4 Fourth Direction

[0052] DBL Virtual Bitline Structure

[0053] DD tangent

[0054] IL capacitor dielectric layer

[0055] OP1 First Contact Hole

[0056] OP2 Second Contact Hole

[0057] OP3 Third Contact Hole

[0058] OP4 Fourth Contact Hole

[0059] R1 First Depression

[0060] R2 Second Depression

[0061] SC1 First plug structure

[0062] SC2 Second Plug Structure

[0063] SC3 Third Plug Structure

[0064] SC4 Fourth Plug Structure

[0065] SNP contact pads

[0066] SP sidewall structure

[0067] TE top electrode

[0068] W1 width

[0069] W1' width

[0070] W1" width

[0071] W2 width

[0072] Width

[0073] Wb width

[0074] Wc width

[0075] Wd width Detailed Implementation

[0076] To enable those skilled in the art to further understand this utility model, preferred embodiments are described below, along with accompanying drawings, to explain in detail the structure and desired effects of this utility model. It should be understood that the following embodiments can be modified by substituting, recombining, or mixing features from several different embodiments without departing from the spirit of this utility model to achieve other embodiments.

[0077] To facilitate reader comprehension and maintain the simplicity of the illustrations, many of the figures in this disclosure depict only a portion of the semiconductor structure, and specific components are not drawn to scale. Furthermore, the number and dimensions of the components in the figures are for illustrative purposes only and are not intended to limit the scope of this disclosure. The descriptions of the vertical relationships between components in the figures should be understood by those skilled in the art to refer to their relative positions; therefore, the same structure can be obtained by flipping the figures, and all of this should fall within the scope of this specification.

[0078] To facilitate explanation and understanding of the semiconductor structure of this invention, the figures show spatial reference directions D1, D2, D3, and D4. The first direction D1, D2, and D3 are parallel to the surface of the substrate 100, and the first direction D1 and the second direction D2 are perpendicular to each other and different from the third direction D3. The angle between the second direction D2 and the third direction D3 can be between 15 degrees and 75 degrees, but is not limited to this. The fourth direction D4 is perpendicular to the surface of the substrate 100. The first direction D1, the second direction D2, and the third direction D3 can also be referred to as horizontal directions, and the fourth direction D4 can also be referred to as vertical directions.

[0079] Figures 1 to 16 The diagram illustrates the structure of a semiconductor structure according to an embodiment of the present invention during the manufacturing process. Figure 13 Figure 15 For the sake of simplicity, some components may be omitted from the figures. The semiconductor structure of this invention can be used to manufacture dynamic random access memory (DRAM) including stacked capacitors. Without departing from the spirit of this invention, it can also be used to manufacture other types of semiconductor devices.

[0080] Please refer to Figure 1 and Figure 2 First, a substrate 100 is provided, such as a silicon substrate, epitaxial silicon substrate, silicon-germanium substrate, silicon carbide substrate, or silicon-on-insulator (SOI) substrate, but not limited thereto. The substrate 100 includes an array region AR and a peripheral region PR. The array region AR, also referred to as a cell region, is the area where an array of memory cells is disposed, where the memory cells are, for example, dynamic random access memory cells. The peripheral region PR is disposed adjacent to the outer side of the array region AR, separating the array region AR from other circuit regions of the substrate 100. In some embodiments, the peripheral region PR may also include peripheral circuitry, such as drivers, buffers, amplifiers, and decoders, but is not limited thereto.

[0081] The substrate 100 includes an isolation structure 104 and a plurality of active regions 102 defined by the isolation structure 104. The isolation structure 104 is, for example, a shallow trench isolation (STI) structure and may be composed of a single layer or multiple layers of dielectric material. Suitable dielectric materials may include, for example, silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), or combinations thereof, but are not limited thereto. The active regions 102 are separated from each other by the isolation structure 104 and are elongated strips with their long axes extending along a third direction D3. The active regions 102 are arranged in an active region array, alternating along a second direction D2 and a first direction D1.

[0082] Multiple gate structures 106 are disposed on the substrate 100, extending along a first direction D1 and arranged in parallel along a second direction D2, and cutting through the active region 102 to divide each active region 102 into two ends and a middle portion. The portion of the gate structure 106 cutting through the active region 102 is the gate of the transistor in the memory cell. The portion of the gate structure 106 cutting through the isolation structure 104 is the passing gate.

[0083] According to one embodiment of the present invention, the manufacturing steps of the gate structure 106 may include forming a gate trench in the substrate 100 that cuts through the isolation structure 104 and the active region 102, then forming a gate dielectric layer 132 along the bottom surface and sidewalls of the gate trench, then forming a metal layer 134 to fill the lower part of the word line trench, and then forming an insulating capping layer 138 to fill the upper part of the word line trench. The insulating capping layer 138 and the gate dielectric layer 132 may each include a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), or a combination of the above materials, but are not limited thereto. In some embodiments, the metal layer 134 may include a low-resistivity metal, such as tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), titanium nitride (TiN), or a compound, alloy, and / or composite layer of the above materials, but are not limited thereto. In some embodiments, a polysilicon layer 136 may be included between the metal layer 134 and the insulating capping layer 138 to adjust the conductivity of the gate structure 106.

[0084] After the gate structure 106 is fabricated, an insulating pad layer 108 is formed on the substrate 100. Then, an etching process is performed to form a first recess R1 and a second recess R2 that pass through the insulating pad layer 108 and expose the middle part of the active region 102 of the array region AR. Then, a bit line material stack (not shown) is formed on the substrate 100 to completely cover the substrate 100 and fill the first recess R1 and the second recess R2. Then, an etching process is performed to remove the excess part of the bit line material stack to obtain multiple bit line structures BL and dummy bit line structures DBL.

[0085] In some embodiments, the insulating pad 108 may be a composite layer, such as an ONO composite layer composed of a silicon oxide layer 108a, a silicon nitride layer 108b, and a silicon oxide layer 108c, but is not limited thereto.

[0086] The first recess R1 is located outside the array region AR, and the second recess R2 is located inside the array region AR. The first recess R1 and the second recess R2 have generally circular or elliptical outlines in a plan view. Along the first direction D1, the width W1 of the first recess R1 is greater than the width W2 of the second recess R2, and the first recess R1 is slightly offset towards the peripheral region PR. Therefore, the active region 102 exposed from the first recess R1 is not located at the center of the first recess R1, but rather closer to the inner side of the first recess R1 (the side furthest from the peripheral region PR). In some embodiments, the depths of the first recess R1 and the second recess R2 are approximately equal.

[0087] Bit line structures BL extend along the second direction D2 and are arranged parallel to each other along the first direction D1 on the array region AR of the substrate 100. From bottom to top, the bit line structures BL may sequentially include a semiconductor layer 122, an interface layer 124, a metal layer 126, and a hard mask layer 128. The material of the semiconductor layer 122 may include crystalline silicon, polycrystalline silicon, amorphous silicon, doped silicon, silicon-germanium (SiGe), or other suitable semiconductor materials, but is not limited thereto. The material of the interface layer 124 may include metals, metal silicides, or metal nitrides, such as titanium (Ti), titanium nitride (TiN), tungsten silicide (WSi), cobalt silicide (CoSi), tungsten nitride (WN), but is not limited thereto. The material of the metal layer 126 may include tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or compounds, alloys, and / or composite layers of the aforementioned metal materials, but is not limited thereto. The hard mask layer 128 may include a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), or a combination of the above materials, but is not limited thereto. According to one embodiment of the present invention, the semiconductor layer 122 is made of polysilicon, the interface layer 124 is made of tungsten silicide (WSi), the metal layer 126 is made of tungsten (W), and the hard mask layer 128 is made of silicon nitride (SiN). The bit line structure BL includes a first bit line structure BL1 on the outer side (adjacent to the peripheral region PR) and a second bit line structure BL2 on the inner side (away from the peripheral region PR). The first bit line structure BL1 is in direct contact with the middle portion of the active region 102 exposed by the first recess R1. The second bit line structure BL2 is in direct contact with the middle portion of the active region 102 exposed by the second recess R2. Figure 2As shown, since the first recess R1 is slightly offset towards the peripheral region PR, the portions of the first recess R1 exposed on both sides of the first line structure BL1 have different widths, wherein the width W1' of the outer side is greater than the width W1 of the inner side.

[0088] A dummy bit line DBL is disposed on the peripheral region PR of the substrate 100 adjacent to the outer side of the first bit line structure BL1, and extends along the second direction D2, crossing the active region 102 disposed in the peripheral region PR. The dummy bit line DBL has the same stacked structure and material as the bit line structure BL. The active region 102 of the peripheral region PR and the dummy bit line DBL are completely isolated by an insulating pad 108 and do not make direct contact.

[0089] Please refer to Figure 3 Next, a first insulating layer 142 and a second insulating layer 144 are sequentially formed to conformally cover the insulating pad layer 108, the first recess R1, the second recess R2, and the top and sidewalls of the bit line structure BL and the dummy bit line structure DBL. The first insulating layer 142 and the second insulating layer 144 comprise different dielectric materials, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), or combinations thereof, but are not limited thereto. According to one embodiment of the present invention, the first insulating layer 142 comprises silicon nitride (SiN), and the second insulating layer 144 comprises silicon oxide (SiO2). The thickness of the second insulating layer 144 needs to be controlled to completely fill the second recess R2 exposed on both sides of the second bit line structure BL2 and the first recess R1 inside the first bit line structure BL1, but not to fill the first recess R1 outside the first bit line structure BL1, thus forming a gap 144s in the second insulating layer 144 at that location.

[0090] Please refer to Figure 4 Next, an etching process is performed to remove part of the second insulating layer 144, so that the remaining second insulating layer 144 only fills the first recess R1 and the second recess R2, and exposes the first insulating layer 142 covering the top surface and sidewalls of the dummy bit line structure DBL, the first bit line structure BL1 and the second bit line structure BL2, and the insulating pad layer 108.

[0091] Please refer to Figure 5 and Figure 6 Next, a third insulating layer 152 is formed on the sidewalls of the dummy bit line structure DBL, the first bit line structure BL1, and the second bit line structure BL2. Then, a dielectric layer 154 is formed to fill the gap between the dummy bit line structure DBL, the first bit line structure BL1, and the second bit line structure BL2. The dielectric layer 154 directly above the gate structure 106 is then etched away, and the spacer 156 is refilled, thereby forming a spacer layer 152 between the dummy bit line structure DBL, the first bit line structure BL1, and the second bit line structure BL2. Figure 6The diagram shows an alternating arrangement of dielectric layer 154 and spacers 156. The third insulating layer 152, dielectric layer 154, and spacers 156 are made of dielectric materials, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), or combinations thereof, but are not limited thereto. According to one embodiment of the present invention, the material of the third insulating layer 152 includes silicon nitride (SiN), the material of the dielectric layer 154 includes silicon oxide (SiO2), and the material of the spacers 156 includes silicon nitride (SiN).

[0092] Please refer to Figure 7 , Figure 8 , Figure 9 , Figure 10 and Figure 11 Next, using spacer 156 and hard mask layer 128 as a mask, an etching process is performed to remove part of dielectric layer 154 to form multiple openings separated by spacer 156 between dummy bit line structure DBL, first bit line structure BL1 and second bit line structure BL2. Then, the first insulating layer 142, insulating pad layer 108, second insulating layer 144 and active region 102 are etched down through these openings to obtain multiple contact holes, including first contact hole OP1 and second contact hole OP2 arranged alternately along the second direction D2 between the outer side of first bit line structure BL1 and dummy bit line structure DBL, and third contact hole OP3 and fourth contact hole OP4 arranged alternately along the second direction D2 between the inner side of first bit line structure BL1 and second bit line structure BL2 and between adjacent second bit line structures BL2. In some embodiments, a dielectric layer 154 may be retained on the sidewalls of the dummy bit line structure DBL, the first bit line structure BL1, and the second bit line structure BL2, and together with the first insulating layer 142 and the second insulating layer 144, constitutes the sidewall structure SP.

[0093] The first contact hole OP1 and the third contact hole OP3 are aligned along the first direction D1. One side of the first contact hole OP1 overlaps with the end portion of the active region 102 crossed by the dummy bit line structure DBL, and the other side overlaps with the first recess R1. One side of the third contact hole OP3 overlaps with the end portion of the active region 102 crossed by the second bit line structure BL2, while the other side of the third contact hole OP3 located next to the first bit line structure BL1 overlaps with the first recess R1, and the other side of the remaining third contact holes OP3 overlaps with the second recess R2. Along the first direction D1, the first contact hole OP1 has a width Wa, and the third contact hole OP3 has a width Wc. In some embodiments, the width Wa is greater than the width Wc.

[0094] The second contact hole OP2 and the fourth contact hole OP4 are aligned along the first direction D1. One side of the second contact hole OP2 overlaps with the end portion of the active region 102 crossed by the first bit line structure BL1, and the other side is adjacent to or partially overlaps with the middle portion of the active region 102 crossed by the dummy bit line structure DBL. One side of the fourth contact hole OP4 overlaps with the end portion of the active region 102 crossed by the second bit line structure BL2, and the other side partially overlaps with the second recess R2. Along the first direction D1, the second contact hole OP2 has a width Wb, and the fourth contact hole OP4 has a width Wd. In some embodiments, the width Wb is greater than or equal to the width Wd. In some embodiments, the widths Wb, Wc, and Wd are equal. In some embodiments, the width Wa of the first contact hole OP1 is greater than the width Wb of the second contact hole OP2, the width Wc of the third contact hole OP3, and the width Wd of the fourth contact hole OP4.

[0095] It is worth noting that, due to the gap 144s (reference) of the second insulating layer 144 Figure 5 This makes it easier for the etchant to penetrate downwards, therefore, under the same etching process conditions, the depth of the first contact hole OP1 will be greater than the depths of the second contact hole OP2, the third contact hole OP3, and the fourth contact hole OP4. In some embodiments, such as Figure 8 and Figure 10 As shown, the bottom surfaces of the second contact hole OP2, the third contact hole OP3, and the fourth contact hole OP4 are lower than the bottom surface of the insulating pad 108, but not lower than the bottom surface of the first recess R1 or the second recess R2. The bottom surface of the first contact hole OP1 is lower than the bottom surface of the first recess R1. In some embodiments, such as Figure 9 and Figure 11 As shown, the bottom surfaces of the first contact hole OP1, the second contact hole OP2, the third contact hole OP3, and the fourth contact hole OP4 are all higher than the top surface of the metal layer 134 of the gate structure 106. In some embodiments, such as Figure 10 and Figure 11 As shown, the depths of the second contact hole OP2, the third contact hole OP3, and the fourth contact hole OP4 are approximately equal.

[0096] Please refer to Figure 12 , Figure 13 , Figure 14 , Figure 15 and Figure 16Next, a contact material layer 162 is formed to fill the lower half of the first contact hole OP1, the second contact hole OP2, the third contact hole OP3, and the fourth contact hole OP4. Then, a barrier layer 164 is formed to conformally cover the top surface of the contact material layer 162, the sidewalls of the first contact hole OP1, the second contact hole OP2, the third contact hole OP3, and the fourth contact hole OP4, as well as the top surface of the sidewall structure SP, the dummy bit line structure DBL, the first bit line structure BL1, and the second bit line structure BL2. Then, a conductive layer 166 is formed to completely cover the dummy bit line structure DBL, the first bit line structure BL1, and the second bit line structure BL2 and fill the upper half of the first contact hole OP1, the second contact hole OP2, the third contact hole OP3, and the fourth contact hole OP4. Next, an etching process is performed to remove excess conductive layer 166 and barrier layer 164. The conductive layer 166 and barrier layer 164 outside the openings of the first contact hole OP1, second contact hole OP2, third contact hole OP3, and fourth contact hole OP4 are patterned into multiple separate contact pads SNPs. Simultaneously, first plug structures SC1, second plug structure SC2, third plug structure SC3, and fourth plug structure SC4 are obtained, respectively disposed within the first contact hole OP1, second contact hole OP2, third contact hole OP3, and fourth contact hole OP4. The dimensions of the plug structures are determined by the dimensions of the contact holes; therefore, along the first direction D1, the widths of the first plug structure SC1, second plug structure SC2, third plug structure SC3, and fourth plug structure SC4 are Wa, Wb, Wc, and Wd, respectively.

[0097] The first plug structure SC1, the second plug structure SC2, the third plug structure SC3, and the fourth plug structure SC4 each include a contact material layer 162 located in the lower half and in direct contact with the active region 102, a conductive layer 166 located on the contact material layer 162, and a barrier layer 164 along the bottom surface and sidewalls of the conductive layer 166. The contact material layer 162 may include semiconductor materials, such as crystalline silicon, polycrystalline silicon, amorphous silicon, doped silicon, and silicon-germanium (SiGe), but is not limited thereto. The materials of the barrier layer 164 and the conductive layer 166 may include tungsten (W), titanium (Ti), nitrides, silicides, alloys, and / or composite layers of the aforementioned materials, but are not limited thereto. According to one embodiment of the present invention, the material of the contact material layer 162 includes phosphorus (P)-doped silicon, the material of the barrier layer 164 includes titanium nitride (TiN), and the material of the conductive layer 166 includes tungsten (W). The contact pad SNP is integrally formed with the conductive layer 166 of the first plug structure SC1, the second plug structure SC2, the third plug structure SC3, or the fourth plug structure SC4, and includes the same material. In some embodiments, such as Figure 12As shown, the contact pads SNPs are aligned along the first direction D1 and staggered along the second direction D2, partially overlapping the dummy bit line structure DBL and the first bit line structure BL1 and the second bit line structure BL2. In some embodiments, the contact pads SNPs may partially overlap with the spacer 156 directly above the gate structure 106. This design increases the arrangement density of the contact pads SNPs and provides a larger process window for the subsequent fabrication of the bottom electrode BE of the capacitor structure CAP, improving the electrical connection quality with the bottom electrode (not shown).

[0098] Thus, the semiconductor structure of this embodiment is obtained. For example... Figure 12 , Figure 13 , Figure 14 , Figure 15 and Figure 16 As shown, the semiconductor structure includes a substrate 100, which includes an array region AR and a peripheral region PR. Multiple active regions 102 are disposed on the array region AR and the peripheral region PR of the substrate 100. Multiple gate structures 106 extend along a first direction D1 through the array region AR and the peripheral region PR, intersecting with the active regions 102 to divide each active region 102 into a middle portion and two ends. Multiple bit line structures BL are disposed on the array region AR, extending along a second direction D2 across the active regions 102, and directly contacting and electrically connecting with the middle portion of the active regions 102, wherein the first direction D1 and the second direction D2 are perpendicular to each other. The bit line structure BL includes a first bit line structure BL1 on the outer side (adjacent to the peripheral region PR) and a second bit line structure BL2 on the inner side (away from the peripheral region PR). A dummy bit line junction DBL is disposed on the peripheral region, extending along the second direction D2 across the active region 102. The dummy bit line junction DBL is completely separated from and electrically isolated from the active regions 102 by an insulating pad layer 108. Multiple first plug structures SC1 and second plug structures SC2 are alternately and spaced along the second direction D2 between the outer side of the first line structure B1 and the dummy position line junction DBL, and are electrically connected to the end of the active region 102 respectively. Multiple third plug structures SC3 and fourth plug structures SC4 are alternately arranged along the second direction D2 between the inner side of the first line structure BL1 and the adjacent second position line structure BL2, and are electrically connected to the end of the active region 102 respectively. The third plug structure SC3 is aligned with the first plug structure SC1 along the first direction D1, and the fourth plug structure SC4 is aligned with the second plug structure SC2 along the first direction D1. As mentioned above, due to the gap 144s (reference) in the second insulating layer 144 at the expected location of the first contact hole OP1, Figure 5This design allows the etchant to penetrate more easily, resulting in a deeper first contact hole OP1 than the second, third, and fourth contact holes OP2, OP3, and OP4. Consequently, the bottom of the first plug structure SC1 within the first contact hole OP1 is lower than the bottom of the second, third, and fourth plug structures S2, S3, and S4 within the second, third, and fourth contact holes OP2, OP3, and OP4, respectively. The first plug structure SC1 extends further into the substrate 100, increasing the contact area between the first plug structure SC1 and the end of the active region 102, thereby reducing contact resistance and improving electrical connection quality.

[0099] In some embodiments, such as Figure 13 and Figure 15 As shown, the bottom of the first plug structure SC1 is lower than the bottom surface of the first recess R1, while the bottoms of the second plug structures SC2, the third plug structure SC3, and the fourth plug structure SC4 are not lower than the bottom surface of the second recess R2. In other words, the bottom of the first plug structure SC1 is lower than the top surface of the middle portion of the recessed active region 102, and the bottoms of the second plug structures SC2, the third plug structure SC3, and the fourth plug structure SC4 are not lower than the top surface of the middle portion of the recessed active region 102. The bottom of the semiconductor layer 122 of the portion of the first bit line structure BL1 located within the first recess R1 is higher than the bottom of the first plug structure SC1, while the bottom of the semiconductor layer 122 of the portion of the second bit line structure BL2 located within the second recess R2 is lower than the bottoms of the second plug structures SC2, the third plug structure SC3, and the fourth plug structure SC4.

[0100] In some embodiments, such as Figure 14 As shown, the first plug structure SC1 and the second plug structure SC2 are alternately arranged between the spacers 156. The bottoms of the first plug structure SC1 and the second plug structure SC2 extend below the top surface of the insulating cap layer 138 of the gate structure 106 and above the top surface of the metal layer 134 of the gate structure 106, and are arranged in an alternating high-low configuration. In some embodiments, when the gate structure 106 further includes a polysilicon layer 136 disposed between the metal layer 134 and the insulating cap layer 138, the bottoms of the first plug structure SC1 and the second plug structure SC2 are both above the top surface of the polysilicon layer 136.

[0101] In some embodiments, such as Figure 15 and Figure 16 As shown, the bottoms of the second plug structure SC2, the third plug structure SC3, and the fourth plug structure SC4 are approximately at the same depth within the substrate 100 and are aligned with each other.

[0102] The widths of the first plug structure SC1, the second plug structure SC2, the third plug structure SC3, and the fourth plug structure SC4 are determined by the first contact hole OP1, the second contact hole OP2, the third contact hole OP3, and the fourth contact hole OP4, respectively. In some embodiments, along the first direction D1, the width of the first plug structure SC1 is greater than the width of the third plug structure SC3. In some embodiments, along the first direction D1, the widths of the second plug structure SC2, the third plug structure SC3, and the fourth plug structure SC3 are approximately equal. In some embodiments, the width of the first plug structure SC1 is greater than the widths of the second plug structure SC2, the third plug structure SC3, and the fourth plug structure SC4.

[0103] Please continue to refer to this. Figure 12 , Figure 13 , Figure 14 , Figure 15 and Figure 16 In some embodiments, the semiconductor structure of this invention can be used to fabricate dynamic random access memory (DRAM) including stacked capacitors. For example, after forming contact pads SNP, an insulating material 172 is then formed to cover the substrate 100 and fill the gaps between the contact pads SNP to planarize the surface and ensure electrical isolation between the contact pads SNP. Then, semiconductor manufacturing processes are performed to fabricate a capacitor structure CAP on the contact pads SNP. The capacitor structure CAP includes a bottom electrode BE vertically erected on the contact pads SNP, a capacitor dielectric layer IL covering the sidewalls and top surface of the bottom electrode BE, and a top electrode TE disposed on the capacitor dielectric layer IL and capacitively coupled to the bottom electrode BE. Depending on design requirements, the bottom electrode BE can be configured as follows: Figure 13 , Figure 14 , Figure 15 and Figure 16 The diagram shows a solid columnar structure with a closed bottom. In other embodiments, the bottom electrode BE may be a solid columnar structure, allowing the top electrode TE to be filled into the cavity of the bottom electrode BE, increasing the capacitive coupling area between them. In some embodiments, a support layer 176 may be included between the capacitor structures CAP, extending horizontally between the bottom electrodes BE and directly contacting the sidewalls of the bottom electrodes BE to support each bottom electrode BE. In some embodiments, an etch stop layer 174 may be provided on the insulating material 172, with the bottom of the bottom electrode BE penetrating the etch stop layer 174 to directly contact the contact pad SNP.

[0104] The insulating material 172, etch stop layer 174, support layer 176, and capacitor dielectric layer IL each comprise a dielectric material. The bottom electrode BE and top electrode TE each comprise a conductive material. The bottom electrode BE of the capacitor structure CAP is electrically connected to the active region 102 via contact pad SNP and first plug structure SC1, second plug structure SC2, third plug structure SC3, or fourth plug structure SC4. The storage or release of charge in the capacitor structure CAP is controlled by the gate structure 106 and bit line structure BL to achieve the purpose of storing data.

[0105] In summary, the semiconductor structure and its fabrication method provided by this invention can obtain contact holes of different depths at predetermined locations through the same etching steps, thereby obtaining plug structures of different depths and improving the electrical connection quality between the plug structure and the active region. The semiconductor structure of this invention, when used to manufacture dynamic random access memory (DRAM), can achieve improved device performance.

[0106] The above description is merely a preferred embodiment of this utility model and is not intended to limit the utility model. Various modifications and variations can be made to this utility model by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this utility model should be included within the protection scope of this utility model.

Claims

1. A semiconductor structure, characterized in that, include: The substrate includes multiple active regions; Multiple gate structures extend along a first direction and intersect with the active region, dividing each active region into a middle part and two ends; Multiple bit line structures extend along a second direction and are electrically connected to the middle portion of the active region, wherein the first direction and the second direction are perpendicular to each other, and the bit line structure includes an outer first bit line structure and an inner second bit line structure; and Multiple first plug structures and second plug structures are arranged alternately and at intervals along the second direction outside the first plug structure and are electrically connected to the end, wherein the bottom of the first plug structure is lower than the bottom of the second plug structure.

2. The semiconductor structure according to claim 1, characterized in that, The second plug structure is not lower than the top surface of the middle part of the active region, and the first plug structure is lower than the top surface of the middle part of the active region.

3. The semiconductor structure according to claim 1, characterized in that, It also includes a dummy bit line structure located outside the first bit line structure, wherein the first plug structure and the second plug structure are alternately sandwiched between the first bit line structure and the dummy bit line structure along the second direction.

4. The semiconductor structure according to claim 3, characterized in that, The dummy bit line structure is electrically isolated from each of the active regions.

5. The semiconductor structure according to claim 1, characterized in that, The gate structure includes: Gate dielectric layer; A metal layer is located on the gate dielectric layer; and An insulating cap layer is located on the conductive layer, wherein the bottom of the first plug structure is higher than the top surface of the metal layer.

6. The semiconductor structure according to claim 5, characterized in that, The gate structure further includes a polysilicon layer between the conductive layer and the insulating capping layer, wherein the bottom of the first plug structure is higher than the top surface of the polysilicon layer.

7. The semiconductor structure according to claim 5, characterized in that, The bottom of the second plug structure is lower than the top surface of the insulating cover layer.

8. The semiconductor structure according to claim 1, characterized in that, It also includes multiple third and fourth plug structures, which are alternately arranged along the second direction between the inner side of the first line structure and the second line structure. The third plug structure and the first plug structure are arranged along the first direction, and the fourth plug structure and the second plug structure are arranged along the first direction. The bottom of the third plug structure and the bottom of the fourth plug structure are both higher than the bottom of the first plug structure.

9. The semiconductor structure according to claim 8, characterized in that, The bottoms of the second, third, and fourth plug structures extend into the substrate to the same depth.

10. The semiconductor structure according to claim 1, characterized in that, It also includes multiple capacitor structures, which are located on the first plug structure and the second plug structure, respectively.

11. A semiconductor structure, characterized in that, include: The substrate includes multiple active regions; Multiple gate structures extend along a first direction and intersect with the active region; Multiple spacers are disposed on the gate structure; Multiple first plug structures and second plug structures are alternately arranged between the spacers along a second direction and are electrically connected to the active region, wherein the bottom of the first plug structure is lower than the bottom of the second plug structure.

12. The semiconductor structure according to claim 11, characterized in that, The gate structure includes: Metal layer; A gate dielectric layer, situated between the substrate and the metal layer; and An insulating cap layer is located on the metal layer, wherein the bottom of the first plug structure is higher than the top surface of the metal layer.

13. The semiconductor structure according to claim 12, characterized in that, The gate structure further includes a polysilicon layer between the metal layer and the insulating cap layer, wherein the bottom of the first plug structure is higher than the top surface of the polysilicon layer.

14. The semiconductor structure according to claim 12, characterized in that, The bottom of the second plug structure is lower than the top surface of the insulating cover layer.

15. A semiconductor structure, characterized in that, include: The substrate includes multiple active regions; Multiple gate structures extend along a first direction and intersect with the active region; Multiple bit line structures extend along a second direction and are electrically connected to the active region, wherein the first direction and the second direction are perpendicular to each other, and the bit line structure includes an outer first bit line structure and an inner second bit line structure. At least one first plug structure is disposed on the outside of the first bit line structure; as well as Multiple third plug structures are disposed inside the first bit line structure and between the second bit line structure and arranged with the first plug structure along the first direction, wherein in the cross-sectional view, the bottom of the first plug structure is lower than the bottom of the third plug structure, and the width of the first plug structure is greater than the width of the third plug structure.

16. The semiconductor structure according to claim 15, characterized in that, Also includes: At least one second plug structure is disposed outside the first bit line structure; as well as Multiple fourth plug structures are disposed inside the first bit line structure and between the second bit line structure, and are arranged along the first direction with the second plug structure, wherein in the cross-sectional view, the bottom of the second plug structure is at the same height as the bottom of the fourth plug structure.

17. The semiconductor structure according to claim 15, characterized in that, It also includes a dummy bit line structure located outside the first bit line structure, wherein the first plug structure is sandwiched between the first bit line structure and the dummy bit line structure.

18. The semiconductor structure according to claim 15, characterized in that, The gate structure includes: Gate dielectric layer; A metal layer is located on the gate dielectric layer; and An insulating cap layer is located on the metal layer, wherein the bottom of the first plug structure is higher than the top surface of the metal layer.

19. The semiconductor structure according to claim 18, characterized in that, The gate structure further includes a polysilicon layer between the metal layer and the insulating cap layer, wherein the bottom of the first plug structure is higher than the top surface of the polysilicon layer.

20. The semiconductor structure according to claim 18, characterized in that, The bottom of the third plug structure is lower than the top surface of the insulating cover layer.

21. A semiconductor structure, characterized in that, include: The substrate includes multiple active regions; Multiple gate structures extend along a first direction and intersect with the active region; Multiple bitline structures, extending along the second direction; At least one first plug structure is disposed adjacent to the bit line structure, and the bottom of the first plug structure is lower than the bottom of the bit line structure.

22. The semiconductor structure according to claim 21, characterized in that, The bit line structure includes a semiconductor layer that is in direct contact with the active region, and the bottom of the first plug structure is lower than the bottom of the semiconductor layer.

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