transistor region

Abstract

The present application relates to a transistor region. The transistor region includes: a substrate; a first region provided in the substrate; a first sub-region and a second sub-region provided in the substrate; a gate insulating layer provided on the substrate; and an interlayer insulating layer provided on the gate insulating layer. A channel length between the first region and the second sub-region is longer than a channel length between the first region and the first sub-region.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0056219, filed on April 26, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to transistor regions, and more specifically, to transistor regions including doped regions having subregions. Background Technology

[0004] Organic light-emitting display devices are self-emissive display devices that may include a hole injection electrode, an electron injection electrode, and an organic light-emitting layer formed between the hole injection electrode and the electron injection electrode. Organic light-emitting display devices can emit light simultaneously as holes injected from the hole injection electrode and electrons injected from the electron injection electrode recombine in the organic light-emitting layer. Organic light-emitting display devices can exhibit high-quality characteristics such as low power consumption, high brightness, and high response speed.

[0005] Organic light-emitting display devices may include thin-film transistors to control the operation of each pixel or to transmit electrical signals from a driver to each pixel. Utility Model Content

[0006] The implementation provides a transistor region capable of compensating for degradation caused by ultraviolet exposure.

[0007] According to an aspect of this disclosure, a transistor region is provided, the transistor region comprising: a substrate; a first region disposed in the substrate; a first sub-region and a second sub-region disposed in the substrate; a gate insulating layer disposed on the substrate; and an interlayer insulating layer disposed on the gate insulating layer, wherein the channel length between the first region and the second sub-region is longer than the channel length between the first region and the first sub-region.

[0008] The transistor region may also include a well disposed in the substrate, wherein the first region, the first sub-region, and the second sub-region may be disposed in the well and spaced apart from each other.

[0009] The well can be a channel region, and the transistor region can also include a gate electrode on the gate insulating layer and overlapping the channel region.

[0010] The transistor region may further include a first conductive pattern disposed on the interlayer insulating layer. The first conductive pattern may be electrically connected to the first region through a first connection portion passing through the gate insulating layer and the interlayer insulating layer.

[0011] The transistor region may also include a second conductive pattern disposed on the interlayer insulating layer. The second conductive pattern may be electrically connected to one of the first sub-region and the second sub-region via a second connection portion passing through the gate insulating layer and the interlayer insulating layer.

[0012] The amount of impurities in the second sub-region can be greater than the amount of impurities in the first sub-region.

[0013] The first region can be the source region, and the first and second sub-regions can correspond to the leaked regions.

[0014] The first region can be the leak region, and the first and second sub-regions can correspond to the source region.

[0015] The second sub-region can be positioned relative to the first sub-region in a first direction, and the first region can be positioned relative to the first sub-region in a second direction opposite to the first direction.

[0016] According to another aspect of this disclosure, a transistor region is provided, the transistor region comprising: a substrate; a first doped region disposed in the substrate; a first doped sub-region and a second doped sub-region disposed in the substrate; a gate insulating layer disposed on the substrate; and an interlayer insulating layer disposed on the gate insulating layer, wherein the channel length between the first doped region and the second doped sub-region is different from the channel length between the first doped region and the first doped sub-region.

[0017] The transistor region may also include a well disposed in the substrate, wherein the first doped region, the first doped sub-region, and the second doped sub-region may be disposed in the well and spaced apart from each other.

[0018] A trap can be a channel region.

[0019] The transistor region may further include a first conductive pattern disposed on the interlayer insulating layer. The first conductive pattern may be electrically connected to the first doped region through a first connection portion passing through the gate insulating layer and the interlayer insulating layer.

[0020] The transistor region may further include a second conductive pattern disposed on the interlayer insulating layer. The second conductive pattern may be electrically connected to one of the first doped region and the second doped region via a second connection portion passing through the gate insulating layer and the interlayer insulating layer.

[0021] The amount of impurities in the second doped sub-region can be greater than the amount of impurities in the first doped sub-region.

[0022] The first doped region can correspond to the source region, and the first doped sub-region and the second doped sub-region can correspond to the drain region.

[0023] The first doped region can correspond to the drain region, and the first doped sub-region and the second doped sub-region can correspond to the source region.

[0024] The second doped sub-region may be disposed in a first direction relative to the first doped sub-region, and the first doped region may be disposed in a second direction opposite to the first doped sub-region relative to the first doped sub-region.

[0025] According to another aspect of this disclosure, a transistor region is provided, comprising: a substrate; a well disposed in the substrate; a first region disposed in the well; a first sub-region and a second sub-region disposed in the well, wherein the first region, the first sub-region and the second sub-region are spaced apart from each other in the well, and wherein the amount of impurities in the first sub-region is different from the amount of impurities in the second sub-region; a gate insulating layer disposed on the substrate; and an interlayer insulating layer disposed on the gate insulating layer, wherein the second sub-region is disposed in a first direction relative to the first sub-region, and the first region is disposed in a second direction opposite to the first direction relative to the first sub-region.

[0026] The transistor region may further include: a first conductive pattern disposed on an interlayer insulating layer; and a second conductive pattern disposed on an interlayer insulating layer, wherein the first conductive pattern is electrically connected to the first region through a first connection portion passing through the gate insulating layer and the interlayer insulating layer, and wherein the second conductive pattern is electrically connected to one of the first sub-region and the second sub-region through a second connection portion passing through the gate insulating layer and the interlayer insulating layer. Attached Figure Description

[0027] The above and other features of this disclosure will become more apparent from a detailed description of embodiments thereof with reference to the accompanying drawings.

[0028] Figure 1 This is a block diagram illustrating an implementation of the display device.

[0029] Figure 2 It is shown Figure 1 A plan view of an embodiment of the display panel shown.

[0030] Figure 3 It is along Figure 2 The sectional view shown is taken by line I-I'.

[0031] Figure 4 It is shown Figure 3 A view of the transistor region shown.

[0032] Figure 5 It is shown Figure 3 A view of an embodiment of the transistor region shown.

[0033] Figure 6It is shown Figure 3 A view of an embodiment of the transistor region shown.

[0034] Figure 7 This is a block diagram illustrating an electronic device according to an embodiment of the present disclosure.

[0035] Figure 8 It is shown Figure 7 A schematic diagram illustrating an example of an electronic device implemented as a smartphone.

[0036] Figure 9 It is shown Figure 7 The electronic device shown is an example of a tablet computer. Detailed Implementation

[0037] In the following description, embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. Parts unrelated to the present disclosure may be omitted from the description. Furthermore, the present disclosure is not limited to the exemplary embodiments described herein, but may be implemented in various different forms. Rather, the exemplary embodiments described herein are provided to thoroughly and completely describe the disclosure and to fully convey the scope of this specification to those skilled in the art.

[0038] Throughout this specification, when an element is referred to as “connected” or “coupled” to another element, the element may be directly connected or directly coupled to the other element, or the element may be indirectly connected or indirectly coupled to the other element with one or more intermediary elements inserted therebetween. The technical terms used herein may be understood in the context of various embodiments and may not be limited to the specific description.

[0039] It will be understood that when a component “comprises” an element, it should be understood that the component may not exclude another element and may also include another element. It will be understood that, for the purposes of this disclosure, “at least one of X, Y, and Z” can be interpreted as only X, only Y, only Z, or any combination of two or more items of X, Y, and Z (e.g., XYZ, XYY, YZ, ZZ). Similarly, for the purposes of this disclosure, “at least one selected from the group consisting of X, Y, and Z” can be interpreted as only X, only Y, only Z, or any combination of two or more items of X, Y, and Z (e.g., XYZ, XYY, YZ, ZZ).

[0040] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms can be used to distinguish one element from another. Therefore, without departing from the teachings of this disclosure, the “first” element discussed herein may also be referred to as the “second” element.

[0041] For ease of description, spatially relative terms such as “below” and “above” may be used herein to describe the relationship between one element and another as shown in the figures. It will be understood that the spatially relative terms and the configurations shown may be intended to include different orientations of the device in use or operation, in addition to those described herein and depicted in the figures. For example, if the device in the figures is flipped, an element described as “below” or “under” other elements or features will consequently be oriented “above” other elements or features. Thus, the exemplary term “above” can include both above and below orientations. The device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein should be interpreted accordingly.

[0042] Furthermore, embodiments of this disclosure can be described herein with reference to the schematic diagrams (and intermediate structures) of this disclosure, such that variations in the illustrated shapes can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of this disclosure should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations caused by, for example, manufacturing techniques. The regions shown in the figures are schematic in nature, and their shapes may not represent the actual shapes of regions of the device, and do not limit the scope of this disclosure.

[0043] Exemplary embodiments will now be described more fully below with reference to the accompanying drawings. However, aspects of the drawings may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art.

[0044] In the accompanying drawings, dimensions may be exaggerated for clarity. It will be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or there may be one or more intervening elements. The same reference numerals always denote the same elements.

[0045] Figure 1 This is a block diagram illustrating an implementation of the display device.

[0046] refer to Figure 1 The display device 100 may include a display panel 110, a gate driver 120, a data driver 130, a voltage generator 140, and a controller 150.

[0047] The display panel 110 may include sub-pixels SP. Sub-pixels SP can be connected to gate driver 120. Sub-pixels SP can be connected to gate driver 120 via first gate line GL1 to the m-th gate line GLm. Sub-pixels SP can be connected to data driver 130. Sub-pixels SP can be connected to data driver 130 via first data line DL1 to the n-th data line DLn.

[0048] Each of the subpixels SP can include at least one light-emitting element configured to generate light. Therefore, each of the subpixels SP can produce light of a specific color, such as red, green, blue, cyan, magenta, or yellow. Two or more subpixels SP can constitute a pixel PXL. For example, three subpixels SP can constitute a pixel PXL. Figure 1 The pixel PXL shown in the image.

[0049] Gate driver 120 can be connected to sub-pixels SP arranged in the row direction via first gate lines GL1 to m-th gate lines GLm. Gate driver 120 can output gate signals to first gate lines GL1 to m-th gate lines GLm in response to gate control signal GCS. In an embodiment, gate control signal GCS may include a start signal indicating the start of each frame and a horizontal synchronization signal for outputting gate signals in timing synchronization with applied data signals.

[0050] The display device 100 may include first light-emitting control lines EL1 to m-th light-emitting control lines ELm. In one embodiment, the first light-emitting control lines EL1 to m-th light-emitting control lines ELm may be connected to sub-pixels SP in the row direction. The gate driver 120 may include an emission control driver configured to control the first light-emitting control lines EL1 to m-th light-emitting control lines ELm, and the emission control driver may operate under the control of the controller 150.

[0051] The gate driver 120 may be disposed on one side of the display panel 110. However, the implementation is not limited to this. For example, the gate driver 120 may be divided into two or more drivers that can be physically and / or logically separated, and these drivers may be disposed on a first side of the display panel 110 and a second side of the display panel 110 that may be opposite to the first side. Thus, in some embodiments, the gate driver 120 may be disposed in various forms at the periphery of the display panel 110.

[0052] Data driver 130 can be connected to sub-pixels SP arranged in the column direction via first data lines DL1 to nth data lines DLn. Data driver 130 can receive image data DATA and data control signal DCS from controller 150. Data driver 130 can operate in response to data control signal DCS. In an embodiment, data control signal DCS may include one or more signals. For example, data control signal DCS may include source start pulse, source shift clock, and source output enable signal.

[0053] The data driver 130 can apply a data signal corresponding to the image data DATA to the first data lines DL1 to the nth data lines DLn using a voltage from the voltage generator 140. For example, the data driver 130 can apply a data signal having a grayscale voltage corresponding to the image data DATA to the first data lines DL1 to the nth data lines DLn using a voltage from the voltage generator 140. When a gate signal is applied to each of the first gate lines GL1 to the mth gate line GLm, the data signal corresponding to the image data DATA can be applied to the data lines DL1 to DLm. Therefore, the corresponding sub-pixel SP can generate light corresponding to the data signal. Thus, an image can be displayed on the display panel 110.

[0054] In one embodiment, the gate driver 120 and the data driver 130 may include complementary metal-oxide-semiconductor (CMOS) circuit elements.

[0055] Voltage generator 140 can operate in response to a voltage control signal (VCS) from controller 150. Voltage generator 140 can be configured to generate multiple voltages and provide the generated voltages to components of display device 100. For example, voltage generator 140 can be configured to generate multiple voltages by receiving an input voltage from outside display device 100, adjusting the received voltage, and regulating the adjusted voltage.

[0056] Voltage generator 140 can generate a first power voltage VDD and a second power voltage VSS. The generated first power voltage VDD and second power voltage VSS can be provided to sub-pixels SP. The first power voltage VDD can have a relatively high voltage level, and the second power voltage VSS can have a lower voltage level than the first power voltage VDD. In some embodiments, the first power voltage VDD or the second power voltage VSS can be provided by an external device of display device 100.

[0057] Voltage generator 140 can generate other voltages. For example, voltage generator 140 can generate an initialization voltage applied to the sub-pixel SP. For example, in a sensing operation that senses the electrical characteristics of the transistor and / or light-emitting element of the sub-pixel SP, a predetermined reference voltage can be applied to the first data line DL1 to the nth data line DLn, and voltage generator 140 can generate the reference voltage.

[0058] The controller 150 can control the operation of the display device 100. The controller 150 can receive input image data IMG and a control signal CTRL for controlling its display from an external source. The controller 150 can provide a gate control signal GCS, a data control signal DCS, and a voltage control signal VCS in response to the control signal CTRL.

[0059] Controller 150 can process input image data IMG. For example, the input image data IMG can be processed to fit display device 100 or display panel 110. The input image data IMG can be output as image data DATA by controller 150. For example, the input image data IMG can be converted to fit display device 100 or display panel 110 and output as image data DATA. In one embodiment, controller 150 can align the input image data IMG row by row to fit sub-pixels SP, thereby outputting image data DATA. In some embodiments, the input image data IMG can be output as image data DATA without being processed by controller 150.

[0060] Two or more of the components—data driver 130, voltage generator 140, and controller 150—can be mounted on an integrated circuit. For example... Figure 1 As shown, the data driver 130, voltage generator 140, and controller 150 may be included in a driver integrated circuit (DIC). The data driver 130, voltage generator 140, and controller 150 may be functionally separated components within the driver integrated circuit (DIC). In some embodiments, at least one of the data driver 130, voltage generator 140, and controller 150 may be configured as a component distinct from the driver integrated circuit (DIC).

[0061] Display device 100 may include at least one temperature sensor 160. Temperature sensor 160 may be configured to sense temperature and generate temperature data TEP indicating the sensed temperature. Temperature sensor 160 may be configured to sense the temperature at the periphery of display device 100 and generate temperature data TEP indicating the sensed temperature. In an embodiment, temperature sensor 160 may be positioned adjacent to display panel 110 and / or driver integrated circuit DIC.

[0062] The controller 150 can control various operations of the display device 100 in response to temperature data TEP. In one embodiment, the controller 150 can adjust the brightness of the image output from the display panel 110 in response to the temperature data TEP. For example, the controller 150 can control components such as the data driver 130 and / or the voltage generator 140 to adjust the data signal and the first power voltage VDD and the second power voltage VSS.

[0063] Figure 2 It is shown Figure 1 A plan view of an embodiment of the display panel shown.

[0064] refer to Figure 2 , Figure 1The embodiment of the display panel 110 shown may include a display area DA and a non-display area NDA. The display panel 110 can display images through the display area DA. The non-display area NDA may be located at the periphery of the display area DA.

[0065] The display panel 110 may include a substrate SUB, sub-pixels SP, and pads PD.

[0066] In some embodiments, when the display panel 110 is used as a display screen, the display panel 110 may be positioned close to the user's eyes. For example, when the display panel 110 is used as a display screen for a head-mounted display (HMD), virtual reality (VR) device, mixed reality (MR) device, or augmented reality (AR) device, the display panel 110 may be positioned close to the user's eyes. In implementations where the display panel 110 can be positioned close to the user's eyes, the integration density of the sub-pixels SP can be relatively high to maintain the image quality of the displayed image. To support the relatively high integration density of the sub-pixels SP, the substrate SUB may be configured as a silicon substrate. The sub-pixels SP may be formed on the substrate SUB, which is a silicon substrate. A display device 100 including sub-pixels SP formed on a substrate SUB configured as a silicon substrate (see [link to relevant documentation]). Figure 1 It can be named an OLED on silicon (OLEDoS) display device.

[0067] Subpixels SP can be disposed on the substrate SUB in the display area DA. The subpixels SP can be arranged in a matrix along a first direction DR1 and a second direction DR2 intersecting the first direction DR1. However, the implementation is not limited to this. For example, the subpixels SP can be arranged in a zigzag pattern along the first direction DR1 and the second direction DR2. For example, the subpixels SP can be configured as follows: The first direction DR1 can be the row direction, and the second direction DR2 can be the column direction. Furthermore, the third direction DR3 can be the thickness direction of the display panel 110.

[0068] Two or more subpixels in subpixel SP can form pixel PXL.

[0069] Components for controlling sub-pixels SP can be disposed on the substrate SUB in the non-display area NDA. For example, lines connected to the sub-pixels SP (such as...) Figure 1 The first gate line GL1 to the m-th gate line GLm and the first data line DL1 to the n-th data line DLn shown can be set in the non-display area NDA.

[0070] Gate driver 120, data driver 130, voltage generator 140, controller 150, and temperature sensor 160 (see also...) Figure 1At least one of them can be integrated into the non-display area NDA of the display panel 110. In an embodiment, Figure 1 The gate driver 120 shown can be mounted on the display panel 110 and can be located in the non-display area NDA. In some embodiments, the gate driver 120 can be implemented as an integrated circuit separate from the display panel 110. In one embodiment, the temperature sensor 160 can be located in the non-display area NDA and can sense the temperature of the display panel 110.

[0071] The pad PD can be disposed on the substrate SUB in the non-display area NDA. The pad PD can be electrically connected to the sub-pixel SP via wirelines. For example, the pad PD can be connected to the sub-pixel SP via the first data line DL1 to the nth data line DLn.

[0072] The pad PD can connect the display panel 110 to the display device 100 (see...) Figure 1 Other component interfaces. In the embodiment, voltages and signals that can be used for the operation of components included in the display panel 110 can be transmitted from the pad PD via Figure 1 The driver integrated circuit (DIC) shown is provided. For example, the first data line DL1 to the nth data line DLn can be connected to the driver integrated circuit (DIC) via the pad PD. For example, the first power voltage VDD and the second power voltage VSS can be received from the driver integrated circuit (DIC) via the pad PD. When the gate driver 120 is mounted in the display panel 110, the gate control signal GCS can be transmitted from the driver integrated circuit (DIC) to the gate driver 120 via the pad PD.

[0073] In this implementation, the circuit board can be electrically connected to the pads (PD). For example, the circuit board can be electrically connected to the pads (PD) using a conductive adhesive component such as an anisotropic conductive film. The circuit board can be a flexible printed circuit board (FPCB) or a flexible film that can be formed from a flexible material. The driver integrated circuit (DIC) can be mounted on the circuit board and can be electrically connected to the pads (PD).

[0074] In this implementation, the display area DA can have any of a variety of shapes. The display area DA can have a closed-loop shape including linear edges and / or curved edges. For example, the display area DA can have shapes such as polygons, circles, semicircles, and ellipses.

[0075] In some embodiments, the display panel 110 may have a flat display surface. In some embodiments, the display panel 110 may have at least a partially rounded display surface. In some embodiments, the display panel 110 may be flexible. For example, the display panel 110 may be at least partially bendable, foldable, or rollable. The display panel 110 and / or the substrate SUB may comprise a flexible material.

[0076] Figure 3 It is along Figure 2 The sectional view shown is taken by line I-I'.

[0077] refer to Figure 3 It can provide a substrate (SUB) and a pixel circuit layer (PCL). The pixel circuit layer (PCL) can be disposed on the substrate (SUB).

[0078] The substrate SUB may include a silicon wafer substrate formed using semiconductor processes. For example, the substrate SUB may include silicon, germanium, and / or silicon-germanium.

[0079] The pixel circuit layer (PCL) can be disposed on the substrate (SUB). The substrate (SUB) and the pixel circuit layer (PCL) can include circuit elements for each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. Each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can include one or more transistors. For example, the substrate (SUB) and the pixel circuit layer (PCL) can include transistor T_SP1 for the first sub-pixel SP1, transistor T_SP2 for the second sub-pixel SP2, and transistor T_SP3 for the third sub-pixel SP3. Transistor T_SP1 for the first sub-pixel SP1, transistor T_SP2 for the second sub-pixel SP2, and transistor T_SP3 for the third sub-pixel SP3 can be sub-pixels SP of pixel PXL (see [link to documentation]). Figure 2 (Transistor). In Figure 3 In the diagram, for clarity and brevity, one transistor for each sub-pixel SP is shown, and other circuit elements may be omitted.

[0080] The transistors of sub-pixels SP of pixel PXL (e.g., transistor T_SP1 of first sub-pixel SP1, transistor T_SP2 of second sub-pixel SP2, and transistor T_SP3 of third sub-pixel SP3) may each include a doped region. The doped region may be the source / drain region of the transistor.

[0081] The transistor T_SP1 of the first sub-pixel SP1 can each include a first region SCP1, a second region SCP2, and a gate electrode GE. (See reference) Figure 3 The first region SCP1 and the second region SCP2 can be doped regions of transistor T_SP1.

[0082] First region SCP1 and second region SCP2 can be disposed in substrate SUB. Well WL can be disposed in substrate SUB. Well WL can be formed by ion implantation. First region SCP1 and second region SCP2 can be disposed in well WL and can be spaced apart from each other. The region between first region SCP1 and second region SCP2 in well WL can be defined as a channel region. In one embodiment, first region SCP1 can be a source region and second region SCP2 can be a drain region. However, the embodiment is not limited to this; for example, in some embodiments, first region SCP1 can be a drain region and second region SCP2 can be a source region.

[0083] The gate electrode GE may overlap with the channel region between the first region SCP1 and the second region SCP2, and may be disposed in the pixel circuit layer PCL. The gate electrode GE may be spaced apart from the well WL or the channel region by an insulating layer such as the gate insulating layer GI. The gate electrode GE may include a conductive material.

[0084] The multiple layers included in the pixel circuit layer PCL may include insulating layers and conductive patterns disposed between the insulating layers, and the conductive patterns may include a first conductive pattern CP1 and a second conductive pattern CP2. The first conductive pattern CP1 may be electrically connected to a first region SCP1 through a first connection portion RC1 passing through one or more insulating layers. The second conductive pattern CP2 may be electrically connected to a second region SCP2 through a second connection portion RC2 passing through one or more insulating layers.

[0085] Since the gate electrode GE and the first conductive pattern CP1 and the second conductive pattern CP2 can be connected to other circuit elements and / or lines, the transistor T_SP1 of the first sub-pixel SP1 can be set to any one of the transistors of the first sub-pixel SP1.

[0086] Each of the transistors T_SP2 of the second sub-pixel SP2 and T_SP3 of the third sub-pixel SP3 can be configured similarly to the transistor T_SP1 of the first sub-pixel SP1.

[0087] Thus, the substrate SUB and / or pixel circuit layer PCL may include circuit elements for each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3.

[0088] A via layer (VIAL) can be disposed on the pixel circuit layer (PCL). The via layer (VIAL) can cover the pixel circuit layer (PCL). The via layer (VIAL) can have a completely flat surface. The via layer (VIAL) can be configured to flatten step differences on the pixel circuit layer (PCL). The via layer (VIAL) can include silicon oxide (SiO2). x ), silicon nitride (SiN)x It may contain at least one of silicon carbide (SiCN) and silicon nitride (SiCN), but the implementation is not limited thereto.

[0089] The light-emitting element layer (LDL) can be disposed on the via layer (VIAL). The LDL may include a first reflective electrode (RE1), a second reflective electrode (RE2), and a third reflective electrode (RE3), a planarization layer (PLNL), a first anode electrode (AE1), a second anode electrode (AE2), and a third anode electrode (AE3), a pixel definition layer (PDL), a light-emitting structure (EMS), and a cathode electrode (CE).

[0090] The first reflective electrode RE1 to the third reflective electrode RE3 can be disposed on the via layer VIAL and respectively disposed in the first sub-pixel SP1 to the third sub-pixel SP3. Each of the first reflective electrode RE1 to the third reflective electrode RE3 can contact a circuit element disposed in the pixel circuit layer PCL through a via passing through the via layer VIAL.

[0091] The first reflecting electrodes RE1 to the third reflecting electrodes RE3 can be used as total reflection mirrors, which can reflect light emitted from the light-emitting structure EMS toward the display surface (or the cover window CW). The first reflecting electrodes RE1 to the third reflecting electrodes RE3 can include metallic materials suitable for reflecting light. The first reflecting electrodes RE1 to the third reflecting electrodes RE3 can include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), and titanium (Ti), or an alloy of two or more materials selected therefrom, but the embodiments are not limited thereto.

[0092] In one embodiment, a connecting electrode may be disposed on the bottom of each of the first reflective electrodes RE1 to the third reflective electrodes RE3. The connecting electrode can improve the electrical connection characteristics between the respective reflective electrode and the circuit elements of the pixel circuit layer PCL. The connecting electrode may have a multilayer structure. The multilayer structure may include titanium (Ti), titanium nitride (TiN), or tantalum nitride (TaN), but the embodiment is not limited thereto. In another embodiment, the respective reflective electrode may be disposed between multiple layers of the connecting electrode.

[0093] A buffer pattern BFP can be disposed on the bottom surface of at least one of the first reflective electrodes RE1 to the third reflective electrode RE3. For example, the buffer pattern BFP can be disposed on the via layer VIAL. The buffer pattern BFP can include inorganic materials such as silicon carbide, but the implementation is not limited thereto. The height on the third-direction DR3 of the corresponding reflective electrode can be controlled according to the height of the buffer pattern BFP. For example, the buffer pattern BFP can be disposed between the first reflective electrode RE1 and the via layer VIAL to control the height of the first reflective electrode RE1.

[0094] The first reflecting electrodes RE1 to the third reflecting electrodes RE3 can be used as total reflection mirrors, and the cathode electrode CE can be used as a partial reflection mirror. Light emitted from the light-emitting layer of the light-emitting structure EMS can be amplified by at least partially reciprocating between the corresponding reflecting electrodes and the cathode electrode CE, and the amplified light can be output through the cathode electrode CE. Thus, the distance between each reflecting electrode and the cathode electrode CE can be understood as the resonant distance of the light emitted from the light-emitting layer of the corresponding light-emitting structure EMS.

[0095] By using a buffer pattern (BFP), the first sub-pixel SP1 can have a shorter resonant distance than the other sub-pixel. Light within a specific wavelength range (e.g., red) can be effectively and efficiently amplified by adjusting the resonant distance. Therefore, the first sub-pixel SP1 can effectively and efficiently output light within the corresponding wavelength range.

[0096] refer to Figure 3 The buffer pattern BFP can be set in the first sub-pixel SP1 and can be omitted from the second sub-pixel SP2 and the third sub-pixel SP3. However, the implementation is not limited to this. The buffer pattern BFP can be set in at least one of the second sub-pixel SP2 and the third sub-pixel SP3. The buffer pattern BFP can adjust the resonant distance of at least one of the second sub-pixel SP2 and the third sub-pixel SP3. For example, the first sub-pixel SP1 to the third sub-pixel SP3 can correspond to red, green and blue, respectively. The distance between the first reflective electrode RE1 and the cathode electrode CE can be shorter than the distance between the second reflective electrode RE2 and the cathode electrode CE, and the distance between the second reflective electrode RE2 and the cathode electrode CE can be shorter than the distance between the third reflective electrode RE3 and the cathode electrode CE.

[0097] A planarization layer PLNL can be disposed on the via layer VIAL and the first reflective electrodes RE1 to the third reflective electrodes RE3. The planarization layer PLNL can planarize the step difference between the first reflective electrodes RE1 to the third reflective electrodes RE3 and the via layer VIAL, and can have a flat upper surface. In some embodiments, the planarization layer PLNL can be omitted.

[0098] First anode electrodes AE1 to third anode electrodes AE3, respectively overlapping with first reflective electrodes RE1 to third reflective electrodes RE3, can be disposed on the planarization layer PLNL. First anode electrodes AE1 to third anode electrodes AE3 can be electrically connected to first reflective electrodes RE1 to third reflective electrodes RE3, respectively. First anode electrode AE1 can be electrically connected to first reflective electrode RE1 through a first via VIA1 passing through the planarization layer PLNL. Second anode electrode AE2 can be electrically connected to second reflective electrode RE2 through a second via VIA2 passing through the planarization layer PLNL. Third anode electrode AE3 can be electrically connected to third reflective electrode RE3 through a third via VIA3 passing through the planarization layer PLNL.

[0099] In the embodiment, the first anode electrode AE1 to the third anode electrode AE3 may include at least one of a transparent conductive material, such as indium tin oxide (ITO), indium zinc oxide (IZO), or zinc oxide (ZnO). x The materials used for the first anode electrode AE1 to the third anode electrode AE3 are indium gallium zinc oxide (IGZO) or indium tin zinc oxide (ITZO), but the embodiments are not limited thereto. However, the materials used for the first anode electrode AE1 to the third anode electrode AE3 are not limited thereto. For example, the first anode electrode AE1 to the third anode electrode AE3 may include titanium nitride.

[0100] In this embodiment, an insulating layer may also be included for adjusting the height of at least one of the first anode electrodes AE1 to the third anode electrodes AE3. The insulating layer may be disposed between at least one of the first anode electrodes AE1 to the third anode electrodes AE3 and a corresponding reflective electrode. The planarization layer PLNL and / or the buffer pattern BFP may be omitted. For example, the first sub-pixels SP1 to the third sub-pixels SP3 may correspond to red, green, and blue, respectively; the distance between the first anode electrode AE1 and the cathode electrode CE may be shorter than the distance between the second anode electrode AE2 and the cathode electrode CE; and the distance between the second anode electrode AE2 and the cathode electrode CE may be shorter than the distance between the third anode electrode AE3 and the cathode electrode CE. A pixel defining layer PDL may be disposed on a portion of the first anode electrodes AE1 to the third anode electrodes AE3 and the planarization layer PLNL. The pixel defining layer PDL may include an opening OP exposing a portion of each of the first anode electrodes AE1 to the third anode electrodes AE3. The opening OP of the pixel defining layer PDL may define the emission region of each of the first sub-pixels SP1 to the third sub-pixels SP3.

[0101] In one embodiment, the pixel defining layer (PDL) may include a plurality of inorganic insulating layers. Each of the plurality of inorganic insulating layers may include silicon oxide (SiO2). x ) and silicon nitride (SiN) xAt least one of the following. For example, the pixel defining layer (PDL) may include a first to a third inorganic insulating layer that can be sequentially stacked. The first to third inorganic insulating layers may each include silicon nitride, silicon oxide, and silicon nitride, respectively. However, the implementation is not limited thereto. The first to third inorganic insulating layers may have stepped portions in the region adjacent to the opening (OP).

[0102] The separation region SPR can be set in the boundary region BDA between adjacent sub-pixels. In other words, the separation region SPR can be set in... Figure 2 The boundary regions between sub-pixels SP shown in the diagram.

[0103] The split-part splitting (SPR) can cause the formation of a discontinuity in the light-emitting structure (EMS) within the boundary region BDA. For example, the light-emitting structure (EMS) can be cut or bent within the boundary region BDA through the split-part splitting (SPR).

[0104] The separation segment SPR can be disposed in or on the pixel-defining layer PDL. The pixel-defining layer PDL may include one or more trenches (e.g., a first trench TRCH1 and a second trench TRCH2) as the separation segment SPR. In an embodiment, as... Figure 3 As shown, one or more of the first trench TRCH1 and the second trench TRCH2 can pass through the pixel defining layer PDL and can partially pass through the planarization layer PLNL. In some embodiments, one or more of the first trench TRCH1 and the second trench TRCH2 can pass through the pixel defining layer PDL and the planarization layer PLNL, and can partially pass through the via layer VIAL. In some embodiments, one or more of the first trench TRCH1 and the second trench TRCH2 can at least partially pass through the planarization layer PLNL and / or the via layer VIAL, and a portion of the pixel defining layer PDL can be disposed in one or more of the first trench TRCH1 and the second trench TRCH2.

[0105] exist Figure 3 The diagram illustrates that a first trench TRCH1 and a second trench TRCH2 can be disposed in the boundary region BDA. However, the implementation is not limited to this. For example, the pixel defining layer PDL can include one trench in the boundary region BDA. Alternatively, the pixel defining layer PDL can include three or more trenches in the boundary region BDA.

[0106] In some cases, discontinuities (such as the first gap VD1 and the second gap VD2) can be formed in the boundary region BDA within the light-emitting structure EMS. For example, the first gap VD1 and the second gap VD2 can be formed in the first trench TRCH1 and the second trench TRCH2. The first gap VD1 and the second gap VD2 can be formed in a portion of the first trench TRCH1 and the second trench TRCH2. One or more layers among the multiple layers stacked in the light-emitting structure EMS can be cut or bent at the first gap VD1 and the second gap VD2. For example, at least one charge-generating layer included in the light-emitting structure EMS can be cut through the first gap VD1 and the second gap VD2. Thus, a portion of the light-emitting structure EMS included in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can be at least partially separated from each other.

[0107] exist Figure 3 The diagram illustrates that a first gap VD1 and a second gap VD2 can be formed in the boundary region BDA within the light-emitting structure EMS. However, this is merely illustrative, and the implementation is not limited thereto. For example, a concave valley can be formed in the boundary region BDA within the light-emitting structure EMS. The discontinuities formed in the light-emitting structure EMS can be varied depending on the shape of the first trench TRCH1 and the second trench TRCH2.

[0108] In this embodiment, the light-emitting structure EMS can be formed by processes such as vacuum deposition or inkjet printing. The same material as the light-emitting structure EMS can be disposed on the bottom surface adjacent to the via layer VIAL in the first trench TRCH1 and the second trench TRCH2.

[0109] The separation section SPR can be modified in various ways. The separation section SPR can be modified in various ways so that the light-emitting structure EMS can have discontinuities in the boundary region BDA. In an embodiment, without the first trench TRCH1 and the second trench TRCH2, an inorganic insulating pattern additionally stacked on the pixel defining layer PDL can be provided in the boundary region BDA. The width of the inorganic insulating pattern at the uppermost portion of the additionally stacked inorganic insulating patterns can be greater than the width of the inorganic insulating pattern directly below the inorganic insulating pattern at the uppermost portion. For example, in the boundary region BDA, the first to third inorganic insulating patterns can be sequentially stacked from the pixel defining layer PDL, and the third inorganic insulating pattern at the uppermost portion can have a width greater than the width of the second inorganic insulating layer. For example, the pixel defining layer PDL can have segments with a "T" shape or an "I" shape in the boundary region BDA, but this disclosure is not limited to this. Depending on the shape of the pixel defining layer PDL, multiple layers included in the light-emitting structure EMS can be partially cut or bent in the boundary region BDA.

[0110] The light-emitting structure EMS can be disposed on the anode electrode AE ​​exposed by the opening OP of the pixel-defining layer PDL. The light-emitting structure EMS can be disposed within the opening OP of the pixel-defining layer PDL. The light-emitting structure EMS can fill the opening OP of the pixel-defining layer PDL and can be completely disposed throughout the entire first sub-pixel SP1 to the third sub-pixel SP3. As described herein, the light-emitting structure EMS can be at least partially cut or bent in the boundary region BDA by the separation portion SPR. Therefore, during the operation of the display panel 110, the current leakage from each of the first sub-pixel SP1 to the third sub-pixel SP3 through the layer included in the light-emitting structure EMS to its adjacent sub-pixel can be reduced. Therefore, the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 can operate with relatively high reliability.

[0111] The cathode electrode CE can be disposed on the light-emitting structure EMS. The cathode electrode CE can be commonly disposed in the first sub-pixel SP1 to the third sub-pixel SP3. The cathode electrode CE can function as a semi-reflective mirror, which allows light emitted from the light-emitting structure EMS to be partially transmitted through and partially reflected from it.

[0112] A first light-emitting element LD1 can be formed by a first anode electrode AE1, a portion of the light-emitting structure EMS overlapping with the first anode electrode AE1, and a portion of the cathode electrode CE overlapping with the first anode electrode AE1. A second light-emitting element LD2 can be formed by a second anode electrode AE2, a portion of the light-emitting structure EMS overlapping with the second anode electrode AE2, and a portion of the cathode electrode CE overlapping with the second anode electrode AE2. A third light-emitting element LD3 can be formed by a third anode electrode AE3, a portion of the light-emitting structure EMS overlapping with the third anode electrode AE3, and a portion of the cathode electrode CE overlapping with the third anode electrode AE3.

[0113] The encapsulation layer TFE can be disposed on the cathode electrode CE. The encapsulation layer TFE can suppress or prevent oxygen and / or moisture from penetrating into the light-emitting element layer LDL.

[0114] An optical functional layer (OFL) can be disposed on the encapsulation layer TFE. In one embodiment, the optical functional layer OFL can be attached to the encapsulation layer TFE via an adhesive layer (APL). For example, the optical functional layer OFL can be manufactured separately for attachment to the encapsulation layer TFE via the adhesive layer APL. The adhesive layer APL can further perform the function of protecting the underlying layer including the encapsulation layer TFE.

[0115] The optical functional layer (OFL) may include a color filter layer (CFL) and a lens array (LA). The color filter layer (CFL) may include a first color filter (CF1), a second color filter (CF2), and a third color filter (CF3) corresponding to the first sub-pixel (SP1) to the third sub-pixel (SP3), respectively. The first color filter (CF1) to the third color filter (CF3) can allow light with different wavelength ranges to pass through it. For example, the first color filter (CF1) to the third color filter (CF3) can allow red light, green light, and blue light to pass through it, respectively.

[0116] In at least one embodiment, the first color filter CF1 to the third color filter CF3 may partially overlap. For example, the edge portions of the first color filter CF1 to the third color filter CF3 may meet in the boundary region BDA. In some embodiments, the first color filter CF1 to the third color filter CF3 may partially overlap each other in the boundary region BDA. In one or more embodiments, the first color filter CF1 to the third color filter CF3 may be spaced apart from each other, and a black matrix may be disposed between the first color filter CF1 to the third color filter CF3. For example, a black matrix may be disposed in the boundary region BDA.

[0117] The lens array LA can be disposed on the color filter layer CFL. The lens array LA may include a first lens LS1, a second lens LS2, and a third lens LS3, respectively corresponding to the first sub-pixel SP1 to the third sub-pixel SP3. The first lens LS1 to the third lens LS3 can each output light emitted from the first light-emitting element LD1 to the third light-emitting element LD3 along their respective paths, thereby improving luminous efficiency. In an embodiment, the outer coating OC can be disposed on the optical functional layer OFL, and the cover window CW can be disposed on the outer coating OC.

[0118] Figure 4 It is shown Figure 3 A view of the transistor region shown.

[0119] refer to Figure 4 The transistor region TA may include a first region SCP1 and a second region SCP2. Figure 4 The transistor region TA shown can correspond to Figure 3 The transistor region TA and transistor T_SP1 are shown in the diagram. That is, transistor region TA can be referred to as transistor T_SP1.

[0120] The pixel circuit layer PCL disposed on the substrate SUB may also include a gate insulating layer GI, an interlayer insulating layer ILD, and a passivation layer PSV.

[0121] An interlayer insulating layer (ILD) may be disposed on the gate insulating layer (GI). In some embodiments, the ILD may be an inorganic insulating layer comprising inorganic materials, but this disclosure is not limited thereto. In some embodiments, the ILD may be an organic insulating layer comprising organic materials. The organic insulating layer may include at least one of, for example, acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, and benzocyclobutene resin.

[0122] A first conductive pattern CP1 and a second conductive pattern CP2 can be disposed on the interlayer insulating layer (ILD). The first conductive pattern CP1 can be electrically connected to the first region SCP1 through a first connection portion RC1 passing through the gate insulating layer (GI) and the interlayer insulating layer (ILD). The second conductive pattern CP2 can be electrically connected to the second region SCP2 through a second connection portion RC2 passing through the gate insulating layer (GI) and the interlayer insulating layer (ILD).

[0123] A passivation layer PSV can be disposed on an interlayer insulating layer (ILD). In an embodiment, the passivation layer PSV may include an inorganic protective layer and an organic protective layer disposed on the inorganic protective layer. The inorganic protective layer may include at least one of silicon oxide and silicon nitride. The organic protective layer may include one of acrylic resin, polyimide (PI), polyamide (PA), and benzocyclobutene (BCB). The organic protective layer may be transparent and may have flowability. For example, the organic protective layer may be a planarization layer capable of reducing and planarizing the bending of the underlying structure.

[0124] When a substrate SUB, including a silicon wafer substrate, is exposed to ultraviolet light, electron-hole pairs can be generated within the substrate SUB. The electron-hole pairs generated within the substrate SUB allow holes to move through the lower portion of the channel region between the first region SCP1 and the second region SCP2. Therefore, the channel length of transistor T_SP1 can be reduced, and the threshold voltage of transistor T_SP1 can be increased. In other words, the channel length and threshold voltage of transistor T_SP1 can be reduced due to ultraviolet light exposure. Furthermore, the brightness level presented by the sub-pixel SP in which transistor T_SP1 is disposed can vary. For example, the brightness level presented by the sub-pixel SP in which transistor T_SP1 is disposed can differ from the brightness level presented by another sub-pixel SP. In some embodiments, the reduction in channel length and increase in threshold voltage of transistor T_SP1 due to ultraviolet light exposure can be compensated, and the sub-pixel SPs of pixel PXL can exhibit a uniform brightness level.

[0125] Figure 5 It is shown Figure 3 A view of an embodiment of the transistor region shown.

[0126] refer to Figure 5 The transistor region TA may include a first doped region, a first doped sub-region, and a second doped sub-region. For example, the transistor region TA may include a first region SCP1, a first sub-region SCP2_1, and a second sub-region SCP2_2. Figure 5 The transistor region TA shown can correspond to Figure 3 The transistor region TA and transistor T_SP1 are shown in the diagram.

[0127] Figure 5 The first area SCP1 shown can be similar to Figure 4 The first area SCP1 shown is shown. Figure 5 The first sub-region SCP2_1 shown can be similar to Figure 4 The second area SCP2 shown, and Figure 5 The pixel circuit layer PCL shown can be similar to Figure 4 The pixel circuit layer PCL is shown. Detailed descriptions of the first region SCP1, the first sub-region SCP2_1, and the pixel circuit layer PCL, which may be redundant or omitted, can be simplified.

[0128] A first region SCP1, a first sub-region SCP2_1, and a second sub-region SCP2_2 can be disposed in a substrate SUB. A well WL can be disposed in the substrate. The well WL can be formed by an ion implantation process. The first region SCP1, the first sub-region SCP2_1, and the second sub-region SCP2_2 can be disposed in the well WL. The first region SCP1, the first sub-region SCP2_1, and the second sub-region SCP2_2 can be disposed in the well WL and spaced apart from each other. The second sub-region SCP2_2 can be disposed relative to the first sub-region SCP2_1 in a first direction DR1. In an embodiment, the first region SCP1 can be a source region, and the first sub-region SCP2_1 and the second sub-region SCP2_2 can correspond to drain regions.

[0129] The channel length L2 between the first region SCP1 and the second sub-region SCP2_2 can differ from the channel length L1 between the first region SCP1 and the first sub-region SCP2_1. For example, the channel length L2 between the first region SCP1 and the second sub-region SCP2_2 can be longer than the channel length L1 between the first region SCP1 and the first sub-region SCP2_1. The extent to which the channel length L2 can be reduced due to degradation can be approximately equal to the extent to which the channel length L1 can be reduced due to degradation.

[0130] Although the channel length L2 between the first region SCP1 and the second sub-region SCP2_2 can decrease due to degradation, the reduced channel length can be approximately equal to the channel length L1 between the first region SCP1 and the first sub-region SCP2_1. Therefore, the decrease in channel length and increase in threshold voltage of the transistor T_SP1 under ultraviolet exposure can be compensated by forming a channel between the first region SCP1 and the second sub-region SCP2_2, wherein, in the degraded state, the reduced channel length between the first region SCP1 and the second sub-region SCP2_2 is approximately equal to the channel length L1.

[0131] In this implementation, if the transistor deteriorates due to UV exposure, the second conductive pattern CP2 can be connected to the second sub-region SCP2_2. If the transistor is not deteriorated, the second conductive pattern CP2 can be connected to the first sub-region SCP2_1. That is, one of the first sub-region SCP2_1 and the second sub-region SCP2_2 can be selected based on the degree of transistor degradation, and the selected region can be connected to the second conductive pattern CP2. In this implementation, the channel length and threshold voltage can be substantially maintained during UV exposure, and the sub-pixel SP can exhibit a relatively uniform brightness level.

[0132] In an implementation, the amount of impurities doped or implanted into the second sub-region SCP2_2 may differ from the amount of impurities doped or implanted into the first sub-region SCP2_1. For example, the amount of impurities doped or implanted into the second sub-region SCP2_2 may be greater than the amount of impurities doped or implanted into the first sub-region SCP2_1. For example, the amount of impurities doped or implanted into the second sub-region SCP2_2 may be sufficient such that although the channel length L2 between the first region SCP1 and the second sub-region SCP2_2 may decrease due to ultraviolet light exposure of transistor T_SP1, the reduced channel length may be approximately equal to the channel length L1 between the first region SCP1 and the first sub-region SCP2_1 before any degradation.

[0133] Figure 6 It is shown Figure 3 A view of an embodiment of the transistor region shown.

[0134] refer to Figure 6 The transistor region TA may include a first subregion SCP1_1, a second subregion SCP1_2, and a second region SCP2. Figure 6 The transistor region TA shown can correspond to Figure 3 The transistor region TA and the first transistor T_SP1 are shown in the diagram.

[0135] Figure 6The first sub-region SCP1_1 shown can be similar to Figure 4 The first area SCP1 shown is shown. Figure 6 The second area SCP2 shown can be similar to Figure 4 The second area SCP2 shown, and Figure 6 The pixel circuit layer PCL shown can be similar to Figure 4 The pixel circuit layer PCL is shown. Detailed descriptions of the first sub-region SCP1_1, the second region SCP2, and the pixel circuit layer PCL may be omitted or simplified, even if they are repetitive or redundant.

[0136] The first sub-region SCP1_1, the second sub-region SCP1_2, and the second region SCP2 can be disposed in the substrate SUB. The well WL can be disposed in the substrate SUB. The well WL can be formed by an ion implantation process. The first sub-region SCP1_1, the second sub-region SCP1_2, and the second region SCP2 can be disposed in the well WL. The first sub-region SCP1_1, the second sub-region SCP1_2, and the second region SCP2 can be disposed in the well WL and spaced apart from each other. The second sub-region SCP1_2 can be disposed in a direction opposite to the first direction DR1 relative to the first sub-region SCP1_1. In an embodiment, the first sub-region SCP1_1 and the second sub-region SCP1_2 can correspond to the source region, and the second region SCP2 can be the drain region.

[0137] The channel length L2 between the second subregion SCP1_2 and the second region SCP2 can differ from the channel length L1 between the first subregion SCP1_1 and the second region SCP2. For example, the channel length L2 between the second subregion SCP1_2 and the second region SCP2 can be longer than the channel length L1 between the first subregion SCP1_1 and the second region SCP2. The extent to which the channel length L2 can be reduced due to degradation can be approximately equal to the extent to which the channel length L1 can be reduced due to degradation.

[0138] Although the channel length L2 between the second sub-region SCP1_2 and the second region SCP2 can decrease due to degradation, the reduced channel length can be approximately equal to the channel length L1 between the first sub-region SCP1_1 and the second region SCP2. Therefore, the reduction in channel length and increase in threshold voltage of transistor T_SP1 caused by ultraviolet exposure can be compensated by forming a channel between the second sub-region SCP1_2 and the second region SCP2. In the degraded state, the reduced channel length of the channel formed between the second sub-region SCP1_2 and the second region SCP2 is approximately equal to the channel length L1.

[0139] In an implementation, if the transistor deteriorates due to UV exposure, the first conductive pattern CP1 can be connected to the second sub-region SCP1_2. If the transistor is not deteriorated, the first conductive pattern CP1 can be connected to the first sub-region SCP1_1. That is, one of the first sub-region SCP1_1 and the second sub-region SCP1_2 can be selected based on the degree of transistor deterioration, and the selected region can be connected to the first conductive pattern CP1. In an implementation, the channel length and threshold voltage of the transistor of the sub-pixel can be substantially maintained during UV exposure, and the sub-pixel can exhibit a relatively uniform brightness level. For example, the transistors of the sub-pixel can have relatively identical channel lengths and relatively identical threshold voltages, and the sub-pixel can exhibit a relatively uniform brightness level. Here, "relatively identical," "relatively uniform," and "substantially maintained" can be measured based on the brightness level of the sub-pixel using different optional sub-regions under different conditions, for example, based on exposure to UV light. For example, one sub-region of the sub-pixel can be used in the absence of UV light, and another sub-region of the sub-pixel can be used in the presence of UV light. Sub-regions can be selected such that sub-pixels can have relatively identical channel lengths and relatively identical threshold voltages regardless of UV exposure, and that the sub-pixels can exhibit uniform brightness levels. For example, sub-regions can be selected to improve the uniformity of brightness levels in sub-pixels and / or pixels.

[0140] In an implementation, the amount of impurities doped or implanted into the second sub-region SCP1_2 may be greater than the amount of impurities doped or implanted into the first sub-region SCP1_1.

[0141] In the transistor region according to this disclosure, degradation caused by ultraviolet exposure can be compensated, and the brightness of the display device can be uniformly controlled.

[0142] Figure 7 This is a block diagram illustrating an electronic device 1000 according to an embodiment of the present disclosure. Figure 8 It is shown Figure 7 The diagram shows an example of an electronic device 1000, which is a smartphone. Figure 9 It is shown Figure 7 The electronic device 1000 is a schematic diagram of an example of a tablet computer.

[0143] refer to Figures 7 to 9 The electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. The display device 1060 may be... Figure 1The display device 100. The electronic device 1000 may also include various ports for communicating with video cards, sound cards, memory cards, USB devices, or other systems. In embodiments, such as Figure 8 As shown, the electronic device 1000 can be implemented as a smartphone. In an implementation, as... Figure 9 As shown, the electronic device 1000 can be implemented as a tablet computer. However, the above example is illustrative, and the electronic device 1000 is not limited to the above example. For example, the electronic device 1000 can be implemented as a cellular phone, video phone, smartboard, smartwatch, vehicle navigation device, computer display, laptop computer, head-mounted display device, etc.

[0144] Processor 1010 can perform specific calculations or tasks. In embodiments, processor 1010 may include at least one of a central processing unit, an application processor, a graphics processing unit, a communication processor, an image signal processor, a controller, etc. Processor 1010 can be connected to other components via an address bus, a control bus, a data bus, etc. In embodiments, processor 1010 may be connected to an expansion bus, such as a peripheral component interconnect (PCI) bus. In embodiments, processor 1010 can provide input image data to display device 1060. Therefore, display device 1060 can display an image based on the input image data provided from processor 1010.

[0145] The memory device 1020 can store data required for performing operations of the electronic device 1000. The memory device 1020 can be used as working memory and / or buffer memory for the processor 1010. For example, the memory device 1020 may include one or more volatile memory devices, such as dynamic random access memory (DRAM) devices, static random access memory (SRAM) devices, and mobile DRAM devices.

[0146] Storage device 1030 can store data in response to control signals or data from processor 1010. Storage device 1030 may include one or more non-volatile memories to retain data even when electronic device 1000 is powered off. In some embodiments, storage device 1030 may include solid-state drive (SSD), hard disk drive (HDD), CD-ROM, etc.

[0147] I / O device 1040 may include input devices such as a keyboard, keypad, touchpad, touchscreen, and mouse, as well as output devices such as speakers and printers. In some embodiments, display device 1060 may be integrated with I / O device 1040.

[0148] Power supply 1050 can provide the power required to operate electronic device 1000. For example, power supply 1050 may include a power management integrated circuit (PMIC). In one embodiment, power supply 1050 may provide power to display device 1060.

[0149] Display device 1060 can display images in response to image data signals and / or control signals from processor 1010. Display device 1060 can be connected to other components via a bus or other communication link.

[0150] Exemplary embodiments have been disclosed herein, and although specific terminology has been used, it is used and interpreted in a general and descriptive sense only and not for limiting purposes. In some instances, as will be apparent to those skilled in the art, unless specifically indicated otherwise, features, characteristics, and / or elements described in connection with particular embodiments at the time of filing this application may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of this disclosure as set forth in the appended claims.

Claims

1. A transistor region, characterized by The transistor region includes: Substrate; A first region is disposed in the substrate; The first sub-region and the second sub-region are disposed in the substrate; A gate insulating layer is disposed on the substrate; and An interlayer insulating layer is disposed on the gate insulating layer. The channel length between the first region and the second sub-region is longer than the channel length between the first region and the first sub-region.

2. The transistor region according to claim 1, characterized in that, The transistor region further includes a well disposed in the substrate, wherein the first region, the first sub-region, and the second sub-region are disposed in the well and spaced apart from each other.

3. The transistor region according to claim 2, characterized in that, The well is a channel region, and the transistor region also includes a gate electrode on the gate insulating layer and overlapping the channel region.

4. The transistor region according to claim 1, characterized in that, The transistor region also includes a first conductive pattern disposed on the interlayer insulating layer. The first conductive pattern is electrically connected to the first region through a first connection portion passing through the gate insulating layer and the interlayer insulating layer.

5. The transistor region according to claim 4, characterized in that, The transistor region further includes a second conductive pattern disposed on the interlayer insulating layer. The second conductive pattern is electrically connected to one of the first sub-region and the second sub-region through a second connection portion passing through the gate insulating layer and the interlayer insulating layer.

6. The transistor region according to claim 1, characterized in that, The amount of impurities in the second sub-region is greater than the amount of impurities in the first sub-region.

7. The transistor region according to claim 1, characterized in that, The first region is the source region, and the first sub-region and the second sub-region correspond to the drain region.

8. The transistor region according to claim 1, characterized in that, The first region is the drain region, and the first sub-region and the second sub-region correspond to the source region.

9. The transistor region according to claim 1, characterized in that, The second sub-region is disposed in a first direction relative to the first sub-region, and the first region is disposed in a second direction opposite to the first direction relative to the first sub-region.

10. A transistor region, characterized in that, The transistor region includes: Substrate; A first doped region is disposed in the substrate; A first doped sub-region and a second doped sub-region are disposed in the substrate; A gate insulating layer is disposed on the substrate; and An interlayer insulating layer is disposed on the gate insulating layer. The channel length between the first doped region and the second doped sub-region is different from the channel length between the first doped region and the first doped sub-region.

Images