Electronic devices, methods for manufacturing electronic devices

Abstract

To suppress generation of shrinkage.SOLUTION: The electronic device includes: a first electronic component having a Ni-based electrode; and a second electronic component joined to the Ni-based electrode by a Sn-based solder. There is a (Cu, Ni, Pd)6Sn5 compound layer in the interface of the joint part of the Ni-based electrode and the Sn-based solder. The content of Pd as a (Pd, Ni)Sn4 compound in the mother phase of the Sn-based solder after the joint is smaller than the content of Pd as a (Cu, Ni, Pd)6Sn5 compound layer or is zero.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to an electronic device and a method for manufacturing an electronic device.

Background Art

[0002] Due to the restrictions on the use of lead in electronic control devices mounted on automobiles by the RoHS Directive and the ELV Directive, the transition to lead-free has been promoted using mainly lead-free solder such as Sn-3Ag-0.5Cu (weight %). The power module used in an inverter is trending towards higher power density for the purpose of miniaturization and weight reduction, and for example, the following two points are required. First, the upper and lower surfaces of the power semiconductor are solder-bonded so that heat can be dissipated from both the upper and lower surfaces of the power module. Second, the guaranteed temperature of the power semiconductor junction is increased so that more current can flow.

[0003] Ni-based electrodes responsible for bonding with solder are used for the electrodes of semiconductor elements, and in order to ensure easy wetting of the solder, the re-surface of the electrodes is metallized with Au or Ag. However, depending on the heating and storage environment during the chip manufacturing process, Ni may diffuse to the surface of the thin Au metallization or the Ag metallization with many defects, generating Ni oxide on the outermost surface from the re-surface, which may impair the solder bonding property. Therefore, in order not to form Ni oxide on the re-surface, the use of providing a Pd layer on the Ni-based electrode and then metallizing with Au or Ag has been increasing. Patent Document 1 discloses an alloy for lead-free solder balls composed of Ag: 3 to 6%, Cu: 1 to 4%, Co: 0.01 to 2%, and Sn: the remainder in atomic %.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In the invention described in Patent Document 1, there is room for consideration regarding countermeasures against shrinkage cavities. [Means for solving the problem]

[0006] An electronic device according to a first aspect of the present invention comprises a first electronic component having a Ni-based electrode and a second electronic component joined to the Ni-based electrode via Sn-based solder, wherein a (Cu,Ni,Pd)6Sn5 compound layer exists at the interface between the Ni-based electrode and the Sn-based solder, and the Pd content present as a (Pd,Ni)Sn4 compound in the matrix phase of the Sn-based solder after joining is less than or zero than the Pd content present as the (Cu,Ni,Pd)6Sn5 compound layer. A method for manufacturing an electronic device according to a second aspect of the present invention is a method for manufacturing an electronic device comprising a first electronic component having a Ni-based electrode and a second electronic component joined to the Ni-based electrode via Sn-based solder, the method comprising a placement step of placing Sn-based solder containing more Cu than the eutectic composition on the surface of the Pd layer of the first electronic component having a Pd layer formed on the outer periphery of the Ni-based electrode, By adjusting the Cu content in the Sn-based solder and the thickness of the solder joint according to the thickness of the Pd layer, (Pd,Ni)Sn is formed in the matrix phase of the Sn-based solder after bonding. 4 The Pd content present as a compound is (Cu, Ni, Pd) 6 Sn 5 The Pd content is set to be less than or zero than the Pd content present in the compound layer. The electronic device has a junction interface between the Ni-based electrode and the Sn-based solder. The aforementioned A (Cu,Ni,Pd)6Sn5 compound layer is formed. A method for manufacturing an electronic device according to a third aspect of the present invention is a method for manufacturing an electronic device comprising a first electronic component having a Ni-based electrode and a second electronic component joined to the Ni-based electrode via Sn-based solder, the method comprising a placement step of placing Sn-based solder containing more Cu than the eutectic composition on the surface of the Pd layer of the first electronic component having a Pd layer formed on the outer periphery of the Ni-based electrode, wherein the electronic device has (Cu,Ni,Pd) at the interface of the joint between the Ni-based electrode and the Sn-based solder. 6 Sn 5 A compound layer is formed, and the thickness of the (Cu,Ni,Pd) layer is 40 times thicker than the thickness of the Pd layer formed on the Ni-based electrode before bonding. 6 Sn 5 A compound layer is formed at the interface of the junction. [Effects of the Invention]

[0007] According to the present invention, the occurrence of shrinkage cavities can be suppressed. [Brief explanation of the drawing]

[0008] [Figure 1] A diagram showing an example of a cavities. [Figure 2] A diagram showing the behavior of solder during cooling. [Figure 3]Diagram showing the first configuration of an electronic component. [Figure 4] A diagram showing a configuration using a typical soldering iron. [Figure 5] Diagram showing the second configuration of the electronic component. [Figure 6] Diagram showing a method for manufacturing a semiconductor device. [Figure 7] Figures showing Examples 1-6 [Figure 8] Figures showing Comparative Examples 1 and 2 [Figure 9] Diagram showing a method for manufacturing a semiconductor device. [Figure 10] Figures showing Examples 7-9 [Figure 11] Figures showing comparative examples 3 and 4. [Modes for carrying out the invention]

[0009] —First Embodiment— A first embodiment of a semiconductor device, which is an electronic component, will be described below with reference to Figures 1 to 11. When using a chip with a Pd (palladium) layer on a Ni (nickel) electrode, it is known that shrinkage cavities are more likely to form at the solder joints compared to when using a chip without a Pd layer.

[0010] Figure 1 shows an example of a shrinkage cavity. In Figure 1, a solder joint 3 is formed between the semiconductor element 1 and the emitter-side lead 2 of the power module. A shrinkage cavity 101, shown in black, is formed in the region of the solder joint 3 closest to the emitter-side lead 2. In the example shown in Figure 1, more heat was dissipated from the semiconductor element 1 side than from the emitter-side lead 2 side. When a shrinkage cavity is formed, the heat dissipation path for the heat generated by the semiconductor element due to current flow is reduced, making it difficult to ensure reliability. Therefore, if a shrinkage cavity is formed, it will be judged as a defective product in the quality inspection after assembly. It is thought that the shrinkage cavity occurs because when Pd formed on the Ni-based electrode of the semiconductor element diffuses into the molten Sn (tin)-based lead-free solder during soldering, the liquidus temperature of the Sn-based lead-free solder rises.

[0011] The Ni-based electrode in this embodiment is, for example, only nickel, nickel and phosphorus, nickel and vanadium, etc. In this case, the ratio of nickel to phosphorus is, for example, about 100:1 to 15. In this case, the ratio of nickel to vanadium is, for example, about 100:1 to 15.

[0012] Figure 2 is a diagram showing the behavior of solder during cooling. The left side of Figure 2 shows the case where the temperature difference between the start and end of solder solidification is small, and the right side of Figure 2 shows the case where the temperature difference between the start and end of solder solidification is large. In Figure 2, time elapses from the upper part shown in the figure towards the lower part. Also in the example shown in Figure 2, a large amount of heat is radiated from the side of the semiconductor element 1. In the case where the temperature difference between the start and end of solder solidification shown on the left side of Figure 2 is small, the entire solder joint 3 contracts as a whole under the influence of volume shrinkage due to solidification. On the other hand, in the case where the temperature difference between the start and end of solder solidification shown on the right side of Figure 2 is large, it solidifies little by little from the cooled side and undergoes volume shrinkage during solidification at the final solidification part, and thus the shrinkage cavity 101 is likely to be formed. If, hypothetically, more heat is radiated from the side of the emitter-side lead 2 than from the side of the semiconductor element 1, the shrinkage cavity 101 is formed on the side of the semiconductor element 1.

[0013] Figure 3 is a diagram showing the first configuration of the semiconductor device 100 which is an electronic component in this embodiment. The left side shown in the figure shows the state before bonding, and the right side shown in the figure shows the state after bonding. On the surface of the semiconductor element 1, there are a Ni-based electrode 8, a Pd layer 7, and a metal film 6. The metal film 6 is a metallization with Au (gold) or Ag (silver). On the surface of the emitter-side lead 2, there is a Ni plating 5. In this embodiment, a copper-added solder 24 is arranged between the metal film 6 and the Ni plating 5 for bonding. The copper-added solder 24 is a Sn-based solder with more Cu (copper) added than the eutectic composition. Specifically, the copper-added solder 24 has a Cu weight% of 0.9% or more, preferably 3% or more and less than 6%, and a Sn weight% of 80% or more.

[0014] The copper-doped solder 24, which contains more Cu than the eutectic composition, contains a large amount of the Cu6Sn5 compound indicated by symbol 25. By joining using the Cu6Sn5 compound, Pd can be incorporated into the Cu6Sn5 compound supplied from within the solder, forming a compound as (Cu,Ni,Pd)6Sn5 compound at the joint interface 26. The solder joint consists of the joint interface 26 located at the top and bottom of the figure and the solder central layer 27.

[0015] At this time, by controlling the Cu content in the solder and the thickness L of the solder joint according to the Pd thickness of the semiconductor element 1, it is possible to incorporate Pd almost entirely into the (Cu,Ni,Pd)6Sn5 compound formed at the joint interface 26. Here, the thickness of the Pd layer 7 is represented by the symbol d, the thickness of the Pd layer is represented by the symbol y1, the thickness of the upper joint interface 26 is represented by the symbol y2, the density of Pd is represented by the symbol D1, and the density D2 of (Cu,Ni,Pd)6Sn5 is represented by the symbol D2. Since the Pd in ​​(Cu,Ni,Pd)6Sn5 is 3.6 wt%, the following equation 1 holds true for the weight of Pd. The left side of equation 1 describes the Pd before joining, and the right side describes the Pd after joining. Note that "x" in equation 1 is an operation symbol meaning multiplication.

[0016] dx D1=(y1+y2)x D2 x 0.036 (Formula 1)

[0017] Here, the Pd density D1 is 12.03 g / cm³ and the (Cu,Ni,Pd)6Sn5 density D2 is 8.33 g / cm³, so rearranging Equation 1 gives the following Equation 2.

[0018] y = y1 + y2 = 40.1 xd ... (Equation 2)

[0019] In other words, from Equation 2, it can be seen that the sum of the thickness of the upper joint interface 26 and the thickness of the lower joint interface 26 is approximately 40 times the thickness of the Pd layer 7 before joining. Furthermore, if the desired solder thickness L is determined, the required Cu content of the solder can be calculated based on the thickness y of the joint interface 26.

[0020] If all of the Pd can be incorporated into the joint interface 26, the (Pd,Ni)Sn4 compound will be almost completely absent in the solder central layer 27, thereby suppressing the rise in liquidus temperature and thus suppressing shrinkage cavities. The effect of suppressing shrinkage cavities is particularly pronounced when the Pd content present as the (Pd,Ni)Sn4 compound in the matrix phase of the Sn-based solder after joining is less than or zero than the Pd content present as the (Cu,Ni,Pd)6Sn5 compound layer. Note that the Ni content in the (Cu,Ni,Pd)6Sn5 compound layer is 5 wt.% or less.

[0021] Figure 4 shows a configuration using a general solder for comparison. The left side of the figure shows the state before joining, and the right side shows the state after joining. Comparing the left side of Figure 4 with the left side of Figure 3, general solder 4 is used instead of the copper-doped solder 24 in Figure 3. The presence of a Ni-based electrode 8, a Pd layer 7, and a metal film 6 on the surface of the semiconductor element 1, and the presence of Ni plating 5 on the surface of the emitter-side lead 2 are common to both Figure 4 and Figure 3. The general solder 4 is, for example, a Sn-based lead-free solder such as Sn-3Ag-0.5Cu.

[0022] In this case, the Pd contained in the Pd layer 7 is distributed between being incorporated as a component of the (Ni,Cu,Pd)3Sn4 compound formed at the joint interface through a reaction with the solder, and existing as floating islands of (Pd,Ni)Sn4 compound inside the solder joint. If we consider the joint separately as the intermetallic compound at the joint interface and the rest of the solder, the intermetallic compound formed at the joint interface is independent of the solder's liquidus temperature, while the liquidus temperature of the rest of the solder affects the likelihood of shrinkage cavities forming. Here, the more (Pd,Ni)Sn4 compound 23 is formed, the higher the solder's liquidus temperature becomes, and the more likely shrinkage cavities are to form.

[0023] Figure 5 shows a second configuration of the semiconductor device 100 in this embodiment. A semiconductor element 1, such as a power module, may have both its emitter and collector sides soldered together, as shown in Figure 5. Specifically, the semiconductor element 1 shown in Figure 5 is sandwiched between the collector-side lead 12 at the bottom and the emitter-side lead 2 at the top. In this case, since cooling begins from the collector-side lead 12 at the bottom, the collector-side junction (indicated by reference numeral 13) located on the underside of the semiconductor element 1 cools faster, while the emitter-side junction (indicated by reference numeral 3) cools more slowly. Since shrinkage cavities are more likely to occur at slower cooling rates, the emitter-side junction is more prone to developing them. Therefore, at least at the emitter-side junction, the formation of shrinkage cavities can be suppressed by bonding a semiconductor element having Pd on a Ni-based electrode with Sn-based solder containing more Cu than the eutectic composition.

[0024] (Examples 1-6) Examples 1 to 6 will be described with reference to Figures 6 and 7. The manufacturing method for the semiconductor device 100A shown in Figure 6 is as follows. First, collector-side solder 24-2 is supplied to the solder mounting position of the Cu collector-side lead 32 having roughened Ni plating. On top of that, a semiconductor element 1 having a 600 nm thick Pd layer on both Ni-based electrodes is bonded. Furthermore, emitter-side solder 24-1 is placed on the electrode on the upper surface of the bonded semiconductor element 1, and then a copper emitter-side lead 31 having roughened Ni plating is laminated and bonded on top of that. This makes it possible to incorporate Pd supplied from the semiconductor device into the (Cu,Ni,Pd)6Sn5 compound at the junction interface, with almost no (Pd,Ni)Sn4 compound inside the emitter-side junction where shrinkage cavities are easily generated. After that, the semiconductor device 100A is manufactured by sealing with resin 33 using a transfer mold.

[0025] The composition of the emitter-side solder 24-1 and collector-side solder 24-2 for each example is as shown in the "Upper board solder" and "Lower board solder" columns of Figure 10. For example, in Example 1, both the collector-side solder 24-2 and the emitter-side solder 24-1 are solders mainly composed of Sn with Cu at 3% to less than 6% by weight. In Example 2, both the collector-side solder 24-2 and the emitter-side solder 24-1 are solders mainly composed of Sn with Ag at 4% by weight and Cu at 3% to less than 6% by weight.

[0026] For each example, 100 semiconductor devices 100A were fabricated, and the presence of shrinkage cavities 101 was evaluated. The evaluation of shrinkage cavities 101 was based on the following criteria: "Pass" if no shrinkage cavities 101 exceeding 5% of the joint area were found in any of the 100 devices, and "Fail" if even one device showed shrinkage cavities exceeding 5%. As a result, all of Examples 1 to 6 were deemed "Pass".

[0027] (Comparative Examples 1-2) Comparative Examples 1 and 2 will be explained with reference to Figures 6 and 8. Comparative Examples 1 and 2 differed from Examples 1 to 6 only in the composition of the emitter-side solder 24-1 and the collector-side solder 24-2. Semiconductor devices were similarly fabricated and evaluated. As a result of the evaluation, both Comparative Examples 1 and 2 were deemed "unacceptable".

[0028] (Examples 7-9) Examples 7 to 9 will be described with reference to Figures 9 and 10. The manufacturing method for the semiconductor device 100B shown in Figure 9 is as follows. First, a sheet of lower substrate solder 24-4 is placed on the heat dissipation base 45, and a ceramic insulating substrate 43 is laminated on top of it. The emitter-side lead 2 is arranged on the upper side of the ceramic insulating substrate 43 as shown. Next, upper substrate solder 24-3 is placed on the emitter-side lead 2, and after the semiconductor element 1 is installed, it is heated and bonded. Then, after the solder is bonded, the aluminum wire 42 and terminal 41 are bonded, and then the case 47 is attached. Finally, the inside of the case 47 is sealed with gel 46 to manufacture the semiconductor device 100B.

[0029] The compositions of the upper substrate solder 24-3 and lower substrate solder 24-4 for each example are as shown in the "Upper Substrate Solder" and "Lower Substrate Solder" columns of Figure 10. For each example, 100 semiconductor devices 100B were fabricated and the presence of shrinkage cavities 101 was evaluated. The evaluation of shrinkage cavities 101 was "pass" if no shrinkage cavities 101 exceeding 5% of the joint area were found in any of the 100 devices, and "fail" if even one device showed shrinkage cavities 101 exceeding 5%. As a result, as shown in Figure 10, all of Examples 7 to 9 were "passed".

[0030] (Comparative Examples 3-4) Comparative Examples 3 and 4 will be explained with reference to Figures 9 and 11. The only difference from Examples 7 to 9 is the composition of the solder 24-3 on the upper part of the substrate and the solder 24-4 on the lower part of the substrate. Comparative Examples 3 and 4 were similarly constructed and evaluated. The compositions of the solder 24-3 on the upper part of the substrate and the solder 24-4 on the lower part of the substrate for Comparative Examples 3 and 4 are as shown in the "Solder on the upper part of the substrate" and "Solder on the lower part of the substrate" columns in Figure 11. As a result of the evaluation, both Comparative Examples 1 and 2 were deemed "failures".

[0031] According to the first embodiment described above, the following effects and advantages can be obtained. (1) The semiconductor device 100, which is an electronic device, comprises a semiconductor element 1 having a Ni-based electrode and an emitter-side lead 2 joined to the Ni-based electrode via Sn-based solder. A (Cu,Ni,Pd)6Sn5 compound layer exists at the interface 26 of the joint between the Ni-based electrode and the Sn-based solder, and the Pd content present as a (Pd,Ni)Sn4 compound in the matrix phase of the Sn-based solder after joining is less than or zero than the Pd content present as a (Cu,Ni,Pd)6Sn5 compound layer. Therefore, the occurrence of shrinkage cavities 101 is suppressed.

[0032] (2) The semiconductor device 1 is equipped with multiple Ni-based electrodes, and the (Cu,Ni,Pd)6Sn5 compound layer is present at least at the interface between the Ni-based electrode that takes the longest time to dissipate heat and the Sn-based solder. For example, in the example shown in Figure 6, heat is dissipated from the collector-side lead 32 at the bottom of the figure, so shrinkage cavities 101 are less likely to occur in the collector-side solder 24-2 which cools quickly, making countermeasures less necessary. However, on the side that takes longer to cool, the emitter side in the example of Figure 6, shrinkage cavities 101 may occur if no countermeasures are taken, so the occurrence of shrinkage cavities 101 is suppressed by using solder with the above composition.

[0033] (3) The semiconductor device 100 has a Ni content of 5 wt.% or less in the (Cu,Ni,Pd)6Sn5 compound layer.

[0034] (4) A method for manufacturing a semiconductor device 100 comprising a semiconductor element 1 having a Ni-based electrode and an emitter-side lead 2 joined to the Ni-based electrode via Sn-based solder includes a placement step of placing copper-doped solder 24 containing more Cu than the eutectic composition on the surface of the Pd layer of the semiconductor element 1, which has a Pd layer formed on the outer periphery of the Ni-based electrode. In the semiconductor device 100, a (Cu,Ni,Pd)6Sn5 compound layer is formed at the interface between the Ni-based electrode and the Sn-based solder.

[0035] (5) The semiconductor device 1 has multiple Ni-based electrodes. In the placement process, copper-doped solder 24 containing more Cu than the eutectic composition is placed at least between the upper Ni-based electrode shown in Figure 6, which requires time for heat dissipation, and the emitter-side lead 31.

[0036] (6) The composition of copper-doped solder 24, which contains more Cu than the eutectic composition, contains 3-6 wt.% Cu.

[0037] (7) As explained with reference to Figure 3, a (Cu,Ni,Pd)6Sn5 compound layer with a thickness L, which is 40 times the thickness d of the Pd layer on the Ni electrode of the semiconductor device 1, is formed at the junction interface.

[0038] (Variation 1) In the first embodiment described above, a solder composition for suppressing the occurrence of shrinkage cavities 101 at the junction of a power module, which is a semiconductor element, was explained. However, since the occurrence of shrinkage cavities 101 can be a problem in all aspects of electronic components, the application of the present invention is not limited to power modules, but can be applied to various semiconductor elements. Furthermore, it is not limited to semiconductors, but can be applied to various electronic devices equipped with electrodes.

[0039] The embodiments and modifications described above may be combined in any way. Although various embodiments and modifications have been described above, the present invention is not limited to these. Other embodiments that can be conceivable within the scope of the technical idea of ​​the present invention are also included within the scope of the present invention. [Explanation of symbols]

[0040] 1: Semiconductor element 7: Pd layer 8:Ni-based electrode 12: Collector-side lead 24: Copper-added solder 24-1: Emitter side soldering 24-2: Collector side soldering 24-3: Solder on top of circuit board 24-4: Solder on the bottom of the circuit board 31: Emitter-side lead 32: Collector-side lead 100, 100A, 100B: Semiconductor equipment 101: Hikesu

Claims

1. A first electronic component having a Ni-based electrode, The device comprises a second electronic component which is joined to the Ni electrode via Sn-based solder, (Cu, Ni, Pd) at the interface of the junction between the Ni-based electrode and the Sn-based solder ６ Sn ５ A compound layer exists, In the matrix of the Sn-based solder after bonding, (Pd, Ni)Sn ４ The Pd content present as a compound is the (Cu, Ni, Pd) ６ Sn ５ An electronic device in which the Pd content is less than or zero than that present as a compound layer.

2. The electronic device according to claim 1, The first electronic component is a semiconductor element, and the electronic device is an electronic device.

3. The electronic device according to claim 1, The first electronic component is a semiconductor element having a plurality of Ni-based electrodes, The above (Cu, Ni, Pd) ６ Sn ５ An electronic device wherein the compound layer exists at least at the interface between the Ni-based electrode, which takes the longest time to dissipate heat among the plurality of Ni-based electrodes, and the Sn-based solder at the joint.

4. The electronic device according to claim 1, The above (Cu, Ni, Pd) ６ Sn ５ An electronic device in which the Ni content in the compound layer is 5 wt.% or less.

5. A method for manufacturing an electronic device comprising a first electronic component having a Ni-based electrode and a second electronic component joined to the Ni-based electrode via Sn-based solder, The first electronic component, having a Pd layer formed on the outer periphery of the Ni-based electrode, includes a placement step of placing a Sn-based solder containing more Cu than the eutectic composition on the surface of the Pd layer. By adjusting the Cu content in the Sn-based solder and the thickness of the solder joint according to the thickness of the Pd layer, the Pd content present as a (Pd,Ni)Sn4 compound in the matrix phase of the Sn-based solder after bonding is reduced to less than or zero than the Pd content present as a (Cu,Ni,Pd)6Sn5 compound layer. The aforementioned electronic device has the (Cu, Ni, Pd) at the interface of the joint between the Ni-based electrode and the Sn-based solder. ６ Sn ５ A method for manufacturing an electronic device in which a compound layer is formed.

6. A method for manufacturing an electronic device according to claim 5, A method for manufacturing an electronic device, wherein the first electronic component is a semiconductor element.

7. A method for manufacturing an electronic device according to claim 5, The first electronic component is a semiconductor element having a plurality of Ni-based electrodes, A method for manufacturing an electronic device, wherein in the arrangement step, Sn-based solder containing more Cu than the eutectic composition is placed between at least the Ni-based electrode that takes the longest time to dissipate heat among the plurality of Ni-based electrodes and the second electronic component.

8. A method for manufacturing an electronic device according to claim 5, The composition of the Sn-based solder containing more Cu than the eutectic composition is 3 to 6 wt.% Cu, and the method for manufacturing an electronic device.

9. A method for manufacturing an electronic device comprising a first electronic component having a Ni-based electrode and a second electronic component joined to the Ni-based electrode via Sn-based solder, The first electronic component, having a Pd layer formed on the outer periphery of the Ni-based electrode, includes a placement step of placing a Sn-based solder containing more Cu than the eutectic composition on the surface of the Pd layer. In the aforementioned electronic device, a (Cu, Ni, Pd)6 Sn5 compound layer is formed at the interface of the joint between the Ni-based electrode and the Sn-based solder. (Cu, Ni, Pd) with a thickness 40 times greater than the thickness of the Pd layer formed on the Ni-based electrode before bonding. ６ Sn ５ A method for manufacturing an electronic device in which a compound layer is formed at the interface of the junction.

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