Display device and electronic device including the same

Abstract

A display device and an electronic device including the display device are provided. The display device according to one or more embodiments of the present disclosure includes a first sub-pixel, a second sub-pixel, and a third sub-pixel, wherein each of the first to third sub-pixels includes: a reflective electrode; a resonant layer on the reflective electrode; a first electrode on the resonant layer; a pixel defining layer located above the first electrode, the pixel defining layer having an opening; a light-emitting structure on the first electrode and the pixel defining layer; and a second electrode on the light-emitting structure, wherein the thickness of the resonant layer of the first sub-pixel is less than the thickness of the resonant layer of the second sub-pixel, and wherein the depth of the opening of the first sub-pixel is greater than the depth of the opening of the second sub-pixel. The display device has improved brightness.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2024-0050024, filed on April 15, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure generally relates to a display device, a method of manufacturing the display device, and an electronic device including the display device. Background Technology

[0003] Recently, with the increasing interest in information display, research and development of display devices has been ongoing. Utility Model Content

[0004] The purpose of this invention is to provide a high-brightness display device and a method for manufacturing the display device.

[0005] According to some embodiments of this disclosure, a display device is provided, the display device including a first sub-pixel, a second sub-pixel, and a third sub-pixel, wherein each of the first to third sub-pixels includes: a reflective electrode; a resonant layer on the reflective electrode; a first electrode on the resonant layer; a pixel defining layer located above the first electrode, the pixel defining layer having an opening; a light-emitting structure on the first electrode and the pixel defining layer; and a second electrode on the light-emitting structure, wherein the thickness of the resonant layer of the first sub-pixel is less than the thickness of the resonant layer of the second sub-pixel, and wherein the depth of the opening of the first sub-pixel is greater than the depth of the opening of the second sub-pixel.

[0006] In some embodiments, the first electrode may cover the top and side surfaces of the resonant layer.

[0007] In some embodiments, the first electrode may be in contact with the side surface of the reflective electrode.

[0008] In some embodiments, the thickness of the resonant layer of the second sub-pixel may be less than the thickness of the resonant layer of the third sub-pixel.

[0009] In some embodiments, the depth of the opening of the second sub-pixel may be greater than the depth of the opening of the third sub-pixel.

[0010] In some embodiments, the pixel defining layer may include a first layer on the first electrode and a second layer on the first layer.

[0011] In some embodiments, the depth of the opening of the third sub-pixel can be equal to the thickness of the first layer.

[0012] In some embodiments, the thickness of the first layer may be less than the thickness of the second layer.

[0013] In some embodiments, the display device may further include a first barrier layer on the bottom of the reflective electrode.

[0014] In some embodiments, the display device may further include a second blocking layer on top of the reflective electrode.

[0015] In some embodiments, the thickness of the second barrier layer may be less than the thickness of the first barrier layer.

[0016] According to some disclosed embodiments, a method for manufacturing a display device is provided, the method comprising the steps of: forming a reflective electrode in a first sub-pixel to a third sub-pixel; forming a resonant layer on the reflective electrode; patterning the reflective electrode and the resonant layer; forming a first electrode on the reflective electrode and the resonant layer; forming a pixel defining layer on the first electrode; polishing the pixel defining layer; forming a trench of the pixel defining layer between the first sub-pixel and the third sub-pixel; forming an opening in the pixel defining layer to expose the first electrode; and forming a light-emitting structure on the first electrode exposed by the opening, wherein the resonant layers of the first sub-pixel to the third sub-pixel are formed to have different thicknesses than each other.

[0017] In some embodiments, the first electrode can be formed directly on the top and side surfaces of the resonant layer.

[0018] In some embodiments, the first electrode may be formed directly on the side surface of the reflective electrode.

[0019] In some embodiments, the thickness of the resonant layer of the first sub-pixel can be made smaller than the thickness of the resonant layer of the second sub-pixel.

[0020] In some embodiments, the depth of the opening of the first sub-pixel can be configured to be greater than the depth of the opening of the second sub-pixel.

[0021] In some embodiments, the thickness of the resonant layer of the second sub-pixel can be made smaller than the thickness of the resonant layer of the third sub-pixel.

[0022] In some embodiments, the depth of the opening of the second sub-pixel is formed to be greater than the depth of the opening of the third sub-pixel.

[0023] In some embodiments, the method may further include the step of forming a barrier layer between the reflective electrode and the resonant layer.

[0024] In some embodiments, the pixel defining layer may include a first layer and a second layer formed on the first layer, and in the step of polishing the pixel defining layer, the second layer may be polished to expose the top surface of the first layer of the third sub-pixel.

[0025] According to some embodiments of this disclosure, an electronic device is provided, the electronic device comprising: a processor for providing input image data; and a display device for displaying an image based on the input image data, the display device including a sub-pixel region, wherein the display device includes a first sub-pixel, a second sub-pixel, and a third sub-pixel, wherein each of the first to third sub-pixels includes: a reflective electrode; a resonant layer on the reflective electrode; a first electrode on the resonant layer; a pixel defining layer located above the first electrode, the pixel defining layer having an opening; a light-emitting structure on the first electrode and the pixel defining layer; and a second electrode on the light-emitting structure, wherein the thickness of the resonant layer of the first sub-pixel is less than the thickness of the resonant layer of the second sub-pixel, and wherein the depth of the opening of the first sub-pixel is greater than the depth of the opening of the second sub-pixel.

[0026] In this invention, by providing a first resonant layer, a second resonant layer, and a third resonant layer with different thicknesses in the display device, light within a specific wavelength range can be effectively and efficiently amplified in each of the first sub-pixel, the second sub-pixel, and the third sub-pixel, thereby improving the brightness of the display device. Attached Figure Description

[0027] Exemplary embodiments will now be described more fully below with reference to the accompanying drawings; however, they may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the exemplary embodiments to those skilled in the art.

[0028] In the accompanying drawings, dimensions may be exaggerated for clarity. It will be understood that when an element is referred to as "between" two elements, the element may be the only element between the two elements, or there may be one or more intervening elements. The same reference numerals always denote the same elements.

[0029] Figure 1 This is a block diagram illustrating a display device according to some embodiments of the present disclosure.

[0030] Figure 2 This illustrates some embodiments according to the present disclosure. Figure 1 A block diagram of one of the sub-pixels shown.

[0031] Figure 3 This illustrates some embodiments according to the present disclosure. Figure 2 The circuit diagram of the sub-pixel is shown.

[0032] Figure 4 This illustrates some embodiments according to the present disclosure. Figure 1 The plan view of the display panel is shown.

[0033] Figure 5 This illustrates some embodiments according to the present disclosure. Figure 4 An exploded perspective view of a portion of the display panel shown.

[0034] Figure 6 This illustrates some embodiments according to the present disclosure. Figure 5 A planar view of one of the pixels shown.

[0035] Figure 7 Some embodiments according to this disclosure are shown along Figure 6 The sectional view shown is taken by line I-I'.

[0036] Figure 8 and Figure 9 This illustrates some embodiments according to the present disclosure. Figure 7 An enlarged cross-sectional view of a portion of the light-emitting element layer shown.

[0037] Figure 10 This illustrates some embodiments according to this disclosure. Figure 7 A cross-sectional view of the light-emitting structure in any one of the first to third light-emitting elements shown.

[0038] Figure 11 This illustrates some other embodiments according to this disclosure, including... Figure 7 A cross-sectional view of the light-emitting structure in one of the first to third light-emitting elements shown.

[0039] Figure 12 This illustrates some other embodiments according to the present disclosure. Figure 5 A planar view of one of the pixels shown.

[0040] Figure 13 This illustrates yet another embodiment according to the present disclosure. Figure 5 A planar view of one of the pixels shown.

[0041] Figure 14 This is a block diagram illustrating a display system according to some embodiments of the present disclosure.

[0042] Figure 15 This illustrates some embodiments according to the present disclosure. Figure 14 The image shows a perspective view of an application example of the display system.

[0043] Figure 16 This illustrates a user-worn device according to some embodiments of the present disclosure. Figure 15 A view of the head-mounted display device shown.

[0044] Figures 17 to 24This is a cross-sectional view illustrating the process steps of a method for manufacturing a display device according to some embodiments of the present disclosure.

[0045] Figures 25 to 34 This is a cross-sectional view illustrating the process steps of a method for manufacturing a display device according to some embodiments of the present disclosure. Detailed Implementation

[0046] In the following description, embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. In the description below, portions necessary for understanding operation according to the present disclosure are described, and descriptions of other portions may be omitted so as not to unnecessarily obscure the subject matter of the disclosure. Furthermore, the present disclosure is not limited to the exemplary embodiments described herein, but may be implemented in various different forms. Rather, the exemplary embodiments described herein are provided to thoroughly and completely describe the disclosure and to fully convey (e.g., communicate) the disclosed concepts to those skilled in the art.

[0047] Throughout this specification, when an element is referred to as "connected" or "joined" to another element, the element may be directly connected or joined to the other element, or indirectly connected or joined to the other element with one or more intermediary elements inserted therebetween. The technical terminology used herein is for illustrative purposes only and is not intended to limit the embodiments. It will be understood that when an component "comprises" an element, unless there is another description to the contrary, it should be understood that the component does not exclude another element but may also include another element. It will be understood that, for the purposes of this disclosure, "at least one of X, Y, and Z" can be interpreted as only X, only Y, only Z, or any combination of two or more items X, Y, and Z (e.g., XYZ, XYY, YZ, ZZ). Similarly, for the purposes of this disclosure, "at least one selected from the group consisting of X, Y, and Z" can be interpreted as only X, only Y, only Z, or any combination of two or more items X, Y, and Z (e.g., XYZ, XYY, YZ, ZZ).

[0048] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. Therefore, without departing from the teachings of this disclosure, the “first” element discussed below may also be referred to as the “second” element.

[0049] For ease of description, spatial relative terms such as “below” or “above” are used herein to describe the relationship between one element and another, as shown in the accompanying drawings. It will be understood that, in addition to the orientations described herein and depicted in the accompanying drawings, the spatial relative terms and the configurations shown are intended to cover different orientations of the device during use or operation. For example, if the device in the accompanying drawings is flipped, an element described as “below” or “under” other elements or features will subsequently be oriented “above” said other elements or features. Thus, the exemplary term “above” can cover both above and below orientations. The device may be otherwise oriented (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein will be interpreted accordingly.

[0050] Furthermore, the disclosed embodiments are described herein with reference to schematic diagrams of preferred embodiments (and intermediate structures) such that variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances can be anticipated. Therefore, embodiments of this disclosure should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations caused, for example, by manufacturing techniques. The regions shown in the figures are schematic in nature, and their shapes do not represent the actual shapes of regions of the device, nor do they limit the scope of the disclosure.

[0051] Figure 1 This is a block diagram illustrating a display device according to some embodiments of the present disclosure.

[0052] Reference Figure 1 The display device 100 may include a display panel 110, a gate driver 120, a data driver 130, a voltage generator 140, and a controller 150.

[0053] The display panel 110 may include sub-pixels SP. Sub-pixels SP can be connected to gate driver 120 via first gate line GL1 to m-th gate line GLm. Sub-pixels SP can be connected to data driver 130 via first data line DL1 to n-th data line DLn.

[0054] Each of the subpixels SP can include at least one light-emitting element configured to generate light. Therefore, each of the subpixels SP can produce light of a specific color (such as red, green, blue, cyan, magenta, or yellow). Two or more subpixels SP can constitute a pixel PXL. For example, as... Figure 1 As shown, three sub-pixels SP can form a pixel PXL.

[0055] Gate driver 120 can be connected to sub-pixels SP arranged in the row direction via first gate lines GL1 to m-th gate lines GLm. Gate driver 120 can output gate signals to first gate lines GL1 to m-th gate lines GLm in response to gate control signal GCS. In some embodiments, gate control signal GCS may include a start signal indicating the start of each frame, a horizontal synchronization signal for timing-synchronizing the output of gate signals with applied data signals, etc.

[0056] In some embodiments, first emission control lines EL1 to m-th emission control lines ELm connected to sub-pixels SP in the row direction may also be provided. Gate driver 120 may include emission control drivers configured to control the first emission control lines EL1 to m-th emission control lines ELm, and the emission control drivers may operate under the control of controller 150 (e.g., controlled by controller 150).

[0057] The gate driver 120 may be disposed on one side of the display panel 110. However, the embodiments are not limited thereto. For example, the gate driver 120 may be divided into two or more physically and / or logically separated drivers, and these drivers may be disposed on one side of the display panel 110 and on the opposite side of the display panel 110. Thus, in some embodiments, the gate driver 120 may be disposed in various forms at the periphery of the display panel 110.

[0058] Data driver 130 can be connected to sub-pixels SP arranged in the column direction via first data lines DL1 to nth data lines DLn. Data driver 130 can receive image data DATA and data control signal DCS from controller 150. Data driver 130 can operate in response to data control signal DCS. In some embodiments, data control signal DCS may include source start pulse, source shift clock, source output enable signal, etc.

[0059] The data driver 130 can apply a data signal with a grayscale voltage corresponding to the image data DATA to the first data lines DL1 to the nth data line DLn using a voltage from the voltage generator 140. When a gate signal is applied to each of the first gate lines GL1 to the mth gate line GLm, the data signal corresponding to the image data DATA can be applied to the data lines DL1 to DLn respectively. Therefore, the corresponding sub-pixel SP can generate light corresponding to the data signal. Thus, an image can be displayed on the display panel 110.

[0060] In some embodiments, gate driver 120 and data driver 130 may include complementary metal-oxide-semiconductor (CMOS) circuit elements.

[0061] Voltage generator 140 can operate in response to a voltage control signal VCS from controller 150. Voltage generator 140 can be configured to generate multiple voltages and provide the generated voltages to components of display device 100. For example, voltage generator 140 can be configured to generate multiple voltages by receiving an input voltage from outside display device 100, regulating the received voltage, and adjusting the regulated voltage.

[0062] Voltage generator 140 can generate a first electrical voltage VDD and a second electrical voltage VSS, and the generated first electrical voltage VDD and second electrical voltage VSS can be provided to sub-pixel SP. The first electrical voltage VDD can have a relatively high voltage level, and the second electrical voltage VSS can have a lower voltage level than the first electrical voltage VDD. In other embodiments, the first electrical voltage VDD or the second electrical voltage VSS can be provided by an external device of display device 100.

[0063] In some embodiments, voltage generator 140 can generate various voltages. For example, voltage generator 140 can generate an initialization voltage applied to the sub-pixel SP. For example, a set or predetermined reference voltage can be applied to the first data line DL1 to the nth data line DLn during a sensing operation for sensing the electrical characteristics of the transistor and / or light-emitting element of the sub-pixel SP, and voltage generator 140 can generate a reference voltage.

[0064] The controller 150 can control the overall operation of the display device 100. The controller 150 can receive control signals CTRL and input image data IMG from the outside for controlling the display of the display device 100. The controller 150 can provide gate control signal GCS, data control signal DCS and voltage control signal VCS in response to the control signal CTRL.

[0065] The controller 150 can convert the input image data IMG into a format suitable for the display device 100 or the display panel 110, thereby outputting image data DATA. In some embodiments, the controller 150 can align the input image data IMG to a format suitable for sub-pixels SP in rows, thereby outputting image data DATA.

[0066] Two or more of the components—data driver 130, voltage generator 140, and controller 150—may be mounted on an integrated circuit (e.g., connected to or within an integrated circuit). Figure 1As shown, the data driver 130, voltage generator 140, and controller 150 may be included in a driver integrated circuit (DIC). The data driver 130, voltage generator 140, and controller 150 may be functionally separated components within a single driver integrated circuit (DIC). In other embodiments, at least one of the data driver 130, voltage generator 140, and controller 150 may be provided as a component distinguishable from the driver integrated circuit (DIC) (e.g., separate from or outside the driver integrated circuit (DIC)).

[0067] The display device 100 may include at least one temperature sensor 160. The temperature sensor 160 may be configured to sense the temperature at its periphery and generate temperature data TEP indicating the sensed temperature. In some embodiments, the temperature sensor 160 may be positioned adjacent to the display panel 110 and / or the driver integrated circuit DIC.

[0068] The controller 150 can control various operations of the display device 100 in response to temperature data TEP. In some embodiments, the controller 150 can adjust the brightness of the image output from the display device 100 in response to the temperature data TEP. For example, the controller 150 can control components such as the data driver 130 and / or the voltage generator 140 to regulate the data signal and the first power voltage VDD and the second power voltage VSS.

[0069] Figure 2 This illustrates some embodiments according to the present disclosure. Figure 1 A block diagram of any of the sub-pixels shown. Figure 2 It shows Figure 1 The sub-pixel SPij shown is located in the i-th row (i is an integer greater than or equal to 1 and less than or equal to m) and the j-th column (j is an integer greater than or equal to 1 and less than or equal to n) of the sub-pixel SP.

[0070] Reference Figure 2 Subpixel SPij may include subpixel circuit SPC and light-emitting element LD.

[0071] The light-emitting element (LD) can be connected between the first power voltage node VDDN and the second power voltage node VSSN. The first power voltage node VDDN can be a transmission... Figure 1 The first power voltage node VDD shown in the diagram, and the second power voltage node VSSN can be the transmission node. Figure 1 The node of the second power voltage VSS is shown in the figure.

[0072] The anode electrode AE ​​of the light-emitting element LD can be connected to the first power voltage node VDDN via the sub-pixel circuit SPC, and the cathode electrode CE of the light-emitting element LD can be connected to the second power voltage node VSSN. For example, the anode electrode AE ​​of the light-emitting element LD can be connected to the first power voltage node VDDN via one or more transistors included in the sub-pixel circuit SPC.

[0073] Sub-pixel circuits (SPCs) can be connected to Figure 1 The i-th gate line GL1 to the m-th gate line GLm shown in the figure, Figure 1 The first transmit control line EL1 to the m-th transmit control line ELm shown in the figure, and the i-th transmit control line ELi, and Figure 1 The j-th data line DLj is shown among the first data lines DL1 to the nth data line DLn. The sub-pixel circuit SPC can be configured to control the light-emitting element LD based on the signals received through these signal lines.

[0074] The sub-pixel circuit (SPC) can operate in response to a gate signal received via the i-th gate line GLi. The i-th gate line GLi may include one or more sub-gate lines. In some embodiments, such as Figure 2 As shown, the i-th gate line GLi may include a first sub-gate line SGL1 and a second sub-gate line SGL2. The sub-pixel circuit SPC can operate in response to gate signals received through the first sub-gate line SGL1 and the second sub-gate line SGL2. Thus, when the i-th gate line GLi includes two or more sub-gate lines, the sub-pixel circuit SPC can operate in response to gate signals received through the respective sub-gate lines.

[0075] The sub-pixel circuit SPC can operate in response to a transmission control signal received via the i-th transmission control line ELi. In some embodiments, the i-th transmission control line ELi may include one or more sub-transmission control lines. When the i-th transmission control line ELi includes two or more sub-transmission control lines, the sub-pixel circuit SPC can operate in response to a transmission control signal received via the respective transmission control line.

[0076] The sub-pixel circuit SPC can receive a data signal via the j-th data line DLj. The sub-pixel circuit SPC can store a voltage corresponding to the data signal in response to at least one of the gate signals received via the first sub-gate line SGL1 and the second sub-gate line SGL2. The sub-pixel circuit SPC can control the current flowing from the first power voltage node VDDN through the light-emitting element LD to the second power voltage node VSSN based on the stored voltage, in response to the emission control signal received via the i-th emission control line ELi. Therefore, the light-emitting element LD can generate light with a brightness corresponding to the data signal.

[0077] Figure 3 This illustrates some embodiments according to the present disclosure. Figure 2 The circuit diagram of the sub-pixel is shown.

[0078] Reference Figure 3 Subpixel SPij may include subpixel circuit SPC and light-emitting element LD.

[0079] The sub-pixel circuit (SPC) can be connected to the i-th gate line GLi', the i-th emitter control line ELi', and the j-th data line DLj. When the i-th gate line GLi' is connected to... Figure 2 When comparing the i-th gate line GLi as shown, the i-th gate line GLi' may also include a third sub-gate line SGL3. When the i-th emitter control line ELi' is compared with... Figure 2 When comparing the i-th transmit control line ELi shown, the i-th transmit control line ELi' may include a first sub-transmit control line SEL1 and a second sub-transmit control line SEL2.

[0080] The sub-pixel circuit SPC may include a first transistor T1 to a sixth transistor T6, a first capacitor C1, and a second capacitor C2.

[0081] The first transistor T1 can be connected between the first power voltage node VDDN and the first node N1. The gate of the first transistor T1 can be connected to the second node N2, therefore, the first transistor T1 can be turned on according to the voltage level of the second node N2. The first transistor T1 can be designated as a driving transistor.

[0082] The second transistor T2 can be connected between the j-th data line DLj and the second node N2. The gate of the second transistor T2 can be connected to the first sub-gate line SGL1, therefore, the second transistor T2 can be turned on in response to the gate signal of the first sub-gate line SGL1. The second transistor T2 can be designated as a switching transistor.

[0083] The third transistor T3 can be connected between the first node N1 and the second node N2. The gate of the third transistor T3 can be connected to the second sub-gate line SGL2, so the third transistor T3 can be turned on in response to the gate signal of the second sub-gate line SGL2.

[0084] The fourth transistor T4 can be connected between the first node N1 and the anode electrode AE ​​of the light-emitting element LD. The gate of the fourth transistor T4 can be connected to the second sub-emission control line SEL2. Therefore, the fourth transistor T4 can be turned on in response to the emission control signal of the second sub-emission control line SEL2.

[0085] The fifth transistor T5 can be connected between the anode electrode AE ​​of the light-emitting element LD and the initialization voltage node VINTN. The initialization voltage node VINTN can be configured to transmit the initialization voltage. In some embodiments, the initialization voltage can be supplied by... Figure 1 The voltage generator 140 shown provides the initialization voltage. In other embodiments, the initialization voltage may be provided by an external device of the display device 100. The gate of the fifth transistor T5 may be connected to the third sub-gate line SGL3, so that the fifth transistor T5 may be turned on in response to the gate signal of the third sub-gate line SGL3.

[0086] The sixth transistor T6 can be connected between the first power voltage node VDDN and the first transistor T1. The gate of the sixth transistor T6 can be connected to the first sub-emitter control line SEL1, so the sixth transistor T6 can be turned on in response to the emitter control signal of the first sub-emitter control line SEL1.

[0087] The first capacitor C1 can be connected between the second transistor T2 and the second node N2. The second capacitor C2 can be connected between the first power voltage node VDDN and the second node N2.

[0088] Thus, the sub-pixel circuit SPC may include first transistors T1 to sixth transistors T6, and first capacitor C1 and second capacitor C2. However, the embodiments are not limited thereto. The sub-pixel circuit SPC can be implemented as any of various types of circuits, each including multiple transistors and one or more capacitors. For example, the sub-pixel circuit SPC may include two transistors and one capacitor. Depending on the embodiment of the sub-pixel circuit SPC, the number of sub-gate lines included in the i-th gate line GLi' and the number of sub-emission control lines included in the i-th emission control line ELi' can vary.

[0089] The first transistor T1 through the sixth transistor T6 can be P-type transistors. Each of the first transistor T1 through the sixth transistor T6 can be a metal-oxide-semiconductor field-effect transistor (MOSFET). However, the embodiments are not limited thereto. For example, at least one of the first transistor T1 through the sixth transistor T6 can be replaced with an N-type transistor.

[0090] In some embodiments, the first transistor T1 to the sixth transistor T6 may include amorphous silicon semiconductor, single-crystal silicon semiconductor, polycrystalline silicon semiconductor, oxide semiconductor, etc.

[0091] The light-emitting element (LD) may include an anode electrode AE, a cathode electrode CE, and a light-emitting layer. The light-emitting layer may be disposed between the anode electrode AE ​​and the cathode electrode CE. After the data signal transmitted through the j-th data line DLj is reflected in the voltage of the second node N2, the fourth transistor T4 and the sixth transistor T6 may be turned on when the emission control signals of the first sub-emission control line SEL1 and the second sub-emission control line SEL2 are enabled to a low level. The first transistor T1 may be turned on according to the voltage of the second node N2, thus allowing current to flow from the first power voltage node VDDN to the second power voltage node VSSN. The light-emitting element LD may emit light according to the amount of current flowing from the first power voltage node VDDN to the second power voltage node VSSN.

[0092] Figure 4 This illustrates some embodiments according to the present disclosure. Figure 1 The plan view of the display panel is shown.

[0093] Reference Figure 4 ,and Figure 1 The display panel DP corresponding to the display panel 110 shown may include a display area DA and a non-display area NDA. The display panel DP can display images through the display area DA. The non-display area NDA can be located at the periphery of the display area DA.

[0094] The display panel DP may include a substrate SUB, subpixels SP, and pads (also known as solder pads or solder pads) PD. When the display panel DP is used as a display screen for head-mounted display (HMD) devices, virtual reality (VR) devices, mixed reality (MR) devices, augmented reality (AR) devices, etc., the display panel DP can be positioned very close to the user's eyes. A relatively high degree of integration of the subpixels SP may be required. To increase the integration of the subpixels SP, the substrate SUB may be a silicon substrate. The subpixels SP and / or the display panel DP may be formed on the substrate SUB, which is a silicon substrate. A display device 100 including a display panel DP formed on a substrate SUB, which is a silicon substrate (see...) Figure 1 It can be designated as an OLED on silicon (OLEDoS) display device.

[0095] Subpixels SP can be disposed on the substrate SUB in the display area DA. Subpixels SP can be arranged in a matrix along a first direction DR1 and a second direction DR2 intersecting the first direction DR1. However, the embodiments are not limited to this. For example, subpixels SP can be arranged in a zigzag pattern along the first direction DR1 and the second direction DR2. For example, subpixels SP can be arranged in a pentiline pattern. ®(Trademark of Samsung Display Co., Ltd.) The subpixels SP can be arranged in an RGBG matrix structure. The first direction DR1 can be the row direction, and the second direction DR2 can be the column direction.

[0096] Two or more sub-pixels SP can form a pixel PXL.

[0097] Components used to control subpixels SP can be set on the substrate SUB in the non-display area NDA. For example, lines connected to subpixels SP (such as...) Figure 1 The first gate line GL1 to the m-th gate line GLm and the first data line DL1 to the n-th data line DLn shown can be set in the non-display area NDA.

[0098] Figure 1 At least one of the gate driver 120, data driver 130, voltage generator 140, controller 150, and temperature sensor 160 shown may be integrated into the non-display area NDA of the display panel DP. In some embodiments, Figure 1 The gate driver 120 shown is mounted on the display panel DP and may be located in the non-display area NDA. In other embodiments, the gate driver 120 may be implemented as an integrated circuit separate from the display panel DP. In some embodiments, a temperature sensor 160 may be located in the non-display area NDA to sense the temperature of the display panel DP.

[0099] The pad PD can be positioned on the substrate SUB within the non-display area NDA. The pad PD can be electrically connected to the sub-pixel SP via wirelines. For example, the pad PD can be connected to the sub-pixel SP via first data lines DL1 to nth data lines DLn.

[0100] The pad PD can connect the display panel DP to the display device 100 (see...) Figure 1 Other components of the display panel (DP) are coupled together. In some embodiments, voltages and signals for the operation of components included in the display panel (DP) can be transmitted from the PD via pads. Figure 1 The driver integrated circuit DIC shown is provided. For example, the first data line DL1 to the nth data line DLn can be connected to the driver integrated circuit DIC via the pad PD. For example, a first power voltage VDD and a second power voltage VSS can be received from the driver integrated circuit DIC via the pad PD. When the gate driver 120 is mounted in the display panel DP, the gate control signal GCS can be transmitted from the driver integrated circuit DIC to the gate driver 120 via the pad PD.

[0101] In some embodiments, the circuit board may be electrically connected to the pad PD using conductive adhesive members, such as anisotropic conductive films. The circuit board may be a flexible printed circuit board (FPCB) or a flexible film made of flexible material. The driver integrated circuit (DIC) may be mounted on the circuit board for electrical connection to the pad PD.

[0102] In some embodiments, the display area DA can have various suitable shapes. The display area DA can have a closed-loop shape including linear edges and / or curved edges. For example, the display area DA can have shapes such as polygons, circles, semicircles, and ellipses.

[0103] In some embodiments, the display panel DP may have a flat display surface. In other embodiments, the display panel DP may have at least a partially circular display surface. In some embodiments, the display panel DP may be flexible, foldable, and / or rollable. The display panel DP and / or the substrate SUB may include a flexible material.

[0104] Figure 5 This illustrates some embodiments according to the present disclosure. Figure 4 An exploded perspective view of a portion of the display panel shown. Figure 5 For clarity and brevity, the display panel DP can be schematically shown in the diagram. Figure 4 The portion corresponding to pixels PXL1 and PXL2 in pixel PXL shown is illustrated. The portions corresponding to other pixels in the display panel DP can also be constructed in the same way.

[0105] Reference Figure 4 and Figure 5 Each of the first pixel PXL1 and the second pixel PXL2 may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. However, the embodiments are not limited thereto. For example, each of the first pixel PXL1 and the second pixel PXL2 may include four sub-pixels, or two sub-pixels.

[0106] exist Figure 5 The diagram illustrates that, when viewed from a third direction DR3 intersecting the first direction DR1 and the second direction DR2 (e.g., in a planar view), the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can have quadrilateral shapes and have the same or substantially the same dimensions. However, the embodiment is not limited to this. The first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can be modified to have various shapes.

[0107] The display panel (DP) may include a substrate (SUB), a pixel circuit layer (PCL), a light-emitting element layer (LDL), a packaging layer (TFE), an optical functional layer (OFL), an outer coating layer (OC), and a cover window (CW).

[0108] In some embodiments, the substrate SUB may include a silicon wafer substrate formed using semiconductor processes. The substrate SUB may include a semiconductor material suitable for forming circuit elements. For example, the semiconductor material may include silicon, germanium, and / or silicon-germanium. The substrate SUB may be disposed of as a body wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, a semiconductor-on-insulator (SeOI) layer, etc. In other embodiments, the substrate SUB may include a glass substrate. In still other embodiments, the substrate SUB may include a polyimide (PI) substrate.

[0109] The pixel circuit layer (PCL) can be disposed on the substrate (SUB). The substrate (SUB) and / or the pixel circuit layer (PCL) may include an insulating layer and a conductive pattern disposed between the insulating layer. The conductive pattern of the pixel circuit layer (PCL) can be used as at least some of circuit elements, lines, etc. The conductive pattern may include copper, but the embodiments are not limited thereto.

[0110] The circuit elements may include a sub-pixel circuit SPC for each of the first sub-pixel SP1 to the third sub-pixel SP3 (see Figure 2 The sub-pixel circuit (SPC) may include a transistor and one or more capacitors. Each transistor may include a semiconductor portion comprising a source region, a drain region, and a channel region, and a gate electrode stacked with the semiconductor portion. In some embodiments, when the substrate SUB is a silicon substrate, the semiconductor portion may be included in the substrate SUB, and the gate electrode may be included in the pixel circuit layer PCL as a conductive pattern in the pixel circuit layer PCL. In some embodiments, when the substrate SUB is a glass substrate or a PI substrate, the semiconductor portion and the gate electrode may be included in the pixel circuit layer PCL. Each capacitor may include electrodes spaced apart from each other. For example, each capacitor may include electrodes spaced apart from each other on a plane defined by a first direction DR1 and a second direction DR2. For example, a capacitor may include electrodes spaced apart from each other on a third direction DR3 with an insulating layer inserted therebetween.

[0111] The lines of the pixel circuit layer (PCL) may include signal lines, such as gate lines, emit control lines, data lines, etc., connected to each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. The lines may also include connections to... Figure 2 The line shown is the first power voltage node VDDN. The line may also include connections to... Figure 2 The line of the second power voltage node VSSN shown in the figure.

[0112] The light-emitting element layer (LDL) may include an anode electrode (AE), a pixel-defining layer (PDL), a light-emitting structure (EMS), and a cathode electrode (CE).

[0113] The anode electrode AE ​​can be disposed on the pixel circuit layer PCL. The anode electrode AE ​​can contact the circuit elements of the pixel circuit layer PCL. The anode electrode AE ​​can include an opaque conductive material capable of reflecting light, but the embodiments are not limited thereto.

[0114] A pixel-defining layer (PDL) may be disposed above an anode electrode (AE). The PDL may include an opening (OP) that exposes a portion of each of the anode electrodes (AE). The opening (OP) of the PDL can be understood as an emission region corresponding to each of the first sub-pixel (SP1), the second sub-pixel (SP2), and the third sub-pixel (SP3).

[0115] In some embodiments, the pixel-defining layer (PDL) may include an inorganic material. The PDL may include multiple stacked inorganic layers. For example, the PDL may include silicon oxide (SiO2). x ) and silicon nitride (SiN) x In other embodiments, the pixel defining layer (PDL) may include an organic material. However, the material of the pixel defining layer (PDL) is not limited thereto.

[0116] The light-emitting structure (EMS) can be disposed on the anode electrode (AE) exposed by the opening (OP) of the pixel-defining layer (PDL). The light-emitting structure (EMS) may include a light-emitting layer configured to generate light, an electron transport layer configured to transport electrons, a hole transport layer configured to transport holes, etc.

[0117] In some embodiments, the light-emitting structure EMS fills the opening OP of the pixel-defining layer PDL and can be disposed entirely on top of the pixel-defining layer PDL (e.g., completely covering the pixel-defining layer PDL). In other words, the light-emitting structure EMS can extend across the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. At least some of the layers in the light-emitting structure EMS can be cut or bent at the boundaries between the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. However, the embodiments are not limited to this. For example, the portions of the light-emitting structure EMS corresponding to the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can be separated from each other, and each of these portions can be disposed within the opening OP of the pixel-defining layer PDL.

[0118] The cathode electrode CE can be disposed on the light-emitting structure EMS. The cathode electrode CE can extend across the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. Thus, the cathode electrode CE can be configured as a common electrode for the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3.

[0119] The cathode electrode CE can be a thin metal layer with a thickness sufficient to allow light emitted from the light-emitting structure EMS to pass through. The cathode electrode CE can be formed of a metallic material to have a relatively thin thickness, or it can be formed of a transparent conductive material. In some embodiments, the cathode electrode CE may include at least one of various transparent conductive materials, including indium tin oxide, indium zinc oxide, indium tin zinc oxide, aluminum zinc oxide, gallium zinc oxide, zinc tin oxide, and gallium tin oxide. In other embodiments, the cathode electrode CE may include at least one of silver (Ag), magnesium (Mg), and mixtures thereof. However, the material of the cathode electrode CE is not limited to these.

[0120] It is understandable that any one of the anode electrodes AE, the portion of the light-emitting structure EMS superimposed on it, and the portion of the cathode electrode CE superimposed on it constitute a light-emitting element LD (see...). Figure 2 In other words, each of the light-emitting elements of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may include an anode electrode AE, a portion of the light-emitting structure EMS superimposed thereon, and a portion of the cathode electrode CE superimposed thereon. In each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, holes injected from the anode electrode AE ​​and electrons injected from the cathode electrode CE can be transported to the light-emitting layer of the light-emitting structure EMS to form excitons, and light can be generated when the excitons transition from the excited state to the ground state. The brightness of the light can be determined based on the amount of current flowing through the light-emitting layer. The wavelength of the generated light can be determined based on the structure of the light-emitting layer.

[0121] The encapsulation layer TFE can be disposed above the cathode electrode CE. The encapsulation layer TFE can cover the light-emitting element layer LDL and / or the pixel circuit layer PCL. The encapsulation layer TFE can be configured to prevent oxygen and / or moisture from penetrating into the light-emitting element layer LDL. In some embodiments, the encapsulation layer TFE may include a structure in which at least one inorganic layer and at least one organic layer are alternately stacked. For example, the inorganic layer may include silicon nitride, silicon oxide, silicon oxynitride (SiO2), etc. x N y For example, the organic layer may include organic insulating materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene sulfide resin, or benzocyclobutene (BCB). However, the materials of the organic and inorganic layers of the encapsulation layer TFE are not limited to these.

[0122] To improve the packaging efficiency of the TFE encapsulation layer, the TFE encapsulation layer may also include aluminum oxide (AlO2). xThe thin film, including aluminum oxide, may be located on the top surface of the encapsulation layer TFE facing the optical functional layer OFL and / or on the bottom surface of the encapsulation layer TFE facing the light-emitting element layer LDL.

[0123] Thin films including alumina can be formed using an atomic layer deposition (ALD) process. However, the embodiments are not limited thereto. The encapsulation layer TFE may also comprise a thin film formed from at least one of a variety of materials suitable for improving encapsulation efficiency.

[0124] The optical functional layer (OFL) can be disposed on the encapsulation layer (TFE). The optical functional layer (OFL) may include a color filter layer (CFL) and a lens array (LA).

[0125] A color filter layer (CFL) can be disposed between the encapsulation layer (TFE) and the lens array (LA). The CFL can be configured to filter light emitted from the light-emitting structure (EMS), thereby selectively outputting light of a wavelength or color corresponding to each sub-pixel (SP). The CFL may include color filters (CF) corresponding to the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, respectively. Each of the color filters (CF) can allow light with a wavelength corresponding to the respective sub-pixel to pass through it. For example, the color filter (CF) corresponding to the first sub-pixel SP1 can allow red light to pass through it, the color filter (CF) corresponding to the second sub-pixel SP2 can allow green light to pass through it, and the color filter (CF) corresponding to the third sub-pixel SP3 can allow blue light to pass through it. Depending on the light emitted from the light-emitting structure (EMS) in each sub-pixel SP, at least some of the color filters (CF) may be omitted.

[0126] A lens array LA can be disposed on the color filter layer CFL. The lens array LA may include lenses LS corresponding to the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, respectively. Each of the lenses LS can output light emitted from the light-emitting structure EMS along a desired path, thereby improving light emission efficiency. The lens array LA can have a relatively high refractive index. For example, the lens array LA can have a higher refractive index than the outer coating OC. In some embodiments, the lenses LS may include organic materials. In some embodiments, the lenses LS may include acrylamide materials. However, the materials of the lenses LS are not limited to these.

[0127] In some embodiments, at least some of the color filters CF of the color filter layer CFL and at least some of the lenses LS of the lens array LA may be shifted in a direction parallel to the plane defined by the first direction DR1 and the second direction DR2, compared to the opening OP of the pixel defining layer PDL. For example, in the central region of the display area DA, the center of the color filter CF and the center of the lens LS may be aligned with or superimposed on the center of the corresponding opening OP of the pixel defining layer PDL. For example, in the central region of the display area DA, the opening OP of the pixel defining layer PDL may be completely superimposed on the corresponding color filter CF of the color filter layer CFL and the corresponding lens LS of the lens array LA. In the region of the display area DA adjacent to the non-display area NDA, the center of the color filter CF and the center of the lens LS may be shifted from the center of the opening OP of the pixel defining layer PDL in a planar direction. For example, in the region of the display area DA adjacent to the non-display area NDA, the opening OP of the pixel defining layer PDL may be partially superimposed on the corresponding color filter CF of the color filter layer CFL and the corresponding lens LS of the lens array LA. Therefore, at the center of the display area DA, the light emitted from the light-emitting structure EMS can be effectively output in the normal direction of the display surface. Outside the display area DA, the light emitted from the light-emitting structure EMS can be effectively output in a direction tilted at a predetermined angle relative to the normal direction of the display surface.

[0128] An outer coating OC can be disposed on top of the lens array LA. The outer coating OC can cover the optical functional layer OFL, the encapsulation layer TFE, the light-emitting structure EMS, and / or the pixel circuit layer PCL. The outer coating OC can include various materials suitable for protecting the underlying layers from foreign matter such as dust and moisture. For example, the outer coating OC can include at least one of an inorganic insulating layer and an organic insulating layer. For example, the outer coating OC can include epoxy resin, but the embodiments are not limited thereto. The outer coating OC can have a refractive index lower than that of the lens array LA.

[0129] A cover window (CW) may be disposed on the outer coating (OC). The cover window (CW) may be configured to protect the layer beneath it. The cover window (CW) may have a higher refractive index than the outer coating (OC). The cover window (CW) may include glass, but embodiments are not limited thereto. For example, the cover window (CW) may be encapsulation glass configured to protect components disposed beneath it. In other embodiments, the cover window (CW) may be omitted.

[0130] Figure 6 This illustrates some embodiments according to the present disclosure. Figure 5 A planar view of one of the pixels shown. Figure 6 For clarity and brevity, the diagram is shown schematically. Figure 5The first pixel PXL1 is shown as the first pixel of the first pixel PXL1 and the second pixel PXL2 shown. The other pixels can be constructed in the same way as the first pixel PXL1.

[0131] Reference Figure 5 and Figure 6 The first pixel PXL1 may include a first sub-pixel SP1, a second sub-pixel SP2 and a third sub-pixel SP3 arranged on the first direction DR1.

[0132] The first sub-pixel SP1 may include a first emitting region EMA1 and a non-emitting region NEA located around (e.g., around or surrounding) the first emitting region EMA1. The second sub-pixel SP2 may include a second emitting region EMA2 and a non-emitting region NEA located around the second emitting region EMA2. The third sub-pixel SP3 may include a third emitting region EMA3 and a non-emitting region NEA located around the third emitting region EMA3.

[0133] The first emitting region EMA1 can be where light is emitted from the light-emitting structure EMS (see...). Figure 5 The second emission region EMA2 can be the region in which light is emitted from the portion of the light-emitting structure EMS corresponding to the second sub-pixel SP1. The third emission region EMA3 can be the region in which light is emitted from the portion of the light-emitting structure EMS corresponding to the third sub-pixel SP3. (See reference...) Figure 5 As described, the first emission region EMA1, the second emission region EMA2, and the third emission region EMA3 can be understood as the openings OP of the pixel-defined layer PDL corresponding to the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, respectively.

[0134] Figure 7 It is according to some embodiments of this disclosure along Figure 6 The sectional view shown is taken by line I-I'. Figure 8 and Figure 9 This illustrates some embodiments according to the present disclosure. Figure 7 An enlarged cross-sectional view of a portion of the light-emitting element layer shown.

[0135] Reference Figures 7 to 9 It can set the base SUB and the pixel circuit layer PCL set on the base SUB.

[0136] The substrate SUB may include a silicon wafer substrate formed using semiconductor processes. For example, the substrate SUB may include silicon, germanium, and / or silicon-germanium.

[0137] The pixel circuit layer (PCL) can be disposed on the substrate SUB. The substrate SUB and the pixel circuit layer PCL can include circuit elements for each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. For example, the substrate SUB and the pixel circuit layer PCL can include transistor T_SP1 for the first sub-pixel SP1, transistor T_SP2 for the second sub-pixel SP2, and transistor T_SP3 for the third sub-pixel SP3. Transistor T_SP1 of the first sub-pixel SP1 can be a sub-pixel circuit (SPC) included in the first sub-pixel SP1 (see...). Figure 2 The transistor T_SP2 of the second sub-pixel SP2 can be any one of the transistors included in the sub-pixel circuit SPC of the second sub-pixel SP2, and the transistor T_SP3 of the third sub-pixel SP3 can be any one of the transistors included in the sub-pixel circuit SPC of the third sub-pixel SP3. Figure 7 For clarity and brevity, only one transistor for each subpixel is shown, and other circuit elements are omitted.

[0138] The transistor T_SP1 of the first sub-pixel SP1 may include the source region SRA, the drain region DRA, and the gate electrode GE.

[0139] The source region (SRA) and drain region (DRA) can be located within the substrate (SUB). A well (WL) formed by ion implantation can also be located within the substrate (SUB), with the source region (SRA) and drain region (DRA) spaced apart from each other. The region between the source region (SRA) and drain region (DRA) within the well (WL) can be defined as the channel region.

[0140] The gate electrode GE can be stacked with the channel region between the source region SRA and the drain region DRA, and is disposed in the pixel circuit layer PCL. The gate electrode GE can be separated from the well region WL or the channel region by an insulating material such as the gate insulating layer GI. The gate electrode GE may include a conductive material.

[0141] The multiple layers included in the pixel circuit layer PCL may include insulating layers and conductive patterns disposed between the insulating layers, and the conductive patterns may include a first conductive pattern CP1 and a second conductive pattern CP2. The first conductive pattern CP1 may be electrically connected to the drain region DRA through a drain connection DRC that penetrates one or more insulating layers. The second conductive pattern CP2 may be electrically connected to the source region SRA through a source connection SRC that penetrates one or more insulating layers.

[0142] Since the gate electrode GE and the first conductive pattern CP1 and the second conductive pattern CP2 are connected to other circuit elements and / or lines, the transistor T_SP1 of the first sub-pixel SP1 can be set to any one of the transistors of the first sub-pixel SP1.

[0143] Each of the transistors T_SP2 of the second sub-pixel SP2 and T_SP3 of the third sub-pixel SP3 can be constructed in the same way as the transistor T_SP1 of the first sub-pixel SP1.

[0144] Thus, the base SUB and / or pixel circuit layer PCL may include circuit elements of each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3.

[0145] A via layer (VIAL) can be disposed on the pixel circuit layer (PCL). The via layer (VIAL) covers the pixel circuit layer (PCL) and can have an entirely flat surface. The via layer (VIAL) can be configured to planarize step differences on the pixel circuit layer (PCL). The via layer (VIAL) can include silicon oxide (SiO2). x Silicon nitride (SiN) x The embodiments may contain at least one of silicon oxynitride (SiCN) and silicon oxynitride (SiCN), but the embodiments are not limited thereto.

[0146] Reference Figures 7 to 9 The light-emitting element layer (LDL) can be disposed on the via layer (VIAL). The light-emitting element layer (LDL) may include blocking layers BR, BR1 and BR2, a first reflective electrode RE1, a second reflective electrode RE2 and a third reflective electrode RE3, a first resonant layer RS1, a second resonant layer RS2 and a third resonant layer RS3, a first anode electrode AE1 to a third anode electrode AE3, a pixel limiting layer (PDL), a light-emitting structure (EMS) and / or a cathode electrode CE.

[0147] Reference Figure 8 The barrier layer BR can be disposed in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, respectively. The barrier layer BR can be disposed on the via layer VIAL. The barrier layer BR can improve the electrical connection characteristics between the first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3 and the circuit elements of the pixel circuit layer PCL. In some embodiments, the barrier layer BR can have a multilayer structure. The multilayer structure of the barrier layer BR may include titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), etc., but this disclosure is not limited to these. The barrier layer BR of each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can contact the circuit elements disposed in the pixel circuit layer PCL through the vias penetrating the via layer VIAL.

[0148] Reference Figure 9The first barrier layer BR1 may be disposed on the bottom of the first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3, and the second barrier layer BR2 may be disposed on the top of the first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3. The thickness of each of the first barrier layers BR1 on the third-direction DR3 may be greater than the thickness of each of the second barrier layers BR2 on the third-direction DR3; however, this disclosure is not limited thereto. In some embodiments, the first barrier layer BR1 and / or the second barrier layer BR2 may have a multilayer structure. The multilayer structure of the first barrier layer BR1 and / or the second barrier layer BR2 may include titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), etc., but this disclosure is not limited thereto.

[0149] The first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3 can be disposed on the blocking layer BR or the first blocking layer BR1. The first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3 can be disposed in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, respectively.

[0150] The first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3 can be used as a total reflection mirror, which reflects light emitted from the light-emitting structure EMS toward the display surface (or the cover window CW). The first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3 can include metallic materials suitable for reflecting light. The first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3 can include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), and titanium (Ti), as well as alloys selected from two or more of these materials, but the embodiments are not limited thereto.

[0151] The first resonant layer RS1, the second resonant layer RS2, and the third resonant layer RS3 can be disposed on the first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3 or the second blocking layer BR2. The first resonant layer RS1, the second resonant layer RS2, and the third resonant layer RS3 can be disposed in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, respectively.

[0152] The first resonant layer RS1, the second resonant layer RS2, and the third resonant layer RS3 may include materials such as silicon oxide (SiO2). xThe present disclosure is not limited to inorganic materials. The first resonant layer RS1, the second resonant layer RS2, and the third resonant layer RS3 can be used to adjust the resonant distance so that light can be output in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 under optimal resonant conditions. For example, the first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3 can be used as total reflection mirrors, and the cathode electrode CE can be used as a half-reflective mirror. Light emitted from the light-emitting layer of the light-emitting structure EMS can be amplified by at least partially reciprocating between each of the first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3 and the cathode electrode CE, and the amplified light can be output through the cathode electrode CE. Thus, the distance between each of the first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3 and the cathode electrode CE can be understood as the resonant distance of light emitted from the light-emitting layer of the corresponding light-emitting structure EMS.

[0153] In some embodiments, the thicknesses t1, t2, and t3 of the first resonant layer RS1, the second resonant layer RS2, and the third resonant layer RS3 on the third-direction DR3 can be different from each other. For example, the thickness t1 of the first resonant layer RS1 on the third-direction DR3 can be less than the thickness t2 of the second resonant layer RS2 on the third-direction DR3. Therefore, the first sub-pixel SP1 can have a shorter resonant distance than the second sub-pixel SP2. The thickness t2 of the second resonant layer RS2 on the third-direction DR3 can be less than the thickness t3 of the third resonant layer RS3 on the third-direction DR3. Therefore, the second sub-pixel SP2 can have a shorter resonant distance than the third sub-pixel SP3. This adjusted resonant distance allows light within a specific wavelength range to be effectively and efficiently amplified in each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. Therefore, because each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can effectively and efficiently output light in its corresponding wavelength band, the brightness of the display device can be improved.

[0154] The first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 can be disposed on the first resonant layer RS1, the second resonant layer RS2, and the third resonant layer RS3, respectively. The first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 can be disposed in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, respectively.

[0155] When viewed on a third-party DR3, the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 can have the same characteristics as... Figure 6The first emitting region EMA1, the second emitting region EMA2, and the third emitting region EMA3 shown have similar shapes. The first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 can be electrically connected to the first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3, respectively. For example, the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 can respectively cover the top and side surfaces of the first resonant layer RS1, the second resonant layer RS2, and the third resonant layer RS3, and respectively cover the sides of the first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3 disposed below the first resonant layer RS1, the second resonant layer RS2, and the third resonant layer RS3. The first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 can be directly disposed on the top and side surfaces of the first resonant layer RS1, the second resonant layer RS2, and the third resonant layer RS3, respectively, to contact the top and side surfaces of the first resonant layer RS1, the second resonant layer RS2, and the third resonant layer RS3. The first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 can be directly disposed on the side surfaces of the first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3, respectively, so as to contact the side surfaces of the first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3.

[0156] In some embodiments, the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 may comprise at least one of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), and indium tin zinc oxide (ITZO). However, the materials of the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 are not limited thereto. For example, the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 may comprise titanium nitride.

[0157] A pixel defining layer (PDL) can be disposed over the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3. The PDL may include a first opening OP1, a second opening OP2, and a third opening OP3 that respectively expose portions of the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3. The first opening OP1, the second opening OP2, and the third opening OP3 of the PDL can respectively define the emission regions of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. Thus, the pixel defining layer (PDL) can be disposed over the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3. Figure 6 In the non-emission region NEA shown, to define Figure 6The first transmission area EMA1, the second transmission area EMA2, and the third transmission area EMA3 are shown in the diagram.

[0158] In some embodiments, the pixel defining layer (PDL) may include multiple inorganic insulating layers. For example, the pixel defining layer (PDL) may include a first layer L1 disposed on anode electrodes AE1, AE2, and AE3, and a second layer L2 disposed on the first layer L1. The thickness of the first layer L1 on the third-direction DR3 may be different from the thickness of the second layer L2 on the third-direction DR3. For example, the thickness of the first layer L1 on the third-direction DR3 may be less than the thickness of the second layer L2 on the third-direction DR3. The first layer L1 and / or the second layer L2 may include silicon oxide (SiO2). x ) and silicon nitride (SiN) x At least one of the following. In the example, the first layer L1 may be made of silicon nitride (SiN). x The second layer L2 can be formed from silicon dioxide (SiO2). x The first layer L1 can be formed. However, this disclosure is not limited thereto. The first layer L1 can be used as an etch stop in the process of polishing the pixel-defined layer PDL. This will be discussed later. Figure 22 Describe it.

[0159] Due to the thickness difference between the first resonant layer RS1, the second resonant layer RS2, and the third resonant layer RS3, the first opening OP1, the second opening OP2, and the third opening OP3 of the pixel limiting layer PDL can have different depths. For example, when the thickness t1 of the first resonant layer RS1 on the third-direction DR3 is less than the thickness t2 of the second resonant layer RS2 on the third-direction DR3, the depth D1 of the first opening OP1 on the third-direction DR3 can be greater than the depth D2 of the second opening OP2 on the third-direction DR3. When the thickness t2 of the second resonant layer RS2 on the third-direction DR3 is less than the thickness t3 of the third resonant layer RS3 on the third-direction DR3, the depth D2 of the second opening OP2 on the third-direction DR3 can be greater than the depth D3 of the third opening OP3 on the third-direction DR3. In this example, the depth D3 of the third opening OP3 on the third-direction DR3 can be substantially equal to the thickness of the first layer L1 on the third-direction DR3.

[0160] In some embodiments, the separator SPR can be disposed in the boundary region BDA between adjacent sub-pixels SP1, SP2, and SP3. The separator SPR can cause discontinuities in the light-emitting structure EMS within the boundary region BDA. For example, the light-emitting structure EMS can be cut or bent by the separator SPR within the boundary region BDA.

[0161] The separator SPR can be disposed in or on the pixel-defining layer PDL. The pixel-defining layer PDL may include one or more trenches TRCH1 and TRCH2 as separator SPRs. In some embodiments, such as Figure 7 As shown, one or more trenches TRCH1 and TRCH2 can penetrate the pixel-defining layer PDL and partially penetrate the via layer VIAL.

[0162] exist Figures 7 to 9 The diagram illustrates two trenches, TRCH1 and TRCH2, within the boundary region BDA. However, the embodiment is not limited to this. For example, the pixel-defining layer PDL may include one trench within the boundary region BDA. Alternatively, the pixel-defining layer PDL may include three or more trenches within the boundary region BDA.

[0163] Due to the first trench TRCH1 and the second trench TRCH2, discontinuities such as the first gap VD1 and the second gap VD2 can be formed in the boundary region BDA within the light-emitting structure EMS. Some of the multiple layers stacked in the light-emitting structure EMS can be cut or bent by the first gap VD1 and the second gap VD2. For example, at least one charge-generating layer included in the light-emitting structure EMS can be cut by the first gap VD1 and the second gap VD2. Thus, due to the first trench TRCH1 and the second trench TRCH2, portions of the light-emitting structure EMS included in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can be at least partially separated from each other.

[0164] exist Figure 7 The diagram illustrates the formation of a first gap VD1 and a second gap VD2 in the boundary region BDA within the light-emitting structure EMS. However, this is merely illustrative, and the embodiments are not limited thereto. For example, concave valleys may be formed in the boundary region BDA within the light-emitting structure EMS. The discontinuities formed in the light-emitting structure EMS can be appropriately varied depending on the shapes of the first trench TRCH1 and the second trench TRCH2.

[0165] In some embodiments, the light-emitting structure EMS can be formed by processes such as vacuum deposition or inkjet printing. The same material as the light-emitting structure EMS can be located on the bottom surface adjacent to the via layer VIAL in the first trench TRCH1 and the second trench TRCH2.

[0166] The separator SPR can be modified appropriately to allow the light-emitting structure EMS to have discontinuities in the boundary region BDA. In some embodiments, additional inorganic insulating patterns stacked on the pixel defining layer PDL can be provided in the boundary region BDA without the first trench TRCH1 and the second trench TRCH2. The width of the uppermost inorganic insulating pattern among the additionally stacked inorganic insulating patterns can be greater than the width of the inorganic insulating pattern immediately below the uppermost inorganic insulating pattern. For example, in the boundary region BDA, the first to third inorganic insulating patterns can be sequentially stacked from the pixel defining layer PDL, and the third inorganic insulating pattern at the uppermost position can have a width greater than the width of the second inorganic insulating layer. For example, the pixel defining layer PDL can have portions in the boundary region BDA that have a "T" shape or an "I" shape. Depending on the shape of the pixel defining layer PDL, multiple layers included in the light-emitting structure EMS can be partially cut or bent in the boundary region BDA.

[0167] The light-emitting structure EMS can be disposed on the anode electrode AE ​​and / or the pixel defining layer PDL. The light-emitting structure EMS can be disposed on the anode electrode AE ​​exposed by the opening OP of the pixel defining layer PDL. The light-emitting structure EMS can fill the opening OP of the pixel defining layer PDL and can be disposed throughout the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 (e.g., an overall arrangement throughout the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3). As described above, the light-emitting structure EMS can be at least partially cut or bent in the boundary region BDA by the separator SPR. Therefore, during the operation of the display panel DP, the current leakage from each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 through the layers included in the light-emitting structure EMS to its adjacent sub-pixel can be reduced or minimized. Therefore, the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 can operate with relatively high reliability.

[0168] The cathode electrode CE can be disposed on the light-emitting structure EMS. The cathode electrode CE can be commonly disposed in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. The cathode electrode CE can function as a semi-reflective mirror, which allows light emitted from the light-emitting structure EMS to be partially transmitted through it and partially reflected from it.

[0169] The first anode electrode AE1, the portion of the light-emitting structure EMS superimposed on the first anode electrode AE1, and the portion of the cathode electrode CE superimposed on the first anode electrode AE1 can constitute the first light-emitting element LD1. The second anode electrode AE2, the portion of the light-emitting structure EMS superimposed on the second anode electrode AE2, and the portion of the cathode electrode CE superimposed on the second anode electrode AE2 can constitute the second light-emitting element LD2. The third anode electrode AE3, the portion of the light-emitting structure EMS superimposed on the third anode electrode AE3, and the portion of the cathode electrode CE superimposed on the third anode electrode AE3 can constitute the third light-emitting element LD3.

[0170] The TFE encapsulation layer can be disposed on the cathode electrode (CE). The TFE encapsulation layer prevents oxygen and / or moisture from penetrating into the light-emitting element layer (LDL).

[0171] An optical functional layer (OFL) can be disposed on a packaging layer (TFE). In some embodiments, the optical functional layer (OFL) can be attached to the packaging layer (TFE) via an adhesive layer (APL). For example, the optical functional layer (OFL) can be manufactured separately to be attached to the packaging layer (TFE) via the adhesive layer (APL). The adhesive layer (APL) can also perform the function of protecting the underlying layers, including the packaging layer (TFE).

[0172] The optical functional layer (OFL) may include a color filter layer (CFL) and a lens array (LA). The color filter layer (CFL) may include a first color filter (CF1), a second color filter (CF2), and a third color filter (CF3) corresponding to the first sub-pixel (SP1), the second sub-pixel (SP2), and the third sub-pixel (SP3), respectively. The first color filter (CF1), the second color filter (CF2), and the third color filter (CF3) can allow light with different wavelength ranges to pass through them. For example, the first color filter (CF1), the second color filter (CF2), and the third color filter (CF3) can allow red, green, and blue light to pass through them, respectively.

[0173] In some embodiments, the first color filter CF1, the second color filter CF2, and the third color filter CF3 may be partially superimposed on each other in the boundary region BDA. In other embodiments, the first color filter CF1, the second color filter CF2, and the third color filter CF3 may be spaced apart from each other, and a black matrix may be disposed between the first color filter CF1, the second color filter CF2, and the third color filter CF3.

[0174] The lens array LA can be disposed on the color filter layer CFL. The lens array LA may include a first lens LS1, a second lens LS2, and a third lens LS3 corresponding to the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, respectively. The first lens LS1, the second lens LS2, and the third lens LS3 can output light emitted from the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 along a predetermined path, thereby improving light emission efficiency.

[0175] Figure 10 This illustrates some embodiments according to this disclosure. Figure 7 A cross-sectional view of the light-emitting structure in any one of the first to third light-emitting elements shown.

[0176] Reference Figure 10 The light-emitting structure EMS can have a series structure in which a first light-emitting unit EU1 and a second light-emitting unit EU2 are stacked. Figure 7 Each of the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 shown is constructed in a substantially identical manner.

[0177] Each of the first light-emitting unit EU1 and the second light-emitting unit EU2 may include at least one light-emitting layer that generates light according to an applied current. The first light-emitting unit EU1 may include a first light-emitting layer EML1, a first electron transport unit ETU1, and a first hole transport unit HTU1. The first light-emitting layer EML1 may be disposed between the first electron transport unit ETU1 and the first hole transport unit HTU1. The second light-emitting unit EU2 may include a second light-emitting layer EML2, a second electron transport unit ETU2, and a second hole transport unit HTU2. The second light-emitting layer EML2 may be disposed between the second electron transport unit ETU2 and the second hole transport unit HTU2.

[0178] Each of the first hole transport unit HTU1 and the second hole transport unit HTU2 may include at least one of a hole injection layer and a hole transport layer. If desired, each of the first hole transport unit HTU1 and the second hole transport unit HTU2 may also include a hole buffer layer, an electron blocking layer, etc. The first hole transport unit HTU1 and the second hole transport unit HTU2 may have the same or substantially the same structure, or they may have different structures.

[0179] Each of the first electron transport unit ETU1 and the second electron transport unit ETU2 may include at least one of an electron injection layer and an electron transport layer. If desired, each of the first electron transport unit ETU1 and the second electron transport unit ETU2 may also include an electron buffer layer, a hole blocking layer, etc. The first electron transport unit ETU1 and the second electron transport unit ETU2 may have the same or substantially the same structure, or may have different structures.

[0180] A connection layer, which can be configured in the form of a charge generation layer CGL, can be disposed between the first light-emitting unit EU1 and the second light-emitting unit EU2 to connect the first light-emitting unit EU1 and the second light-emitting unit EU2 to each other. In some embodiments, the charge generation layer CGL can have a stacked structure of p-doped layers and n-doped layers. For example, the p-doped layer can include p-type dopants such as HAT-CN, TCNQ, or NDP-9, and the n-doped layer can include alkali metals, alkaline earth metals, lanthanum metals, or any combination thereof. However, the embodiments are not limited thereto.

[0181] In some embodiments, the first emissive layer EML1 and the second emissive layer EML2 can produce light of different colors. Light emitted from the first emissive layer EML1 and the second emissive layer EML2, respectively, can be mixed together to be considered as white light. For example, the first emissive layer EML1 can produce blue light, and the second emissive layer EML2 can produce yellow light. In some embodiments, the second emissive layer EML2 may include a structure in which a first sub-emissive layer configured to produce red light and a second sub-emissive layer configured to produce green light are stacked. The red and green light can be mixed together to provide yellow light. An intermediate layer configured to perform the function of transmitting holes and / or blocking electron transmission may be further disposed between the first and second sub-emissive layers.

[0182] In other embodiments, the first light-emitting layer EML1 and the second light-emitting layer EML2 can produce light of the same or substantially the same color.

[0183] The light-emitting structure EMS can be formed by processes such as vacuum deposition or inkjet printing, but the embodiments are not limited to these.

[0184] Figure 11 It is shown that it includes Figure 7 A cross-sectional view of another embodiment of the light-emitting structure in one of the first to third light-emitting elements shown.

[0185] Reference Figure 11 The light-emitting structure EMS' can be a series structure in which a first light-emitting unit EU1', a second light-emitting unit EU2', and a third light-emitting unit EU3' are stacked. Figure 7 Each of the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 shown is constructed in a substantially identical manner.

[0186] Each of the first light-emitting unit EU1', the second light-emitting unit EU2', and the third light-emitting unit EU3' may include a light-emitting layer that generates light according to an applied current. The first light-emitting unit EU1' may include a first light-emitting layer EML1', a first electron transport unit ETU1', and a first hole transport unit HTU1'. The first light-emitting layer EML1' may be disposed between the first electron transport unit ETU1' and the first hole transport unit HTU1'. The second light-emitting unit EU2' may include a second light-emitting layer EML2', a second electron transport unit ETU2', and a second hole transport unit HTU2'. The second light-emitting layer EML2' may be disposed between the second electron transport unit ETU2' and the second hole transport unit HTU2'. The third light-emitting unit EU3' may include a third light-emitting layer EML3', a third electron transport unit ETU3', and a third hole transport unit HTU3'. The third light-emitting layer EML3' may be disposed between the third electron transport unit ETU3' and the third hole transport unit HTU3'.

[0187] Each of the first hole transport unit HTU1', the second hole transport unit HTU2', and the third hole transport unit HTU3' may include at least one of a hole injection layer and a hole transport layer, and may also include a hole buffer layer and an electron blocking layer if desired. The first hole transport unit HTU1', the second hole transport unit HTU2', and the third hole transport unit HTU3' may have the same or substantially the same structure, or may have different structures.

[0188] Each of the first electron transport unit ETU1', the second electron transport unit ETU2', and the third electron transport unit ETU3' may include at least one of an electron injection layer and an electron transport layer, and may also include an electron buffer layer, a hole blocking layer, etc., if desired. The first electron transport unit ETU1', the second electron transport unit ETU2', and the third electron transport unit ETU3' may have the same or substantially the same structure, or may have different structures.

[0189] The first charge generation layer CGL1' can be disposed between the first light-emitting unit EU1' and the second light-emitting unit EU2'. The second charge generation layer CGL2' can be disposed between the second light-emitting unit EU2' and the third light-emitting unit EU3'.

[0190] In some embodiments, the first emissive layer EML1', the second emissive layer EML2', and the third emissive layer EML3' can produce light of different colors. The light emitted from the first emissive layer EML1', the second emissive layer EML2', and the third emissive layer EML3' can be mixed to be considered as white light. For example, the first emissive layer EML1' can produce blue light, the second emissive layer EML2' can produce green light, and the third emissive layer EML3' can produce red light.

[0191] In other embodiments, at least two of the first light-emitting layer EML1', the second light-emitting layer EML2', and the third light-emitting layer EML3' can produce light of the same or substantially the same color.

[0192] With Figure 11 and Figure 10 The difference shown is not the same. Figure 7 The light-emitting structure EMS shown may include one light-emitting unit in each of the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3. The light-emitting units included in each of the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 may be configured to emit light of different colors. For example, the light-emitting unit of the first light-emitting element LD1 may emit red light, the light-emitting unit of the second light-emitting element LD2 may emit green light, and the light-emitting unit of the third light-emitting element LD3 may emit blue light. Figure 7 Unlike the previous example, the light-emitting units of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can be separated from each other, and each of the light-emitting units can be located in the opening OP of the pixel-defining layer PDL. At least some of the color filters CF1, CF2, and CF3 can be omitted.

[0193] Figure 12 This illustrates some other embodiments according to the present disclosure. Figure 5 A planar view of one of the pixels shown.

[0194] Reference Figure 12 The first pixel PXL1' may include a first sub-pixel SP1', a second sub-pixel SP2', and a third sub-pixel SP3'.

[0195] The first sub-pixel SP1' may include a first emitting region EMA1' and a non-emitting region NEA' located outside the first emitting region EMA1'. The second sub-pixel SP2' may include a second emitting region EMA2' and a non-emitting region NEA' located outside the second emitting region EMA2'. The third sub-pixel SP3' may include a third emitting region EMA3' and a non-emitting region NEA' located outside the third emitting region EMA3'.

[0196] The first sub-pixel SP1' and the second sub-pixel SP2' can be arranged on the second direction DR2. The third sub-pixel SP3' can be set on the first direction DR1 relative to each of the first sub-pixel SP1' and the second sub-pixel SP2'.

[0197] The second sub-pixel SP2' can have a larger area than the first sub-pixel SP1', and the third sub-pixel SP3' can have a larger area than the second sub-pixel SP2'. The second emission region EMA2' can have a larger area than the first emission region EMA1', and the third emission region EMA3' can have a larger area than the second emission region EMA2'. However, the embodiments are not limited to this. For example, the first sub-pixel SP1' and the second sub-pixel SP2' can have substantially the same area, and the third sub-pixel SP3' can have an area larger than each of the first sub-pixel SP1' and the second sub-pixel SP2'. Thus, the areas of the first sub-pixel SP1', the second sub-pixel SP2', and the third sub-pixel SP3' can be modified differently in some embodiments.

[0198] Figure 13 This illustrates some other embodiments. Figure 5 A planar view of one of the pixels shown.

[0199] Reference Figure 13 The first sub-pixel SP1'' may include a first emitting region EMA1'' and a non-emitting region NEA'' located around the first emitting region EMA1''. The second sub-pixel SP2'' may include a second emitting region EMA2'' and a non-emitting region NEA'' located around the second emitting region EMA2''. The third sub-pixel SP3'' may include a third emitting region EMA3'' and a non-emitting region NEA'' located around the third emitting region EMA3''.

[0200] When viewed on a third-party DR3, the first sub-pixel SP1'', the second sub-pixel SP2'', and the third sub-pixel SP3'' can have polygonal shapes. For example, the shapes of the first sub-pixel SP1'', the second sub-pixel SP2'', and the third sub-pixel SP3'' can be hexagonal.

[0201] When viewed on a third-party DR3, the first emission area EMA1'', the second emission area EMA2'', and the third emission area EMA3'' may have a circular shape. However, the embodiment is not limited to this. For example, each of the first emission area EMA1'', the second emission area EMA2'', and the third emission area EMA3'' may have a polygonal shape.

[0202] The first sub-pixel SP1'' and the third sub-pixel SP3'' can be arranged on the first direction DR1. The second sub-pixel SP2'' can be set relative to the first sub-pixel SP1'' in a direction tilted at an acute angle (or diagonal direction) based on the second direction DR2.

[0203] exist Figure 6 , Figure 12 and Figure 13 The arrangement of subpixels shown is merely illustrative, and the embodiments are not limited thereto. Each pixel may include two or more subpixels, and the subpixels may be arranged in various ways. Each of the subpixels may have various shapes, and the emission region of the subpixel may have various shapes.

[0204] Figure 14 This is a block diagram illustrating a display system according to some embodiments of the present disclosure.

[0205] Reference Figure 14 The display system 1000 may include a processor 1100 and one or more display devices 1210 and 1220.

[0206] The processor 1100 can perform various tasks and calculations. In some embodiments, the processor 1100 may include an application processor (AP), a graphics processing unit (GPU), a microprocessor, a central processing unit (CPU), etc. The processor 1100 can be connected to other components of the display system 1000 via a bus system to control the components of the display system 1000.

[0207] exist Figure 14 The diagram shows a display system 1000 including a first display device 1210 and a second display device 1220. A processor 1100 can be connected to the first display device 1210 via a first channel CH1 and to the second display device 1220 via a second channel CH2.

[0208] Through the first channel CH1, the processor 1100 can transmit first image data IMG1 and a first control signal CTRL1 to the first display device 1210. The first display device 1210 can display an image based on the first image data IMG1 and the first control signal CTRL1. The first display device 1210 can be connected to a reference... Figure 1 The display device 100 described is constructed substantially the same as the one described. The first image data IMG1 and the first control signal CTRL1 can be provided respectively as... Figure 1 The input image data IMG and control signal CTRL are shown in the figure.

[0209] Through the second channel CH2, the processor 1100 can transmit second image data IMG2 and second control signal CTRL2 to the second display device 1220. The second display device 1220 can display an image based on the second image data IMG2 and the second control signal CTRL2. The second display device 1220 can be used with a reference... Figure 1 The display device 100 described is constructed substantially the same as the one described. The second image data IMG2 and the second control signal CTRL2 can be provided respectively as... Figure 1 The input image data IMG and control signal CTRL are shown in the figure.

[0210] Display system 1000 may include a computing system for providing image display functionality, such as a portable computer, mobile phone, smartphone, tablet PC, smartwatch, watch phone, portable multimedia player (PMP), navigation system, or ultra-mobile computer (UMPC). Display system 1000 may include at least one of head-mounted display (HMD) device, virtual reality (VR) device, mixed reality (MR) device, and augmented reality (AR) device.

[0211] Figure 15 This illustrates some embodiments according to the present disclosure. Figure 14 The image shows a perspective view of an application example of the display system.

[0212] Reference Figure 15 , Figure 14 The display system 1000 shown can be applied to a head-mounted display device 2000. The head-mounted display device 2000 can be a wearable electronic device that can be worn on a user's head.

[0213] The head-mounted display device 2000 may include a headband 2100 and a display device housing 2200. The headband 2100 may be connected to the display device housing 2200. The headband 2100 may include a horizontal strap and / or a vertical strap for securing the head-mounted display device 2000 to a user's head. The horizontal strap may be configured to surround the sides of the user's head, and the vertical strap may be configured to surround the top of the user's head. However, the embodiments are not limited thereto. For example, the headband 2100 may be implemented in the form of eyeglass frames, helmets, etc.

[0214] The display device housing 2200 can accommodate Figure 14 The first display device 1210 and the second display device 1220 are shown. The display device housing 2200 can also accommodate... Figure 14 The processor 1100 shown is shown.

[0215] Figure 16 This illustrates a user-worn device according to some embodiments of the present disclosure. Figure 15 A view of the head-mounted display device shown.

[0216] Reference Figure 16 The first display panel DP1 of the first display device 1210 and the second display panel DP2 of the second display device 1220 can be disposed in the head-mounted display device 2000. The head-mounted display device 2000 may also include one or more lenses LLNS and RLNS.

[0217] In the display device housing 2200, the right eye lens RLNS can be disposed between the first display panel DP1 and the user's right eye. In the display device housing 2200, the left eye lens LLNS can be disposed between the second display panel DP2 and the user's left eye.

[0218] The image output from the first display panel DP1 can be viewed by the user's right eye through the right eye lens RLNS. The right eye lens RLNS can refract light emitted from the first display panel DP1 so that it faces the user's right eye. The right eye lens RLNS can perform optical functions to adjust the viewing distance between the first display panel DP1 and the user's right eye.

[0219] The image output from the second display panel DP2 can be viewed by the user's left eye through the left eye lens LLNS. The left eye lens LLNS refracts the light emitted from the second display panel DP2 so that it faces the user's left eye. The left eye lens LLNS performs an optical function to adjust the viewing distance between the second display panel DP2 and the user's left eye.

[0220] In some embodiments, each of the right-eye lens RLNS and the left-eye lens LLNS may include an optical lens having a pancake-shaped profile. In some embodiments, each of the right-eye lens RLNS and the left-eye lens LLNS may include a multi-channel lens comprising sub-regions with different optical properties. Each display panel may output an image corresponding to a sub-region of the multi-channel lens, and the output image may be viewed by the user while passing through the respective sub-region.

[0221] A method for manufacturing a display device according to the above embodiments will now be described.

[0222] Figures 17 to 24 This is a cross-sectional view illustrating the process steps of a method for manufacturing a display device according to some embodiments of the present disclosure. Figures 17 to 24 It shows the manufacturing process. Figures 1 to 8 A cross-sectional view of the method of the display device shown. For ease of description, a simplified representation is shown. Figures 17 to 24 The construction shown is illustrated, and detailed reference numerals are omitted.

[0223] Reference Figure 17First, a blocking layer BR, a reflective electrode RE, and / or a resonant layer RS ​​can be formed in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. (Refer to the reference...) Figure 7 A barrier layer BR, a reflective electrode RE, and / or a resonant layer RS ​​are formed on the substrate SUB, pixel circuit layer PCL, and / or via layer VIAL. The barrier layer BR may be formed on the via layer VIAL. The reflective electrode RE may be formed on the barrier layer BR. The resonant layer RS ​​may be formed on the reflective electrode RE.

[0224] Reference Figure 18 Subsequently, the resonant layers RS of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can be etched to different thicknesses. For example, the thickness t1 of the resonant layer RS ​​of the first sub-pixel SP1 on the third-direction DR3 can be less than the thickness t2 of the resonant layer RS ​​of the second sub-pixel SP2 on the third-direction DR3. Therefore, the first sub-pixel SP1 can have a shorter resonant distance than the second sub-pixel SP2. The thickness t2 of the resonant layer RS ​​of the second sub-pixel SP2 on the third-direction DR3 can be less than the thickness t3 of the resonant layer RS ​​of the third sub-pixel SP3 on the third-direction DR3. Therefore, the second sub-pixel SP2 can have a shorter resonant distance than the third sub-pixel SP3. In this way, by adjusting the thickness of the resonant layer RS ​​of each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, the resonant distance of each of the three sub-pixels SP3 can be adjusted, thereby improving the brightness of the display device, as described above.

[0225] Reference Figure 19 Subsequently, the blocking layer BR, the reflective electrode RE, and / or the resonant layer RS ​​can be patterned. Therefore, the blocking layer BR, the first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3, and / or the first resonant layer RS1, the second resonant layer RS2, and the third resonant layer RS3 can be formed in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, respectively.

[0226] Reference Figure 20 Subsequently, a first anode electrode AE1, a second anode electrode AE2, and a third anode electrode AE3 can be formed on the barrier layer BR, the first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3, and / or the first resonant layer RS1, the second resonant layer RS2, and the third resonant layer RS3, respectively.

[0227] The first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 can respectively cover the side surfaces and top surfaces of the first resonant layer RS1, the second resonant layer RS2, and the third resonant layer RS3. The first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 can respectively be directly formed on the side surfaces and top surfaces of the first resonant layer RS1, the second resonant layer RS2, and the third resonant layer RS3. The first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 can respectively contact the side surfaces and top surfaces of the first resonant layer RS1, the second resonant layer RS2, and the third resonant layer RS3.

[0228] The first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 can respectively cover the side surfaces of the first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3. The first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 can respectively be directly formed on the side surfaces of the first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3. The first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 can respectively contact the side surfaces of the first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3.

[0229] The first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 can each cover the side surface of the barrier layer BR. The first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 can each be directly formed on the side surface of the barrier layer BR. The first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 can each contact the side surface of the barrier layer BR.

[0230] Reference Figure 21 Subsequently, a pixel defining layer (PDL) can be formed on the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3. The PDL may include a first layer L1 and a second layer L2. The first layer L1 may be formed on the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3. The second layer L2 may be formed on the first layer L1. The thickness of the second layer L2 on the third-direction DR3 may be greater than the thickness of the first layer L1 on the third-direction DR3. The first layer L1 and / or the second layer L2 may be made of silicon oxide (SiO2). x ) and silicon nitride (SiN) x At least one of the following can be formed: For example, the first layer L1 can be made of silicon nitride (SiN). x The second layer L2 can be formed from silicon dioxide (SiO2). x (This is a process of formation. However, this disclosure is not limited thereto.)

[0231] Reference Figure 22 Subsequently, the pixel-defining layer (PDL) can be polished. The top surface of the PDL can be flattened by chemical mechanical polishing (CMP). The first layer L1 can be used as an etch stop in the process of polishing the PDL. For example, when polishing the second layer L2 in the process of polishing the PDL, the top surface of the first layer L1 of the third sub-pixel SP3 can be exposed.

[0232] Due to the thickness difference between the first resonant layer RS1, the second resonant layer RS2, and the third resonant layer RS3, the thicknesses of the pixel-defining layers PDL on the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 can be different from each other. For example, the thickness of the pixel-defining layer PDL on the first anode electrode AE1 in the third-direction DR3 can be greater than the thickness of the pixel-defining layer PDL on the second anode electrode AE2 in the third-direction DR3. Similarly, the thickness of the pixel-defining layer PDL on the second anode electrode AE2 in the third-direction DR3 can be greater than the thickness of the pixel-defining layer PDL on the third anode electrode AE3 in the third-direction DR3.

[0233] Reference Figure 23 Subsequently, trenches TRCH1 and TRCH2 can be formed in the pixel-defining layer PDL. Trenches TRCH1 and TRCH2 can be formed between the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. Due to trenches TRCH1 and TRCH2, the portions of the light-emitting structure EMS included in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can be at least partially separated from each other. Therefore, the current leakage from each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 through the layers included in the light-emitting structure EMS to its adjacent sub-pixels can be reduced or minimized, as already described above.

[0234] Reference Figure 24 Subsequently, a first opening OP1, a second opening OP2, and a third opening OP3 can be formed in the pixel-defining layer PDL of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. The first opening OP1, the second opening OP2, and the third opening OP3 can expose the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3, respectively.

[0235] Due to the thickness difference between the first resonant layer RS1, the second resonant layer RS2, and the third resonant layer RS3, the first opening OP1, the second opening OP2, and the third opening OP3 of the pixel limiting layer PDL can have different depths. For example, when the thickness t1 of the first resonant layer RS1 on the third-direction DR3 is less than the thickness t2 of the second resonant layer RS2 on the third-direction DR3, the depth D1 of the first opening OP1 on the third-direction DR3 can be greater than the depth D2 of the second opening OP2 on the third-direction DR3. When the thickness t2 of the second resonant layer RS2 on the third-direction DR3 is less than the thickness t3 of the third resonant layer RS3 on the third-direction DR3, the depth D2 of the second opening OP2 on the third-direction DR3 can be greater than the depth D3 of the third opening OP3 on the third-direction DR3. The depth D3 of the third opening OP3 on the third-direction DR3 can be substantially equal to the thickness of the first layer L1 on the third-direction DR3.

[0236] Subsequently, it can be referenced as follows Figure 7 The first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3, as well as the pixel limiting layer PDL, form a light-emitting structure EMS, thereby completing the display device.

[0237] In the following description, another embodiment of this disclosure will be described. In the embodiments described below, the same components as those already described are indicated by the same reference numerals, and repeated descriptions will be omitted or simplified.

[0238] Figures 25 to 34 This is a cross-sectional view illustrating the process steps of a method for manufacturing a display device according to some embodiments of the present disclosure. Figures 25 to 34 It shows the manufacturing process. Figure 9 A cross-sectional view of the method of the display device shown. For ease of description, a simplified diagram is shown. Figures 25 to 34 The construction shown is illustrated, and detailed reference numerals are omitted.

[0239] Reference Figure 25 First, a first blocking layer BR1, a reflective electrode RE, and / or a second blocking layer BR2 can be formed in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. (Refer to...) Figure 8 A first barrier layer BR1, a reflective electrode RE, and / or a second barrier layer BR2 are formed on the substrate SUB, pixel circuit layer PCL, and via layer VIAL. The first barrier layer BR1 may be formed on the via layer VIAL. The reflective electrode RE may be formed on the first barrier layer BR1. The second barrier layer BR2 may be formed on the reflective electrode RE. The thickness of the second barrier layer BR2 may be less than the thickness of the first barrier layer BR1, but this disclosure is not limited thereto.

[0240] Reference Figure 26 Subsequently, the resonant layer RS ​​can be initially formed in the third sub-pixel SP3. The resonant layer RS ​​can be partially deposited on the second blocking layer BR2 in the third sub-pixel SP3.

[0241] Reference Figure 27 Subsequently, the resonant layer RS ​​can be formed a second time in the second sub-pixel SP2 and the third sub-pixel SP3. The resonant layer RS ​​can be deposited partially on the second barrier layer BR2 in the second sub-pixel SP2 and the third sub-pixel SP3. The thickness of the resonant layer RS ​​formed in the second sub-pixel SP2 on the third-direction DR3 can be less than the thickness of the resonant layer RS ​​formed in the third sub-pixel SP3 on the third-direction DR3.

[0242] Reference Figure 28 Subsequently, the resonant layer RS ​​can be formed three times in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. The resonant layer RS ​​can be deposited entirely on the second blocking layer BR2 (e.g., deposited entirely on the second blocking layer BR2) in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. In this way, when the resonant layer RS ​​is formed sequentially, resonant layers RS of different thicknesses can be formed in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3.

[0243] The thickness t1 of the resonant layer RS ​​of the first sub-pixel SP1 on the third-direction DR3 can be less than the thickness t2 of the resonant layer RS ​​of the second sub-pixel SP2 on the third-direction DR3. Therefore, the first sub-pixel SP1 can have a shorter resonant distance than the second sub-pixel SP2. The thickness t2 of the resonant layer RS ​​of the second sub-pixel SP2 on the third-direction DR3 can be less than the thickness t3 of the resonant layer RS ​​of the third sub-pixel SP3 on the third-direction DR3. Therefore, the second sub-pixel SP2 can have a shorter resonant distance than the third sub-pixel SP3. Thus, by adjusting the thickness of the resonant layer RS ​​of each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, the resonant distance of each of the three sub-pixels SP3 can be adjusted, thereby improving the brightness of the display device, as described above.

[0244] Reference Figure 29 Subsequently, the first blocking layer BR1, the reflective electrode RE, the second blocking layer BR2, and / or the resonant layer RS ​​can be patterned. Therefore, the first blocking layer BR1, the first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3, the second blocking layer BR2, and / or the first resonant layer RS1, the second resonant layer RS2, and the third resonant layer RS3 can be formed in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, respectively.

[0245] Reference Figure 30 Subsequently, a first anode electrode AE1, a second anode electrode AE2, and a third anode electrode AE3 can be formed on the first barrier layer BR1, the first reflective electrode RE1, the second reflective electrode RE2 and the third reflective electrode RE3, the second barrier layer BR2 and / or the first resonant layer RS1, the second resonant layer RS2 and the third resonant layer RS3, respectively.

[0246] The first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 can respectively cover the side surfaces and top surfaces of the first resonant layer RS1, the second resonant layer RS2, and the third resonant layer RS3. The first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 can respectively be directly formed on the side surfaces and top surfaces of the first resonant layer RS1, the second resonant layer RS2, and the third resonant layer RS3. The first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 can respectively contact the side surfaces and top surfaces of the first resonant layer RS1, the second resonant layer RS2, and the third resonant layer RS3.

[0247] The first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 can respectively cover the side surfaces of the first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3. The first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 can respectively be directly formed on the side surfaces of the first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3. The first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 can respectively contact the side surfaces of the first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3.

[0248] The first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 can respectively cover the side surfaces of the first barrier layer BR1 and the second barrier layer BR2. The first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 can respectively be directly formed on the side surfaces of the first barrier layer BR1 and the second barrier layer BR2. The first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 can respectively contact the side surfaces of the first barrier layer BR1 and the second barrier layer BR2.

[0249] Reference Figure 31Subsequently, a pixel defining layer (PDL) can be formed on the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3. The PDL may include a first layer L1 and a second layer L2. The first layer L1 may be formed on the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3. The second layer L2 may be formed on the first layer L1. The thickness of the second layer L2 on the third-direction DR3 may be greater than the thickness of the first layer L1 on the third-direction DR3. The first layer L1 and / or the second layer L2 may be made of silicon oxide (SiO2). x ) and silicon nitride (SiN) x At least one of the following can be formed: For example, the first layer L1 can be made of silicon nitride (SiN). x The second layer L2 can be formed from silicon dioxide (SiO2). x (This is a process of formation. However, this disclosure is not limited thereto.)

[0250] Reference Figure 32 Subsequently, the pixel-defining layer (PDL) can be polished. The top surface of the PDL can be flattened by chemical mechanical polishing (CMP). The first layer L1 can be used as an etch stop in the process of polishing the PDL. For example, when polishing the second layer L2 in the process of polishing the PDL, the top surface of the first layer L1 of the third sub-pixel SP3 can be exposed.

[0251] Due to the thickness difference between the first resonant layer RS1, the second resonant layer RS2, and the third resonant layer RS3, the thicknesses of the pixel-defining layers PDL on the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 can be different from each other. For example, the thickness of the pixel-defining layer PDL on the first anode electrode AE1 in the third-direction DR3 can be greater than the thickness of the pixel-defining layer PDL on the second anode electrode AE2 in the third-direction DR3. Similarly, the thickness of the pixel-defining layer PDL on the second anode electrode AE2 in the third-direction DR3 can be greater than the thickness of the pixel-defining layer PDL on the third anode electrode AE3 in the third-direction DR3.

[0252] Reference Figure 33Subsequently, trenches TRCH1 and TRCH2 can be formed in the pixel-defining layer PDL. Trenches TRCH1 and TRCH2 can be formed between the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. Due to trenches TRCH1 and TRCH2, the portions of the light-emitting structure EMS included in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can be at least partially separated from each other. Therefore, the current leakage from each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 through the layers included in the light-emitting structure EMS to its adjacent sub-pixels can be reduced or minimized, as already described above.

[0253] Reference Figure 34 Subsequently, a first opening OP1, a second opening OP2, and a third opening OP3 can be formed in the pixel-defining layer PDL of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. The first opening OP1, the second opening OP2, and the third opening OP3 can expose the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3, respectively.

[0254] Due to the thickness difference between the first resonant layer RS1, the second resonant layer RS2, and the third resonant layer RS3, the first opening OP1, the second opening OP2, and the third opening OP3 of the pixel limiting layer PDL can have different depths. For example, when the thickness t1 of the first resonant layer RS1 on the third-direction DR3 is less than the thickness t2 of the second resonant layer RS2 on the third-direction DR3, the depth D1 of the first opening OP1 on the third-direction DR3 can be greater than the depth D2 of the second opening OP2 on the third-direction DR3. When the thickness t2 of the second resonant layer RS2 on the third-direction DR3 is less than the thickness t3 of the third resonant layer RS3 on the third-direction DR3, the depth D2 of the second opening OP2 on the third-direction DR3 can be greater than the depth D3 of the third opening OP3 on the third-direction DR3. The depth D3 of the third opening OP3 on the third-direction DR3 can be substantially equal to the thickness of the first layer L1 on the third-direction DR3.

[0255] Subsequently, it can be referenced as follows Figure 8 The first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3, as well as the pixel limiting layer PDL, form a light-emitting structure EMS, thereby completing the display device.

[0256] According to this disclosure, the resonant distance of each sub-pixel can be adjusted using a resonant layer of the sub-pixel. Therefore, light within a corresponding wavelength range can be effectively output from each sub-pixel, thereby improving the brightness of the display device.

[0257] Example embodiments have been disclosed herein, and although specific terminology has been used, they are used and interpreted in a general and descriptive sense only and not for limiting purposes. In some instances, as will be apparent to those skilled in the art, features, characteristics, and / or elements described in connection with particular embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise clearly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of this disclosure as set forth in the claims and their equivalents.

Claims

1. A display device, characterized in that, The display device includes: First sub-pixel, second sub-pixel, and third sub-pixel Each of the first to the third sub-pixels includes: Reflective electrode; A resonant layer is located on the reflective electrode. The first electrode is located on the resonant layer; A pixel defining layer is located above the first electrode, and the pixel defining layer has an opening; The light-emitting structure is located on the first electrode and the pixel defining layer; and The second electrode is located on the light-emitting structure. Wherein, the thickness of the resonant layer of the first sub-pixel is less than the thickness of the resonant layer of the second sub-pixel, and Wherein, the depth of the opening of the first sub-pixel is greater than the depth of the opening of the second sub-pixel.

2. The display device as claimed in claim 1, characterized in that, The first electrode covers the top and side surfaces of the resonant layer.

3. The display device as claimed in claim 1, characterized in that, The first electrode is in contact with the side surface of the reflective electrode.

4. The display device as claimed in claim 1, characterized in that, The thickness of the resonant layer of the second sub-pixel is less than the thickness of the resonant layer of the third sub-pixel.

5. The display device as claimed in claim 1, characterized in that, The depth of the opening of the second sub-pixel is greater than the depth of the opening of the third sub-pixel.

6. The display device as claimed in claim 1, characterized in that, The pixel defining layer includes a first layer on the first electrode and a second layer on the first layer.

7. The display device as claimed in claim 6, characterized in that, The depth of the opening in the third sub-pixel is equal to the thickness of the first layer.

8. The display device as claimed in claim 6, characterized in that, The thickness of the first layer is less than the thickness of the second layer.

9. The display device as claimed in claim 1, characterized in that, The display device also includes a first barrier layer on the bottom of the reflective electrode.

10. An electronic device, characterized in that, The electronic device includes: A processor for providing input image data; and A display device for displaying an image based on the input image, the display device including sub-pixel regions. The display device includes a first sub-pixel, a second sub-pixel, and a third sub-pixel. Each of the first to the third sub-pixels includes: Reflective electrode; A resonant layer is located on the reflective electrode. The first electrode is located on the resonant layer; A pixel defining layer is located above the first electrode, and the pixel defining layer has an opening; The light-emitting structure is located on the first electrode and the pixel defining layer; and The second electrode is located on the light-emitting structure. Wherein, the thickness of the resonant layer of the first sub-pixel is less than the thickness of the resonant layer of the second sub-pixel, and Wherein, the depth of the opening of the first sub-pixel is greater than the depth of the opening of the second sub-pixel.

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