Display device

Abstract

The display device includes: a substrate including a display area including an emission area and a non-display area; the circuit layer is arranged on the substrate; and an element layer. The circuit layer includes: a substrate buffer layer disposed on the substrate; a semiconductor layer disposed on the base buffer layer; a first gate insulating layer covering the semiconductor layer; a first gate conductive layer disposed on the first gate insulating layer; a second gate insulating layer covering the first gate conductive layer; a second gate conductive layer disposed on the second gate insulating layer; an interlayer insulating layer covering the second gate conductive layer; a grid defined by grooves defined in the display area and the non-display area, where the grooves include a first extension groove and a second extension groove intersecting the first extension groove; and a grid filling layer filling the grid.

Description

Technical Field

[0001] Embodiments of this disclosure relate to display devices. Background Technology

[0002] With the advancement of information-oriented society, there is an increasing demand for display devices that can display images in various ways. For example, display devices are used in various electronic devices such as smartphones, digital cameras, laptops, navigation devices, and smart TVs.

[0003] The display device may be a flat panel display device (such as a liquid crystal display device, a field emission display device, or a light-emitting display device). Examples of light-emitting display devices may include organic light-emitting display devices that include organic light-emitting elements, inorganic light-emitting display devices that include inorganic light-emitting elements such as inorganic semiconductors, and micro light-emitting display devices that include micro light-emitting elements.

[0004] Organic light-emitting display devices use light-emitting elements, each comprising a light-emitting layer made of organic light-emitting materials, to display images. As described above, organic light-emitting display devices use self-emissive elements to display images, and therefore can have relatively desirable characteristics in terms of power consumption, response speed, luminous efficiency, brightness, and wide viewing angle compared to other types of display devices.

[0005] In a display device, the display surface that emits light may include a display area for displaying an image and a non-display area surrounding the display area. The emitting area for emitting light with corresponding brightness and color may be arranged within the display area. Utility Model Content

[0006] During the manufacturing and use of display devices, external impacts may be applied due to collisions with other objects or drops. When such external impacts are greater than or equal to a critical level, the display device may be easily deformed or damaged, potentially reducing its lifespan and convenience.

[0007] Furthermore, in display devices where a portion of the display device is transformed into a folded, bent, or rolled form, bending stress may be applied to the folded, bent, or rolled portion, making the display device more susceptible to external impacts.

[0008] In view of the above, embodiments of the present disclosure provide a display device capable of mitigating external impacts or reducing impact transmission by improving tensile strength.

[0009] According to embodiments of the present disclosure, a display device includes: a substrate including a display area having a plurality of emitting areas and a non-display area disposed around the display area; a circuit layer disposed on the substrate; and a component layer disposed on the circuit layer, wherein the component layer includes a plurality of light-emitting elements respectively disposed in the plurality of emitting areas, and the circuit layer includes: a plurality of light-emitting pixel drivers respectively electrically connected to the plurality of light-emitting elements; a plurality of gate lines for transmitting gate signals to the plurality of light-emitting pixel drivers; a gate driving circuit disposed in the gate driving region of the non-display area and including a plurality of stages respectively electrically connected to the plurality of gate lines; two or more insulating layers disposed on the substrate; a grid defined by a plurality of grooves, the grid being defined in at least some of a plurality of boundaries between the plurality of light-emitting pixel drivers and in at least some of a plurality of boundaries between the plurality of stages passing through the two or more insulating layers; and a grid filling layer for filling the grid.

[0010] In an embodiment, two or more insulating layers include: a substrate buffer layer disposed on a substrate; a first gate insulating layer disposed on the substrate buffer layer; a second gate insulating layer disposed on the first gate insulating layer; and an interlayer insulating layer disposed on the second gate insulating layer. The circuit layer further includes: a semiconductor layer disposed between the substrate buffer layer and the first gate insulating layer; a first gate conductive layer disposed between the first gate insulating layer and the second gate insulating layer; and a second gate conductive layer disposed between the second gate insulating layer and the interlayer insulating layer. A grid may expose a portion of each of the substrate, the first gate conductive layer, and the second gate conductive layer, and in a plan view, the grid may be spaced apart from the semiconductor layer.

[0011] In one embodiment, the grid's plurality of grooves includes a plurality of first extending grooves and a plurality of second extending grooves intersecting the plurality of first extending grooves. In the extending direction of the plurality of second extending grooves, one or more light-emitting pixel drivers among the plurality of light-emitting pixel drivers and one or more stages among the plurality of stages may be disposed between two adjacent first extending grooves in the plurality of first extending grooves of the grid. In such an embodiment, in the extending direction of the plurality of first extending grooves, one or more light-emitting pixel drivers among the plurality of first extending grooves may be disposed between two adjacent second extending grooves in the display area within the plurality of second extending grooves of the grid.

[0012] In one embodiment, the multiple gate lines may include: a scan write line transmitting a scan write signal; a scan initialization line transmitting a scan initialization signal; an emit control line transmitting an emit control signal; and a gate control line transmitting a gate control signal. In such an embodiment, the multiple stages of the gate drive circuit may include: an initialization stage disposed in a first circuit region of the gate drive region and electrically connected to the scan initialization line and the gate control line; a write stage disposed in a second circuit region of the gate drive region and electrically connected to the scan write line; and an emit control stage disposed in a third circuit region of the gate drive region and electrically connected to the emit control line. In such an embodiment, at least one of the second extended recesses of the multiple second extended recesses of the grid in the non-display region may be disposed between the first circuit region, the second circuit region, and the third circuit region.

[0013] In one embodiment, the non-display area may further include an extension line region disposed between the gate driving region and the display region. In such an embodiment, the circuit layer may further include gate extension lines disposed in the extension line region and electrically connected between multiple stages and multiple gate lines. In such an embodiment, two of the multiple second extension recesses of the gate may be respectively disposed on opposite sides of the extension line region.

[0014] In one embodiment, a light-emitting pixel driver electrically connected to a light-emitting element among a plurality of light-emitting pixel drivers may include: a first transistor electrically connected between a first node and a second node; a pixel capacitor electrically connected between a first power line and a third node; a second transistor electrically connected between a data line transmitting a data signal and the first node; a third transistor electrically connected between the second node and the third node; a fourth transistor electrically connected between a first initialization voltage line transmitting a first initialization voltage and the third node; a fifth transistor electrically connected between the first power line and the first node; a sixth transistor electrically connected between the second node and the fourth node; and a seventh transistor electrically connected between a second initialization voltage line transmitting a second initialization voltage and the fourth node. In such an embodiment, the first node is electrically connected to the first electrode of the first transistor, the second node is electrically connected to the second electrode of the first transistor, the third node is electrically connected to the gate electrode of the first transistor, and the fourth node is electrically connected to a light-emitting element. In such an embodiment, each of the second and third transistors is turned on by a scan write signal, the fourth transistor is turned on by a scan initialization signal, each of the fifth and sixth transistors is turned on by an emit control signal, and the seventh transistor is turned on by a gate control signal.

[0015] In one embodiment, the grid may be spaced apart from the semiconductor layer in a planar view.

[0016] In one embodiment, the circuit layer may further include supply lines disposed in the non-display area and surrounding at least a portion of the edge portion of the display area. In such an embodiment, a portion of the supply lines overlaps with the gate drive region in a plan view.

[0017] In one embodiment, the circuit layer may further include: a first source-drain conductive layer disposed on an interlayer insulating layer; a first planarization layer covering the first source-drain conductive layer and the grid; a second source-drain conductive layer disposed on the first planarization layer; and a second planarization layer covering the second source-drain conductive layer. In such an embodiment, a supply line may be disposed on the second source-drain conductive layer.

[0018] In one embodiment, two or more exposed holes may be defined to extend through the supply line and be spaced apart from each other in a plan view. In such an embodiment, the second planarization layer may contact the first planarization layer through two or more exposed holes, and in a plan view, two or more of the intersecting portions between the plurality of first extended grooves and the plurality of second extended grooves may each overlap with two or more exposed holes.

[0019] In an embodiment, the circuit layer further includes a grid buffer layer disposed between the grid and the grid fill layer and comprising an inorganic insulating material.

[0020] In an embodiment, the circuit layer may further include: an additional semiconductor layer disposed on the interlayer insulating layer; a third gate insulating layer covering the additional semiconductor layer; a third gate conductive layer disposed on the third gate insulating layer; and an additional interlayer insulating layer covering the third gate conductive layer. In such an embodiment, the grid may further expose a portion of the third gate conductive layer.

[0021] According to embodiments of this disclosure, a display device includes: a substrate including a display area having a plurality of emitting areas and a non-display area disposed around the display area; a circuit layer disposed on the substrate; and a component layer disposed on the circuit layer. In such embodiments, the component layer includes a plurality of light-emitting elements respectively disposed in the plurality of emitting areas. In such embodiments, the circuit layer includes: a plurality of light-emitting pixel drivers respectively electrically connected to the plurality of light-emitting elements; a plurality of gate lines for transmitting gate signals to the plurality of light-emitting pixel drivers; a gate driving circuit disposed in the gate driving region of the non-display area and including a plurality of stages respectively electrically connected to the plurality of gate lines. In such embodiments, two or more insulating layers are disposed on the substrate and comprise inorganic insulating material; a grid is defined by a plurality of grooves, the plurality of grooves being defined in at least some of a plurality of boundaries between the plurality of light-emitting pixel drivers and in at least some of a plurality of boundaries between a plurality of stages passing through the two or more insulating layers; and a grid filling layer filling the grid and comprising organic insulating material.

[0022] In an embodiment, two or more insulating layers may include: a substrate buffer layer disposed on a substrate; a first gate insulating layer disposed on the substrate buffer layer; a second gate insulating layer disposed on the first gate insulating layer; and an interlayer insulating layer disposed on the second gate insulating layer. In such an embodiment, the circuit layer may further include: a semiconductor layer disposed between the substrate buffer layer and the first gate insulating layer; a first gate conductive layer disposed between the first gate insulating layer and the second gate insulating layer; and a second gate conductive layer disposed between the second gate insulating layer and the interlayer insulating layer. In such an embodiment, the grid may expose a portion of each of the substrate, the first gate conductive layer, and the second gate conductive layer, and may be spaced apart from the semiconductor layer in a plan view.

[0023] In one embodiment, the plurality of grooves in the grid may include a plurality of first extending grooves and a plurality of second extending grooves intersecting the plurality of first extending grooves. In such an embodiment, one or more light-emitting pixel drivers and one or more stages may be disposed between two adjacent first extending grooves in the plurality of first extending grooves of the grid, along the extending direction of the plurality of first extending grooves. In such an embodiment, one or more light-emitting pixel drivers may be disposed between two adjacent second extending grooves in the plurality of second extending grooves of the grid, along the extending direction of the plurality of first extending grooves, along the extending direction of the plurality of first extending grooves, between two adjacent second extending grooves located in the display area.

[0024] In one embodiment, the multiple gate lines may include: a scan write line for transmitting a scan write signal; a scan initialization line for transmitting a scan initialization signal; an emit control line for transmitting an emit control signal; and a gate control line for transmitting a gate control signal. In such an embodiment, the multiple stages of the gate drive circuit may include: an initialization stage disposed in a first circuit region of the gate drive region and electrically connected to the scan initialization line and the gate control line; a write stage disposed in a second circuit region of the gate drive region and electrically connected to the scan write line; and an emit control stage disposed in a third circuit region of the gate drive region and electrically connected to the emit control line. In such an embodiment, at least one of the second extended recesses of the multiple second extended recesses of the grid in the non-display area may be disposed between the first circuit region, the second circuit region, and the third circuit region.

[0025] In one embodiment, the non-display area may further include an extension line region disposed between the gate driving region and the display region. In such an embodiment, the circuit layer may further include gate extension lines disposed in the extension line region and electrically connected between multiple stages and multiple gate lines. In such an embodiment, two of the multiple second extension recesses of the gate may be respectively disposed on opposite sides of the extension line region.

[0026] In an embodiment, the circuit layer may further include: a first source-drain conductive layer disposed on an interlayer insulating layer; a first planarization layer covering the first source-drain conductive layer and the gate; a second source-drain conductive layer disposed on the first planarization layer; a second planarization layer covering the second source-drain conductive layer; and a supply line disposed in the non-display area and surrounding three sides of the display area. In such an embodiment, the supply line may be disposed in the second source-drain conductive layer, and a portion of the supply line may overlap with the gate driving region in a planar view.

[0027] In one embodiment, two or more exposed holes may be defined to extend through the supply line and be spaced apart from each other in a plan view. In such an embodiment, the second planarization layer may contact the first planarization layer through two or more exposed holes. In such an embodiment, in a plan view, two or more of the intersecting portions between the plurality of first extended grooves and the plurality of second extended grooves overlap with two or more exposed holes, respectively.

[0028] In an embodiment, the circuit layer may further include a grid buffer layer disposed between the grid and the grid fill layer and comprising an inorganic insulating material.

[0029] According to an embodiment, the circuit layer of the display device includes: a grid including a plurality of first extending grooves and a plurality of second extending grooves intersecting the plurality of first extending grooves; and a grid filling layer that fills the grid and includes an organic insulating material.

[0030] In such an embodiment, the grid may include a plurality of first extending grooves and a plurality of second extending grooves intersecting the plurality of first extending grooves.

[0031] In such an embodiment, the grid can be provided by forming a plurality of grooves through one or more insulating layers, each comprising an inorganic insulating material, and can be filled with a grid filling layer comprising an organic insulating material.

[0032] In such embodiments, by providing a grid and a grid-filling layer, an organic insulating material with higher elasticity than inorganic insulating materials can be arranged in a grid form, thereby improving the tensile strength of the display device. Therefore, even when an external impact is applied to the display device, the impact can be mitigated or its transmission reduced due to the inherent tensile strength of the display device. This improves the convenience and lifespan of the display device.

[0033] In this embodiment, the grid is disposed not only in the display area but also in the non-display area, allowing the gate drive circuit disposed in the non-display area to robustly resist external shocks. Therefore, the lifespan and convenience of the display device can be further improved.

[0034] However, the effects of the embodiments according to this disclosure are not limited to those illustrated above, and various other effects are incorporated herein. Attached Figure Description

[0035] The above and other features of the embodiments of this disclosure will become more apparent from the detailed description of the embodiments with reference to the accompanying drawings, in which:

[0036] Figure 1 This is a perspective view showing a display device according to an embodiment;

[0037] Figure 2 It is shown Figure 1 A plan view of the display device;

[0038] Figure 3 It is along Figure 2 A cross-sectional view taken from line A-A';

[0039] Figure 4 It is shown Figure 2 Enlarged plan view of part B;

[0040] Figure 5 This illustrates an embodiment. Figure 4 The equivalent circuit diagram of the light-emitting pixel driver;

[0041] Figure 6 It is shown Figure 5 A cross-sectional view of the light-emitting element and the first and sixth transistors;

[0042] Figure 7 This illustrates an embodiment. Figure 2 A partial plan view of C;

[0043] Figure 8 It is according to the embodiment along Figure 7 A cross-sectional view taken from line D-D';

[0044] Figure 9 It is according to the embodiment along Figure 7 A cross-sectional view taken from line E-E';

[0045] Figure 10 It is according to the embodiment along Figure 7 A cross-sectional view taken from line E-E';

[0046] Figure 11 and Figure 12 This illustrates an embodiment. Figure 8 Enlarged views of parts F and parts G;

[0047] Figure 13 This illustrates an embodiment. Figure 2A partial plan view of C;

[0048] Figure 14 It is along Figure 13 A cross-sectional view taken from line E-E';

[0049] Figure 15 This illustrates an embodiment. Figure 2 A partial plan view of C;

[0050] Figure 16 This illustrates an embodiment. Figure 4 The equivalent circuit diagram of the light-emitting pixel driver;

[0051] Figure 17 It is shown Figure 16 Cross-sectional views of the first transistor, the second transistor, the fourth transistor, the sixth transistor, and the light-emitting element;

[0052] Figure 18 It is according to the embodiment along Figure 7 A cross-sectional view taken by line D-D'; and

[0053] Figure 19 It is according to the embodiment along Figure 7 A cross-sectional view taken from line E-E'. Detailed Implementation

[0054] The present invention will now be described more fully below with reference to the accompanying drawings, in which various embodiments are illustrated. However, the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. The same reference numerals throughout refer to the same elements.

[0055] For ease of description, some parts that are not related to the description may be omitted.

[0056] It will also be understood that when a layer is referred to as being "on" another layer or substrate, the layer may be directly on the other layer or substrate, or an intermediary layer may be present. In contrast, when an element is referred to as being "directly on" another element, an intermediary element may not be present.

[0057] Furthermore, the phrase "in a plan view" means when viewing a portion of an object from above, and the phrase "in a schematic cross-sectional view" means when viewing a schematic cross-section obtained by vertically cutting a portion of an object from the side. The term "overlap" means that the first object may be above or below the second object, or the first object may be on the side of the second object, and vice versa. Furthermore, the term "overlap" can include layering, stacking, facing or oriented, extending above, covering or partially covering, or any other suitable terminology that will be understood and appreciated by one of ordinary skill in the art. The expression "not overlapping" can include meanings such as "separated from," "separated from," or "offset from," and any other suitable equivalent meaning that will be understood and appreciated by one of ordinary skill in the art. The terms "facing" and "oriented" can mean that the first object may be directly or indirectly opposite the second object. In the case of a third object situated between the first and second objects, although they still face each other, the first and second objects can be understood as being indirectly opposite each other.

[0058] For ease of description, the spatial relative terms “below,” “under,” “down,” “above,” or “above,” etc., may be used herein to describe the relationship between one element or component and another, as shown in the accompanying drawings. It will be understood that, in addition to the orientation depicted in the drawings, the spatial relative terms are also intended to cover different orientations of the device during use or operation. For example, in the case where the device shown in the drawings is flipped, a device positioned “below” or “under” another device may be placed “above” another device. Therefore, the descriptive term “below” can include both a lower position and an upper position. The device may also be oriented in other directions, and therefore the spatial relative terms may be interpreted differently depending on the orientation.

[0059] When an element is referred to as being “connected” or “coupled” to another element, the element may be “directly connected” or “directly coupled” to the other element, or it may be “electrically connected” or “electrically coupled” to the other element by one or more intermediary elements between the element and the other element. It will also be understood that when the terms “comprises / comprising,” “has / have / having,” and / or “includes / including” are used, these terms may describe the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of other features, integrals, steps, operations, elements, components, and / or any combinations thereof.

[0060] It will be understood that although the terms “first,” “second,” or “third,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another, or for the convenience of describing and explaining said element and said other element. For example, when “first element” is discussed in the specification, “first element” may be referred to as “second element” or “third element,” and “second element” and “third element” may be named in a similar manner without departing from the teachings herein.

[0061] Given the measurements discussed and the errors associated with measurements of a particular quantity (e.g., limitations of the measurement system), the terms “approximately” or “about” as used herein include the stated value and mean within an acceptable range of deviation for a particular value as determined by one of ordinary skill in the art. For example, “approximately” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0062] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. Unless the context clearly indicates otherwise, as used herein, “a,” “an,” “the,” and “at least one” do not indicate a limitation of quantity and are intended to include both singular and plural forms. Therefore, in the claims, a reference to “the” element following a reference to “a” element includes one element and multiple elements. For example, unless the context clearly indicates otherwise, “element” has the same meaning as “at least one element.” “At least one” should not be construed as limiting “a” or “an.” “Or” means “and / or.” In the specification and claims, for the purposes of their meaning and interpretation, the term “and / or” is intended to include any combination of the terms “and” and “or.” For example, “A and / or B” can be understood to mean “A, B, or A and B.” The terms “and” and “or” can be used in the sense of conjunction or disjunction and can be understood as equivalent to “and / or.” In the specification and claims, for purposes of meaning and interpretation, the phrase “at least one of…” is intended to include the meaning of “at least one selected from…”. For example, “at least one of A and B” can be understood to mean “A, B, or A and B”.

[0063] Unless otherwise defined or implied, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure applies. It will also be understood that, unless clearly defined in this specification, terms (such as those defined in a general dictionary) shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formalized sense.

[0064] Embodiments are described herein with reference to cross-sectional views, which are schematic representations of preferred embodiments. Thus, variations in the shapes illustrated will be expected due to factors such as manufacturing techniques and / or tolerances. Therefore, the embodiments described herein should not be construed as limited to the specific shapes of the regions shown herein, but rather include deviations in shape due to factors such as manufacturing. For example, regions shown or described as flat may generally have rough and / or non-linear characteristics. Furthermore, sharp corners shown may be rounded. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the regions, nor are they intended to limit the scope of the claims.

[0065] In the following description, embodiments will be illustrated with reference to the accompanying drawings.

[0066] Figure 1 This is a perspective view showing a display device according to an embodiment. Figure 2 It is shown Figure 1 A plan view of the display device. Figure 3 It is along Figure 2 A cross-sectional view taken from line A-A'.

[0067] Reference Figure 1 and Figure 2 The display device 100 according to the embodiment is a device for displaying moving or still images, and can be used as a display screen for various devices such as televisions, laptops, monitors, billboards and Internet of Things (IoT) devices, as well as portable electronic devices such as mobile phones, smartphones, tablet PCs, smartwatches, watch phones, mobile communication terminals, e-notebooks, e-books, portable multimedia players (PMPs), navigation devices and ultra-mobile PCs (UMPCs).

[0068] Display device 100 may be an organic light-emitting display, such as an organic light-emitting display including organic light-emitting diodes, a quantum dot light-emitting display including a quantum dot light-emitting layer, an inorganic light-emitting display including inorganic semiconductors, or a micro light-emitting display including micron or nano light-emitting diodes (LEDs). In the following description, an embodiment of display device 100 as an organic light-emitting display will be primarily described. However, this disclosure is not limited thereto and can be applied to display devices including organic insulating materials, organic light-emitting materials, and metallic materials.

[0069] The display device 100 may be formed as flat, but is not limited thereto. For example, in an embodiment, the display device 100 may include curved portions formed at the left and right ends and having a constant or varying curvature. In an embodiment, the display device 100 may be formed as flexible, such that the display device 100 can be bent, folded, rolled up, or bent.

[0070] like Figure 1 , Figure 2 and Figure 3 As shown, the display device 100 according to an embodiment may include a substrate 110.

[0071] The substrate 110 may include a main region MA corresponding to the display surface of the display device 100 and a sub-region SBA protruding from one side of the main region MA.

[0072] like Figure 2 As shown, the main area MA may include a display area DA located in most of the central area of ​​the main area MA and a non-display area NDA located in the peripheral area of ​​the main area MA surrounding the display area DA.

[0073] In a planar view (or when viewed in a third direction DR3), the display area DA can be formed as a rectangle having a short side extending in a first direction DR1 and a long side extending in a second direction DR2 intersecting the first direction DR1. Here, the third direction DR3 can be a direction perpendicular to the first direction DR1 and the second direction DR2, or the thickness direction of the display device 100 or the substrate 110. The corner where the short side in the first direction DR1 intersects the long side in the second direction DR2 can be rounded to have a predetermined curvature or can be right angled. The planar shape of the display area DA is not limited to a rectangular shape, and can also be formed as another polygonal shape, a circular shape, or an elliptical shape.

[0074] The non-display area NDA can be set at the edge of the main area MA to surround the display area DA.

[0075] Sub-region SBA can be a region that protrudes or extends from the non-display area NDA of the main region MA to one side of the second direction DR2.

[0076] The display device 100 may include a display driving circuit 200 disposed in a sub-area SBA and a display circuit board 300 coupled to one side of the sub-area SBA.

[0077] Figure 2 and Figure 3 An embodiment of a display device 100 is shown in which a portion of the sub-area SBA is in a bent state.

[0078] like Figure 2 and Figure 3 As shown, a portion of the sub-region SBA is transformed into a curved shape, allowing another portion of the sub-region SBA to be disposed on the rear surface of the display device 100.

[0079] Reference Figure 3 According to an embodiment, the display device 100 includes a substrate 110, a circuit layer 120 disposed on the substrate 110, and a component layer 130 disposed on the circuit layer 120.

[0080] The display device 100 according to the embodiment may further include an encapsulation layer 140 disposed on the component layer 130 and a touch sensor layer 150 disposed on the encapsulation layer 140.

[0081] Furthermore, the display device 100 according to the embodiment may also include a polarization layer 160 disposed on the touch sensor layer 150 to reduce the reflection of external light.

[0082] The substrate 110 may include or be formed of an insulating material such as a polymeric resin. In embodiments, for example, the substrate 110 may be formed of polyimide. The substrate 110 may be a flexible substrate that can be bent, folded, or rolled up.

[0083] Alternatively, the substrate 110 may include an insulating material such as glass or be formed of an insulating material such as glass.

[0084] The substrate 110 may include a main area MA and a sub-area SBA. The main area MA may include a display area DA and a non-display area NDA.

[0085] The display device 100 may further include a display driving circuit 200 disposed in a sub-area SBA, a display circuit board 300 coupled to one side of the sub-area SBA, and a touch driving circuit 400 mounted on the display circuit board 300.

[0086] The display driver circuit 200 can transmit the data signal Vdata (see...) Figure 5 The data line DL supplied to circuit layer 120 (see...) Figure 5 ).

[0087] The display circuit board 300 can be connected to the signal pads located at the edge of the sub-area SBA, and can be electrically connected to the circuit layer 120 or the display driver circuit 200.

[0088] The touch driver circuit 400 can be electrically connected to the touch sensor layer 150.

[0089] Circuit layer 120 may include an insulating layer, a conductive layer, and one or more semiconductor layers. One or more insulating layers may be interposed between the conductive layer and one or more semiconductor layers. Circuit layer 120 may include transistors defined or formed by one or more semiconductor layers and one or more conductive layers, and signal lines defined or formed by at least one of the free conductive layers.

[0090] The element layer 130 may include light-emitting elements.

[0091] The encapsulation layer 140 can cover the circuit layer 120 and the component layer 130, and can prevent oxygen or moisture from penetrating into the component layer 130.

[0092] The touch sensor layer 150 may include touch electrodes and touch lines connected to the touch electrodes.

[0093] The touch driving circuit 400 can apply touch driving signals to the driving lines of the touch sensor layer 150 and receive touch sensing signals from the sensing lines. Furthermore, the touch driving circuit 400 can detect the amount of charge change in a capacitor based on the touch sensing signals to determine whether a user touch has occurred or whether a user has approached. A user touch means that an object such as a pen or a user's finger makes direct contact with the top surface of the overlay window disposed on the touch sensor layer. A user approach means that an object such as a pen or a user's finger hovers over the uppermost surface of the display device 100 (e.g., the top surface of the overlay window). The touch driving circuit 400 can output touch data, including the user's touch coordinates, to the main processor.

[0094] Figure 4 It is shown Figure 2 A magnified plan view of part B.

[0095] Reference Figure 4 Also refer to Figure 2 According to an embodiment, the display area DA of the display device 100 may include an emission area EA. Furthermore, the display area DA may also include a non-emission area disposed in the gap between the emission areas EA.

[0096] Component layer 130 (see) Figure 3 This may include light-emitting elements LE, which are respectively disposed in the emission region EA (see Figure 5 ).

[0097] Circuit layer 120 (see Figure 3 The main region MA may include light-emitting pixel drivers EPDs arranged side-by-side in a first direction DR1 and a second direction DR2. The light-emitting pixel drivers EPDs may be electrically connected to light-emitting elements LEs of the element layer 130 (see [link to image]). Figure 5 ).

[0098] In an embodiment, the emission region EA may have a rhomboid or rectangular shape in a planar view. However, this is merely an example, and the planar shape of the emission region EA according to the embodiment is not limited to... Figure 4 The planar shape shown is illustrated. In another embodiment, in the planar view, the emission region EA can have a polygonal shape such as a square, pentagon, hexagon, etc., or it can have a circular or elliptical shape including curved edges.

[0099] The emission region EA may include a first emission region EA1 for emitting light of a first color in a predetermined wavelength band, a second emission region EA2 for emitting light of a second color in a wavelength band lower than the first color, and a third emission region EA3 for emitting light of a third color in a wavelength band lower than the second color.

[0100] For example, the first color could be red with a wavelength ranging from approximately 600 nanometers (nm) to approximately 750 nm. The second color could be green with a wavelength ranging from approximately 480 nm to approximately 560 nm. The third color could be blue with a wavelength ranging from approximately 370 nm to approximately 460 nm.

[0101] The first transmission area EA1 and the third transmission area EA3 can be alternately set on at least one of the first direction DR1 and the second direction DR2.

[0102] The second launch area EA2 can be arranged side by side with each other on at least one of the first direction DR1 and the second direction DR2.

[0103] Furthermore, the second launch area EA2 can be adjacent to the first launch area EA1 and the third launch area EA3 on the diagonal directions DR4 and DR5 that intersect the first direction DR1 and the second direction DR2.

[0104] The pixel PX used to display the brightness and color of the pixel itself can be provided by the first emission region EA1, the second emission region EA2 and the third emission region EA3 that are adjacent to each other among these emission regions EA.

[0105] In other words, a pixel (PX) can be the basic unit used to display various colors, including white, at a predetermined brightness.

[0106] Each of the pixels PX may include at least one first emission region EA1, at least one second emission region EA2, and at least one third emission region EA3 that are adjacent to each other. Therefore, each of the pixels PX can display various colors by mixing the light emitted from the adjacent first emission region EA1, second emission region EA2, and third emission region EA3.

[0107] Figure 5 This illustrates an embodiment. Figure 4 The equivalent circuit diagram of the light-emitting pixel driver.

[0108] Reference Figure 5 In this embodiment, circuit layer 120 (see...) Figure 3 The light-emitting pixel driver EPD can be electrically connected to the first power ELVDD and the element layer 130 (see...). Figure 3 Between the light-emitting elements LE.

[0109] One of the light-emitting elements LE in element layer 130 can be electrically connected between one of the light-emitting pixel drivers EPD in circuit layer 120 and the second power ELVSS.

[0110] In other words, the anode electrode of the light-emitting element LE is electrically connected to the light-emitting pixel driver EPD, and the cathode electrode of the light-emitting element LE can be applied with a second power ELVSS that is lower than the first power ELVDD.

[0111] exist Figure 5 In this context, the capacitor Cel connected in parallel with the light-emitting element LE refers to the parasitic capacitance between the anode and cathode electrodes.

[0112] The circuit layer 120 may include a first power line VDL for transmitting a first power ELVDD, a gate initialization voltage line VGIL for transmitting a gate initialization voltage VGINT, and an anode initialization voltage line VAIL for transmitting an anode initialization voltage VAINT.

[0113] The circuit layer 120 may include a gate line GL electrically connected to at least one gate electrode of transistors T1 to T7 provided in each of the light-emitting pixel drivers EPD.

[0114] The gate line GL may include a scan write line GWL for transmitting the scan write signal GW, a scan initialization line GIL for transmitting the scan initialization signal GI, an emit control line ECL for transmitting the emit control signal EC, and a gate control line GCL for transmitting the gate control signal GC.

[0115] A light-emitting pixel driver EPD of circuit layer 120 may include a first transistor T1 that generates a drive current for driving the light-emitting element LE, two or more transistors T2 to T7 electrically connected to the first transistor T1, and at least one pixel capacitor PC1.

[0116] The first transistor T1 can be electrically connected between a first node N1 and a second node N2. The first node N1 is electrically connected to the first electrode (e.g., the source electrode) of the first transistor T1. The second node N2 is electrically connected to the second electrode (e.g., the drain electrode) of the first transistor T1.

[0117] The first node N1 can be electrically connected to the first power line VDL through the fifth transistor T5.

[0118] The second node N2 can be electrically connected to the anode electrode of the light-emitting element LE through the sixth transistor T6.

[0119] Pixel capacitor PC1 can be electrically connected between the first power line VDL and the third node N3. The third node N3 is electrically connected to the gate electrode of the first transistor T1.

[0120] In other words, the gate electrode of the first transistor T1 can be electrically connected to the first power line VDL through the pixel capacitor PC1.

[0121] Therefore, the potential of the gate electrode of the first transistor T1 can be maintained at the voltage charged into the pixel capacitor PC1.

[0122] The second transistor T2 can be electrically connected between the data line DL and the first node N1.

[0123] The second transistor T2 can be electrically connected between the first electrode of the first transistor T1 and the data line DL.

[0124] In other words, the first electrode of the first transistor T1 can be electrically connected to the data line DL through the second transistor T2.

[0125] The second transistor T2 can be turned on by the scan write signal GW of the scan write line GWL.

[0126] The fifth transistor T5 can be electrically connected between the first node N1 and the first power line VDL.

[0127] The sixth transistor T6 can be electrically connected between the second node N2 and the fourth node N4. The fourth node N4 is electrically connected to the anode electrode of the light-emitting element LE.

[0128] In other words, the fifth transistor T5 can be electrically connected between the first electrode of the first transistor T1 and the first power line VDL.

[0129] The sixth transistor T6 can be electrically connected between the second electrode of the first transistor T1 and the anode electrode of the light-emitting element LE.

[0130] The fifth transistor T5 and the sixth transistor T6 can be turned on by the emit control signal EC of the emit control line ECL.

[0131] When the data signal Vdata of the data line DL is transmitted to the first electrode of the first transistor T1 through the conducting second transistor T2, the voltage difference between the gate electrode of the first transistor T1 and the first electrode of the first transistor T1 can be the voltage difference between the first power ELVDD and the data signal Vdata.

[0132] In this case, when the voltage difference between the gate electrode and the first electrode of the first transistor T1 (i.e., the gate-source voltage difference) becomes equal to or greater than the threshold voltage, the first transistor T1 can be turned on, thereby generating the drain-source current of the first transistor T1 corresponding to the data signal Vdata.

[0133] Subsequently, when the fifth transistor T5 and the sixth transistor T6 are turned on, the first power supply ELVDD, the first transistor T1, the light-emitting element LE, and the second power supply ELVSS can be connected in series. Therefore, the drain-source current of the first transistor T1 corresponding to the data signal Vdata can be supplied as the driving current for the light-emitting element LE.

[0134] Therefore, the light-emitting element LE can emit light with a brightness corresponding to the data signal Vdata.

[0135] The third transistor T3 can be electrically connected between the second node N2 and the third node N3. That is, the third transistor T3 can be electrically connected between the gate electrode of the first transistor T1 and the second electrode of the first transistor T1.

[0136] The third transistor T3 may include a plurality of sub-transistors connected in series. In an embodiment, for example, the third transistor T3 may include a first sub-transistor T31 and a second sub-transistor T32.

[0137] The first electrode of the first sub-transistor T31 can be connected to the gate electrode of the first transistor T1, the second electrode of the first sub-transistor T31 can be connected to the first electrode of the second sub-transistor T32, and the second electrode of the second sub-transistor T32 can be connected to the second electrode of the first transistor T1.

[0138] In such an embodiment, the potential of the gate electrode of the first transistor T1 can be effectively prevented from changing due to leakage current caused by the non-conducting third transistor T3.

[0139] The first sub-transistor T31 and the second sub-transistor T32 can be turned on by the scan write signal GW of the scan write line GWL.

[0140] When the first sub-transistor T31 and the second sub-transistor T32 are turned on, the voltage difference between the second node N2 and the third node N3 can be initialized.

[0141] The fourth transistor T4 can be electrically connected between the gate initialization voltage line VGIL and the third node N3. That is, the fourth transistor T4 can be connected between the gate electrode of the first transistor T1 and the gate initialization voltage line VGIL.

[0142] The fourth transistor T4 may include a plurality of sub-transistors connected in series. In an embodiment, for example, the fourth transistor T4 may include a third sub-transistor T41 and a fourth sub-transistor T42.

[0143] The first electrode of the third sub-transistor T41 can be connected to the gate electrode of the first transistor T1, the second electrode of the third sub-transistor T41 can be connected to the first electrode of the fourth sub-transistor T42, and the second electrode of the fourth sub-transistor T42 can be connected to the gate initialization voltage line VGIL.

[0144] In such an embodiment, the potential of the gate electrode of the first transistor T1 can be effectively prevented from changing due to leakage current caused by the non-conducting fourth transistor T4.

[0145] The third sub-transistor T41 and the fourth sub-transistor T42 can be turned on by the scan initialization signal GI of the scan initialization line GIL.

[0146] When the third sub-transistor T41 and the fourth sub-transistor T42 are turned on, the potential of the third node N3 can be initialized to the gate initialization voltage VGINT.

[0147] The seventh transistor T7 can be electrically connected between the fourth node N4 and the anode initialization voltage line VAIL. In other words, the seventh transistor T7 can be electrically connected between the anode electrode of the light-emitting element LE and the anode initialization voltage line VAIL.

[0148] The seventh transistor T7 can be turned on by the gate control signal GC of the gate control line GCL.

[0149] With the seventh transistor T7 turned on, the potential of the fourth node N4 can be initialized to the anode initialization voltage VAINT.

[0150] like Figure 5 As shown, according to an embodiment, the first transistor T1 to the seventh transistor T7 can be provided as a P-type metal-oxide-semiconductor field-effect transistor (MOSFET).

[0151] Figure 6 It is shown Figure 5 The light-emitting element and cross-sectional view of the first transistor and the sixth transistor.

[0152] Reference Figure 6 The display device 100 according to the embodiment may include a substrate 110, a circuit layer 120 on the substrate 110, and a component layer 130 on the circuit layer 120.

[0153] The display device 100 according to the embodiment may further include an encapsulation layer 140 on the component layer 130, a touch sensor layer 150 on the encapsulation layer 140, and a polarization layer 160 on the touch sensor layer 150.

[0154] According to an embodiment, the circuit layer 120 may include a substrate buffer layer 121 disposed on a substrate 110, a semiconductor layer (channel portion CH1, first electrode portion E11, second electrode portion E21, channel portion CH6, first electrode portion E16 and second electrode portion E26) disposed on the substrate buffer layer 121, a first gate insulating layer 122 covering the semiconductor layer, a first gate conductive layer (gate electrodes G1 and G6) disposed on the first gate insulating layer 122, a second gate insulating layer 123 covering the first gate conductive layer, a second gate conductive layer (capacitor electrode CAE) disposed on the second gate insulating layer 123, and an interlayer insulating layer 124 covering the second gate conductive layer (capacitor electrode CAE).

[0155] In addition, the circuit layer 120 may also include a first source-drain conductive layer ANDE1 disposed on the interlayer insulating layer 124, a first planarization layer 125 covering the first source-drain conductive layer ANDE1, a second source-drain conductive layer ANDE2 disposed on the first planarization layer 125, and a second planarization layer 126 covering the second source-drain conductive layer ANDE2.

[0156] The circuit layer 120 may include light-emitting pixel drivers EPDs corresponding to the emission regions EA, respectively.

[0157] Each of the light-emitting pixel drivers (EPD) may include a first transistor T1, and second transistors T2 through T7 electrically connected to the first transistor T1 (see [link to EPD]). Figure 5 ), and at least one pixel capacitor PC1 (see Figure 5 ).

[0158] The channel portion, first electrode portion, and second electrode portion of each of the P-type MOSFETs can be disposed in the semiconductor layer on the substrate buffer layer 121.

[0159] That is, the channel portions CH1 and CH6, the first electrode portions E11 and E16, and the second electrode portions E21 and E26 of each of the first transistors T1 to the seventh transistors T7 can be disposed in the semiconductor layer on the substrate buffer layer 121 (or defined by a portion of the semiconductor layer on the substrate buffer layer 121).

[0160] In each of the first transistor T1 and the sixth transistor T6, the first electrode portions E11 and E16 can be connected to one end of the channel portions CH1 and CH6, and the second electrode portions E21 and E26 can be connected to the other end of the channel portions CH1 and CH6.

[0161] The second electrode portion E21 of the first transistor T1 can be connected to the first electrode portion E16 of the sixth transistor T6.

[0162] The gate electrode of each of the P-type MOSFETs can be disposed in the first gate conductive layer on the first gate insulating layer 122.

[0163] In other words, the gate electrodes G1 and G6 of the first transistor T1 to the seventh transistor T7 can be disposed in or defined by the first gate conductive layer on the first gate insulating layer 122.

[0164] In the first transistor T1 and the sixth transistor T6, the gate electrodes G1 and G6 can overlap with the channel portions CH1 and CH6, respectively.

[0165] exist Figure 5 In the light-emitting pixel driver EPD, the second transistor T2, the first sub-transistor T31, the second sub-transistor T32, the third sub-transistor T41, the fourth sub-transistor T42, and the fifth transistor T5 and the seventh transistor T7 are provided as the same P-type MOSFETs as the first transistor T1 and the sixth transistor T6, so any repeated detailed descriptions of them will be omitted or simplified.

[0166] For pixel capacitor PC1 (see) Figure 5 The capacitor electrode CAE can be disposed in or defined by the second gate conductive layer on the second gate insulating layer 123.

[0167] The capacitor electrode CAE can overlap with the gate electrode G1 of the first transistor T1.

[0168] Therefore, pixel capacitor PC1 (see Figure 5 The region can be provided or defined by the overlapping area between the capacitor electrode CAE and the gate electrode G1 of the first transistor T1.

[0169] The first source-drain conductive layer ANDE1 on the interlayer insulating layer 124 may include a first anode connection electrode ANCE1.

[0170] The first anode connection electrode ANCE1 can be electrically connected to the second electrode portion E26 of the sixth transistor T6 through the first anode connection hole ANCH1.

[0171] The second source-drain conductive layer ANDE2 on the first planarization layer 125 may include a second anode connection electrode ANCE2.

[0172] The second anode connection electrode ANCE2 can be electrically connected to the first anode connection electrode ANCE1 through the second anode connection hole ANCH2.

[0173] The anode electrode 131 of the element layer 130 can be disposed on the second planarization layer 126 and can be electrically connected to the second anode connection electrode ANCE2 through the third anode connection hole ANCH3.

[0174] Therefore, the anode electrode 131 can be electrically connected to the second electrode portion E26 of the sixth transistor T6 via the first anode connection electrode ANCE1 and the second anode connection electrode ANCE2.

[0175] The component layer 130 on the circuit layer 120 may include light-emitting elements LE respectively disposed in the emission regions EA1, EA2 and EA3.

[0176] Each of the plurality of light-emitting elements LE may include a structure in which a light-emitting layer 133 is disposed between an anode electrode 131 and a cathode electrode 134 facing each other.

[0177] According to an embodiment, the element layer 130 may include an anode electrode 131 disposed in the emission region EA, a pixel defining layer 132 disposed in the non-emission region NEA and covering the edge portion of the anode electrode 131, a spacer layer 132' disposed on a portion of the pixel defining layer 132, a light-emitting layer 133 disposed on the anode electrode 131, and a cathode electrode 134 disposed on the light-emitting layer 133, the pixel defining layer 132, and the spacer layer 132'.

[0178] Each of the plurality of light-emitting elements LE may further include a first common layer disposed between the anode electrode 131 and the light-emitting layer 133, and a second common layer disposed between the light-emitting layer 133 and the cathode electrode 134.

[0179] The encapsulation layer 140 can be disposed on the circuit layer 120 and cover the component layer 130.

[0180] Encapsulation layer 140 can be provided to prevent oxygen or moisture from penetrating into component layer 130 and to reduce electrical or physical effects on circuit layer 120 and component layer 130.

[0181] The encapsulation layer 140 may include a first encapsulation layer 141 disposed on the component layer 130 and comprising an inorganic insulating material, a second encapsulation layer 142 disposed on the first encapsulation layer 141 and comprising an organic insulating material, and a third encapsulation layer 143 covering the second encapsulation layer 142 and comprising an inorganic insulating material.

[0182] The touch sensor layer 150 can be disposed on the encapsulation layer 140.

[0183] The polarization layer 160 can be disposed on the touch sensor layer 150.

[0184] Figure 7 This illustrates an embodiment. Figure 2 Plan view of part C.

[0185] Reference Figure 7 The display device 100 according to the embodiment (see Figure 2 Circuit layer 120 (see) Figure 3 This includes components electrically connected to element layer 130 (see [link]). Figure 3 The light-emitting element LE (see) Figure 6 The light-emitting pixel driver EPD is used to transmit gate signals GI, GW, EC, and GC (see [link]). Figure 5 The gate line GL (scan initialization line GIL, scan write line GWL, emission control line ECL and gate control line GCL) transmitted to the light-emitting pixel driver EPD, the gate drive region GDRA containing multiple levels of GIST, GWST and ECST disposed in the non-display region NDA and electrically connected to the gate line GL respectively, and the grid GRD formed in the display region DA and the non-display region NDA.

[0186] According to an embodiment, the non-display area NDA may include a gate driving region GDRA in which a gate driving circuit is disposed, an extension line region GEA disposed between the gate driving region GDRA and the display area DA, a dam region DMA surrounding the gate driving region GDRA and the display area DA, and a junction region JNA surrounding the dam region DMA.

[0187] In an embodiment, for example, the gate driving region GDRA may face at least one edge of the edge of the display region DA that extends in the second direction DR2.

[0188] The gate drive region GDRA may include a first circuit region GDC1, a second circuit region GDC2, and a third circuit region GDC3.

[0189] In an embodiment, for example, such as Figure 7 As shown, the first circuit region GDC1, the second circuit region GDC2, and the third circuit region GDC3 can be arranged adjacent to each other (or sequentially) in the first direction DR1.

[0190] In another embodiment, for example, the first circuit region GDC1 of the gate driving region GDRA may be configured to be closest to one side of the display region DA, and the third circuit region GDC3 of the gate driving region GDRA may be configured to be furthest from the substrate 110 (see [reference]). Figure 6 The corresponding or adjacent edge is closest.

[0191] However, this is merely an example, and some of the first circuit regions GDC1, the second circuit region GDC2, and the third circuit region GDC3 may face one side of the display region DA, while others of the first circuit regions GDC1, the second circuit region GDC2, and the third circuit region GDC3 may face other sides of the display region DA.

[0192] At least one dam section DM can be arranged in the dam area DMA.

[0193] The light-emitting pixel driver EPD can be arranged in a matrix in the display area DA in the first direction DR1 and the second direction DR2.

[0194] The gate line GL can extend in the first direction DR1.

[0195] The gate line GL may include a scan write line GWL for transmitting the scan write signal GW, a scan initialization line GIL for transmitting the scan initialization signal GI, an emit control line ECL for transmitting the emit control signal EC, and a gate control line GCL for transmitting the gate control signal GC.

[0196] The multiple stages GIST, GWST, and ECST of the gate drive circuit may include an initialization stage GIST arranged in a first circuit region GDC1 of the gate drive region GDRA, a write stage GWST arranged in a second circuit region GDC2 of the gate drive region GDRA, and an emit control stage ECST arranged in a third circuit region GDC3 of the gate drive region GDRA.

[0197] Each of the first circuit region GDC1, the second circuit region GDC2, and the third circuit region GDC3 can extend in the second direction DR2.

[0198] The first circuit region GDC1, the second circuit region GDC2, and the third circuit region GDC3 can be adjacent to each other in the first direction DR1.

[0199] The initialization stage GIST of the first circuit region GDC1 can be arranged side by side on the second direction DR2.

[0200] The initialization stage GIST can be electrically connected to the scan initialization line GIL and the gate control line GCL.

[0201] The write stage GWST of the second circuit region GDC2 can be arranged side by side on the second direction DR2.

[0202] The write stage GWST can be electrically connected to the scan write line GWL.

[0203] The transmit control stage ECST in the third circuit region GDC3 can be arranged side-by-side on the second direction DR2.

[0204] The transmit control stage ECST can be electrically connected to the transmit control line ECL.

[0205] According to an embodiment, circuit layer 120 (see...) Figure 3 It may also include a gate extension line (GEL) disposed in the extension line region (GEA).

[0206] The gate extension line GEL may include a first gate extension line GEL1 and a second gate extension line GEL2 disposed in or defined by different conductive layers (i.e., conductive layers disposed in different layers from each other).

[0207] Gate extension lines (GELs) can be electrically connected between multiple stages (GIST, GWST, and ECST) and gate lines (GLs).

[0208] The output terminals of multiple GIST, GWST and ECST stages can be electrically connected to the gate line GL via the gate extension line GEL.

[0209] Some output terminals of the multiple stages GIST, GWST and ECST, which are spaced apart from the extension line region GEA, can be electrically connected to the gate extension line GEL via the output line OPL.

[0210] In an embodiment, for example, each of the multiple levels GIST, GWST, and ECST may correspond to a row of pixels consisting of or corresponding to a light-emitting pixel driver EPD arranged side-by-side on the first direction DR1.

[0211] The output terminal of an initialization level GIST can be electrically connected to the scan initialization line GIL via a second gate extension line GEL2 located in a pixel row corresponding to the initialization level GIST, and can be electrically connected to the gate control line GCL located in another pixel row via a first gate extension line GEL1.

[0212] The output terminal of a write stage GWST can be electrically connected to the scan write line GWL via the write output line GWOPL and another second gate extension line GEL2 disposed in a pixel row corresponding to the write stage GWST.

[0213] The write output line GWOPL can be positioned between the output terminal of the write stage GWST and another second gate extension line GEL2.

[0214] In this embodiment, the second circuit region GDC2 may be adjacent to the extension line region GEA, and the write output line GWOPL may be omitted.

[0215] An output terminal of an Emit Control Stage (ECST) can be electrically connected to the Emit Control Line (ECL) via the Emit Control Output Line (ECOPL) and another second gate extension line (GEL2) located in a pixel row corresponding to the Emit Control Stage (ECST).

[0216] The transmit control output line ECOPL can be positioned between the output terminal of the transmit control stage ECST and another second gate extension line GEL2.

[0217] In this embodiment, the third circuit region GDC3 is adjacent to the extension line region GEA, and the transmit control output line ECOPL can be omitted.

[0218] According to an embodiment, circuit layer 120 (see...) Figure 3 It may also include a supply line SPL disposed in the non-display area NDA and surrounding at least a portion of the edge of the display area DA.

[0219] A portion of the supply line SPL can overlap with the gate drive region GDRA.

[0220] In other words, at least some of the multiple levels of GIST, GWST, and ECST can overlap with the supply line SPL.

[0221] The supply line SPL can transmit the first power ELVDD (see...) Figure 5 ), Second Electricity ELVSS (see Figure 5 ), gate initialization voltage VGINT (see Figure 5 ) and anode initialization voltage VAINT (see Figure 5 ).

[0222] Circuit layer 120 (see Figure 3 It may include one or more supply lines SPL that overlap with the gate drive region GDRA.

[0223] According to an embodiment, circuit layer 120 (see...) Figure 3 This includes the grid GRD formed in the display area DA and the non-display area NDA.

[0224] The grid GRD can be formed in at least some of the boundaries between the light-emitting pixel drivers EPD and in at least some of the boundaries between multiple levels GIST, GWST and ECST.

[0225] The grid GRD can be defined by a groove formed through a portion disposed in circuit layer 120 (see...). Figure 6 The substrate 110 in ) (see Figure 6 ) and includes two or more insulating layers of inorganic insulating material. Figure 6 The portion of the substrate buffer layer 121, the first gate insulating layer 122, the second gate insulating layer 123, and the interlayer insulating layer 124.

[0226] The grid GRD may include a first extended groove EXG1 and a second extended groove EXG2 that intersects with the first extended groove EXG1.

[0227] The first extended groove EXG1 may have a straight line shape extending in the first direction DR1 when viewed in a plan view or when viewed in the third direction DR3.

[0228] The second extension groove EXG2 may have a straight line shape extending in the second direction DR2 when viewed in a plan view or when viewed in the third direction DR3.

[0229] On the second direction DR2 extending from the second extension groove EXG2, one or more light-emitting pixel drivers EPD and one or more levels GIST, GWST and ECST can be disposed between the first extension groove EXG1.

[0230] That is, the first extended groove EXG1 can be formed at the boundary of the light-emitting pixel driver EPD at intervals of one or more light-emitting pixel drivers EPD.

[0231] Alternatively, the first extended groove EXG1 may be formed side-by-side to the boundaries of the multiple levels of GIST, GWST and ECST at intervals of one or more levels of GIST, GWST and ECST.

[0232] On the first direction DR1 extending from the first extension groove EXG1, one or more light-emitting pixel drivers EPDs may be disposed in the second extension groove EXG2, which is disposed in the display area DA.

[0233] In other words, some of the second extended grooves EXG2 provided in the display area DA can be formed at the boundary of the light-emitting pixel driver EPD at intervals of one or more light-emitting pixel drivers EPD.

[0234] In the first direction DR1, some other extension grooves in the second extension groove EXG2 disposed in the non-display area NDA may be formed between the first circuit area GDC1, the second circuit area GDC2 and the third circuit area GDC3.

[0235] In the first direction DR1, the two second extension grooves EXG2 can be respectively set on opposite sides of the extension line region GEA.

[0236] Figure 8 It is according to the embodiment along Figure 7 The cross-sectional view taken by line D-D'. Figure 9 It is according to the embodiment along Figure 7 A cross-sectional view taken from line E-E'.

[0237] Reference Figure 8 and Figure 9 The display device 100 according to the embodiment (see Figure 2 The circuit layer 120 may include a grid GRD and a filled grid GRD and includes a grid-filled layer GFL of organic insulating material.

[0238] The grid GRD can be formed or defined through portions of each of two or more insulating layers comprising inorganic insulating material (i.e., substrate buffer layer 121, first gate insulating layer 122, second gate insulating layer 123, and interlayer insulating layer 124).

[0239] Therefore, the grid GRD can reach or expose a portion of each of the substrate 110, the first gate conductive layer on the first gate insulating layer 122, and the second gate conductive layer on the second gate insulating layer 123, i.e., the grid fill layer GFL contacts a portion of each of the substrate 110, the first gate conductive layer on the first gate insulating layer 122, and the second gate conductive layer on the second gate insulating layer 123.

[0240] In other words, during the etching of two or more insulating layers (i.e., substrate buffer layer 121, first gate insulating layer 122, second gate insulating layer 123 and interlayer insulating layer 124) to form a gate GRD, the first gate conductive layer and the second gate conductive layer can be used as etch barrier layers.

[0241] In other words, during the etching of two or more insulating layers (i.e., base buffer layer 121, first gate insulating layer 122, second gate insulating layer 123 and interlayer insulating layer 124) to form a gate GRD, a portion of each of the base buffer layer 121 and the first gate insulating layer 122 disposed below the first gate conductive layer can be retained through the first gate conductive layer.

[0242] Furthermore, during the etching of two or more insulating layers (i.e., the base buffer layer 121, the first gate insulating layer 122, the second gate insulating layer 123, and the interlayer insulating layer 124) to form the gate GRD, a portion of each of the base buffer layer 121, the first gate insulating layer 122, and the second gate insulating layer 123 disposed below the second gate conductive layer can be retained through the second gate conductive layer.

[0243] Therefore, a portion of the first gate conductive layer of the grid GRD that intersects with the first gate conductive layer can contact (or expose the first gate conductive layer), another portion of the second gate conductive layer of the grid GRD that intersects with the second gate conductive layer can contact (or expose the second gate conductive layer), and the remaining portion of the grid GRD can contact (or expose the substrate 110).

[0244] Furthermore, as described above, the grid GRD can be formed in at least some of the boundaries between the light-emitting pixel drivers EPD and in at least some of the boundaries between multiple levels GIST, GWST and ECST.

[0245] Therefore, transistors T1 to T7 (see) are used to provide each of the light-emitting pixel drivers in the EPD. Figure 5 ) and the semiconductor layers of transistors in each of the multiple levels of GIST, GWST, and ECST (channel portion CH1, first electrode portion E11, second electrode portion E21, channel portion CH6, first electrode portion E16, and second electrode portion E26) (see Figure 6 It can be without contact with the grid GRD (or be exposed to the grid GRD).

[0246] In other words, the grid GRD can be connected to the semiconductor layer (channel portion CH1, first electrode portion E11, second electrode portion E21, channel portion CH6, first electrode portion E16, and second electrode portion E26) in a planar diagram (see...). Figure 6 () are separated.

[0247] According to an embodiment, circuit layer 120 may include a grid fill layer GFL of a grid filler GRD.

[0248] The grid filler layer (GFL) may include organic insulating materials.

[0249] In one embodiment, for example, the grid fill layer GFL may be provided together with the first planarization layer 125. In such an embodiment, the number of stacking processes can be reduced, and the manufacturing process of the display device 100 can be further simplified.

[0250] In another embodiment, for example, the grid fill layer GFL may be provided before the process of disposing the first source-drain conductive layer on the interlayer insulating layer 124, and the first planarization layer 125 may be provided after the process of disposing the source-drain conductive layer. In such an embodiment, the disposition of the first source-drain conductive layer is facilitated because the first source-drain conductive layer can be disposed on the grid fill layer GFL.

[0251] As described above, since the display device 100 according to the embodiment includes a grid filling layer GFL, which fills the grid GRD and includes an organic insulating material, and the organic insulating material has higher elasticity than the inorganic insulating material, deformation or damage to the display device 100 caused by external impact can be reduced.

[0252] Furthermore, according to the embodiment, the grid GRD is not only set in the display area DA (see Figure 7 Furthermore, it is located in the gate drive region GDRA of the non-display area NDA, which reduces the damage to the gate drive circuit caused by external impacts.

[0253] Therefore, in such an embodiment, the display device 100 can robustly resist external impacts, thereby improving the convenience and lifespan of the display device 100.

[0254] like Figure 8 As shown, each of the scan write line GWL and the first gate extension line GEL1 may be disposed in or defined by the first gate conductive layer on the first gate insulating layer 122, or disposed in or defined by the second gate conductive layer on the second gate insulating layer 123.

[0255] In an embodiment, for example, the first gate extension line GEL1 may be alternately disposed in or defined by the first gate conductive layer on the first gate insulating layer 122, or disposed in or defined by the second gate conductive layer on the second gate insulating layer 123.

[0256] Each of the second gate extension lines GEL2 can be disposed in or defined by the first source-drain conductive layer on the interlayer insulating layer 124.

[0257] In each of the output lines ECOPL and GWOPL, a portion may be disposed in or defined by the first source-drain conductive layer on the interlayer insulating layer 124, and other portions may be disposed in or defined by the first gate conductive layer on the first gate insulating layer 122, or disposed in or defined by the second gate conductive layer on the second gate insulating layer 123.

[0258] The supply line SPL can be located in the second source-drain conductive layer on the first planarization layer 125.

[0259] According to an embodiment, at least one dam section DM can be arranged in the dam area DMA.

[0260] At least one dam section DM1 and DM2 is provided to limit the diffusion range of the organic insulating material of the second encapsulation layer 142 of the encapsulation layer 140.

[0261] At least one dam section DM1 and DM2 may include two or more dam layers DML11, DML21, DML31, DML12, DML22, DML32 and DML42.

[0262] Each of two or more dam layers DML11, DML21, DML31, DML12, DML22, DML32, and DML42 may be disposed in the same layer as a corresponding one of the first planarization layer 125, the second planarization layer 126, the pixel defining layer 132, and the spacer layer 132' (or directly on the same layer as a corresponding one of the first planarization layer 125, the second planarization layer 126, the pixel defining layer 132, and the spacer layer 132').

[0263] In an embodiment, for example, at least one dam section DM may include a first dam section DM1 surrounding the display area DA and a second dam section DM2 surrounding the first dam section DM1.

[0264] The first dam portion DM1 may include a first dam layer DML11 disposed in the same layer as the second planarization layer 126 (or directly on the same layer as the second planarization layer 126), a second dam layer DML21 disposed in the same layer as the pixel defining layer 132 (or directly on the same layer as the pixel defining layer 132), and a third dam layer DML31 disposed in the same layer as the spacer layer 132' (or directly on the same layer as the spacer layer 132').

[0265] The second dam portion DM2 may include a first dam layer DML12 disposed in the same layer as the first planarization layer 125 (or directly on the same layer as the first planarization layer 125), a second dam layer DML22 disposed in the same layer as the second planarization layer 126 (or directly on the same layer as the second planarization layer 126), a third dam layer DML32 disposed in the same layer as the pixel defining layer 132 (or directly on the same layer as the pixel defining layer 132), and a fourth dam layer DML42 disposed in the same layer as the spacer layer 132' (or directly on the same layer as the spacer layer 132').

[0266] In the bonding region JNA, the first encapsulation layer 141 of the encapsulation layer 140 can contact the interlayer insulating layer 124 of the circuit layer 120.

[0267] In addition, the third encapsulation layer 143 may contact the first encapsulation layer 141 or the interlayer insulating layer 124 in the bonding region JNA.

[0268] Therefore, a bonding structure between inorganic insulating materials can be provided in the bonding region JNA.

[0269] Figure 10 It is according to the embodiment along Figure 7 A cross-sectional view taken from line E-E'. Figure 11 and Figure 12 This illustrates an embodiment. Figure 8 Enlarged views of parts F and G.

[0270] In addition to the grid buffer layer GBFL set between the grid GRD and the grid fill layer GFL, Figure 10 , Figure 11 and Figure 12 The display device 100 shown according to an embodiment (see also...) Figure 1 )and Figures 1 to 9 The display device 100 shown according to the embodiment is substantially the same. Therefore, any repeated detailed descriptions of elements that are the same as or identical to those described above will be omitted.

[0271] The grid buffer layer GBFL may cover a portion of each of the substrate 110, the first gate conductive layer, and the second gate conductive layer exposed by the grid GRD, as well as the side surface of each of the substrate buffer layer 121, the first gate insulating layer 122, the second gate insulating layer 123, and the interlayer insulating layer 124.

[0272] The grid buffer layer GBFL may include inorganic insulating materials.

[0273] The grid fill layer GFL can be set on the grid buffer layer GBFL.

[0274] As described above, according to the embodiment, the grid buffer layer GBFL can be disposed between the portion of the substrate 110 exposed by the grid GRD and the grid fill layer GFL. Therefore, oxygen or moisture that may penetrate into the organic insulating material of the grid fill layer GFL through the substrate 110 can be blocked by the grid buffer layer GBFL. Thus, the reduction in the lifespan of the display device 100 due to the grid GRD and the grid fill layer GFL can be effectively prevented.

[0275] Figure 13 This illustrates an embodiment. Figure 2 Plan view of part C. Figure 14 It is along Figure 13 A cross-sectional view taken from line E-E'. Figure 15 This illustrates an embodiment. Figure 2 Plan view of part C.

[0276] In addition to circuit layer 120 (see Figure 9 It also includes the area defined as two or more exposed holes EXH extending beyond the supply line SPL. Figure 13 , Figure 14 and Figure 15 The display device 100 shown according to an embodiment (see also...) Figure 1 )and Figures 1 to 12 The display device 100 shown according to the embodiment is substantially the same. Therefore, any repeated detailed descriptions of the same or identical elements will be omitted.

[0277] In an embodiment, such as Figure 13 As shown, two or more exposed holes EXH may be defined or formed to pass through the supply line SPL and spaced apart from each other.

[0278] In an embodiment, for example, two or more exposed holes EXH may be arranged in a matrix in the first direction DR1 and the second direction DR2.

[0279] like Figure 14 As shown, each of the two or more exposed holes EXH may be defined or formed to pass through the supply line SPL.

[0280] Therefore, the second planarization layer 126 can contact the first planarization layer 125 through two or more exposed holes EXH.

[0281] Two or more exposed orifices EXH can provide channels for venting gases contained in the organic insulating material in the first planarization layer 125 and the second planarization layer 126. Therefore, gases containing the organic insulating material can be readily vented through the exposed orifices EXH, thereby reducing warping defects in the supply line SPL.

[0282] According to an embodiment, the grid fill layer GFL of the filled grid GRD (see...) Figure 8 It includes organic insulating materials, such that gases contained in the organic insulating materials in the grid filling layer GFL can also be emitted through the exposed orifice EXH.

[0283] According to the embodiments, such as Figure 13 As shown, the grid GRD includes a first extended groove EXG1 and a second extended groove EXG2 that intersect each other.

[0284] Some of the intersecting portions between the first extended groove EXG1 and the second extended groove EXG2 may overlap with two or more exposed holes EXH.

[0285] In such an embodiment, the overlap area between the grid fill layer GFL and two or more exposed orifices EXH can be increased, thereby facilitating the emission of gases from the organic insulating material included in the grid fill layer GFL.

[0286] In another embodiment, such as Figure 15 As shown, all the intersecting portions between the first extension groove EXG1 and the second extension groove EXG2 may overlap with two or more exposed holes EXH.

[0287] In such an embodiment, the overlap area between the grid GRD and two or more exposed apertures EXH can be further increased, thereby further facilitating the emission of gases from the organic insulating material included in the grid filling layer GFL.

[0288] In the embodiments, as referred to above Figure 5 The described light-emitting pixel driver EPD includes first transistors T1 through seventh transistors T7, which are provided as P-type MOSFETs. However, this is merely an example, and some of the first transistors T1 through seventh transistors T7 may be provided as N-type MOSFETs. In another embodiment, for example, third transistor T3 and fourth transistor T4 may be provided as N-type MOSFETs.

[0289] Figure 16 This illustrates an embodiment. Figure 4 The equivalent circuit diagram of the light-emitting pixel driver.

[0290] Except for the third transistor T3 and the fourth transistor T4 among the first transistor T1 to the seventh transistor T7 of the light-emitting pixel driver EPD, which are provided as N-type MOSFETs, Figure 16 The display device 100 according to the embodiment (see Figure 1 )and Figure 5The embodiments are essentially the same. Therefore, any repeated detailed descriptions of elements that are the same or identical to those described above will be omitted.

[0291] According to the embodiments, such as Figure 16 As shown, the third transistor T3 can be electrically connected between the second node N2 and the third node N3. That is, the third transistor T3 can be electrically connected between the gate electrode of the first transistor T1 and the second electrode of the first transistor T1.

[0292] In such an embodiment, since the third transistor T3 is provided as an N-type MOSFET, the third transistor T3 can be turned on by the gate control signal GC of the gate control line GCL.

[0293] The voltage difference between the second node N2 and the third node N3 can be initialized by turning on the third transistor T3.

[0294] The fourth transistor T4 can be electrically connected between the gate initialization voltage line VGIL and the third node N3. That is, the fourth transistor T4 can be connected between the gate electrode of the first transistor T1 and the gate initialization voltage line VGIL.

[0295] The fourth transistor T4 can be turned on by the scan initialization signal GI of the scan initialization line GIL.

[0296] The potential of the third node N3 can be initialized by the conducting fourth transistor T4.

[0297] In such an embodiment, since the fourth transistor T4 is provided as an N-type MOSFET, the seventh transistor T7 can be turned on by the bias control signal GB of the bias control line GBL instead of the scan initialization signal GI of the scan initialization line GIL.

[0298] Figure 17 It is shown Figure 16 Cross-sectional view of the first transistor, second transistor, fourth transistor, sixth transistor and light-emitting element.

[0299] In addition to the additional semiconductor layer (channel portion CH4, first electrode portion E14 and second electrode portion E24) for providing the N-type MOSFET, the third gate conductive layer (gate electrode G4 of the fourth transistor T4), the additional interlayer insulating layer 128, and the third gate insulating layer 127, it also includes the following: Figure 17 The circuit layer 120 shown according to the embodiment and Figure 6 The circuit layer 120 shown according to the embodiment is substantially the same. Therefore, any repeated detailed descriptions of elements that are the same as or identical to those described above will be omitted.

[0300] According to the embodiments, such as Figure 17 As shown, the circuit layer 120 may include a substrate buffer layer 121 disposed on the substrate 110, a semiconductor layer (channel portion CH1, first electrode portion E11, second electrode portion E21, channel portion CH2, first electrode portion E12, second electrode portion E22, channel portion CH6, first electrode portion E16 and second electrode portion E26) disposed on the substrate buffer layer 121, a first gate insulating layer 122 covering the semiconductor layer, a first gate conductive layer (gate electrodes G1, G2 and G6) disposed on the first gate insulating layer 122, a second gate insulating layer 123 covering the first gate conductive layer, a second gate conductive layer (capacitor electrode CAE) disposed on the second gate insulating layer 123 and a second light blocking layer LB2, and an interlayer insulating layer 124 covering the second gate conductive layer (capacitor electrode CAE) and the second light blocking layer LB2.

[0301] According to the embodiments, such as Figure 17 As shown, the circuit layer 120 may further include an additional semiconductor layer (channel portion CH4, first electrode portion E14 and second electrode portion E24) disposed on the interlayer insulating layer 124, a third gate insulating layer 127 covering the additional semiconductor layer, a third gate conductive layer (gate electrode G4) disposed on the third gate insulating layer 127, and an additional interlayer insulating layer 128 covering the third gate conductive layer (gate electrode G4).

[0302] Circuit layer 120 may include a first source-drain conductive layer ANDE1 disposed on additional interlayer insulating layer 128 (see Figure 6 ), gate initialization voltage line VGIL and data connection electrode DCE, a first planarization layer 125 covering the first source-drain conductive layer ANDE1, and a second source-drain conductive layer ANDE2 disposed on the first planarization layer 125 (see Figure 6 ), and a second planarization layer 126 covering the second source-drain conductive layer ANDE2.

[0303] According to the embodiments, such as Figure 17 As shown, the circuit layer 120 may further include a barrier layer 129 disposed on the substrate 110 and a first light blocking layer LB1 disposed on the barrier layer 129 and covered by the substrate buffer layer 121.

[0304] The semiconductor layer on buffer layer 121 may include a first transistor T1, a second transistor T2, and a fifth transistor T5 provided as P-type MOSFETs (see [link]). Figure 16 ), sixth transistor T6 and seventh transistor T7 (see Figure 16The channel portions CH1, CH2 and CH6, the first electrode portions E11, E12 and E16, and the second electrode portions E21, E22 and E26.

[0305] The first gate conductive layer on the first gate insulating layer 122 may include a first transistor T1, a second transistor T2, and a fifth transistor T5 provided as P-type MOSFETs (see Figure 16 ), sixth transistor T6 and seventh transistor T7 (see Figure 16 The gate electrodes G1, G2 and G6 of ).

[0306] Since the fifth transistor T5 and the seventh transistor T7 have the same structure as the first transistor T1, the second transistor T2 and the sixth transistor T6, any repeated detailed descriptions of them will be omitted.

[0307] In each of the first transistor T1, the second transistor T2, and the sixth transistor T6, the channel portions CH1, CH2, and CH6 may overlap with the gate electrodes G1, G2, and G6.

[0308] The channel portion CH1 of the first transistor T1 can overlap with the first light-blocking layer LB1 below the buffer layer 121.

[0309] In each of the first transistor T1, the second transistor T2, and the sixth transistor T6, the first electrode portions E11, E12, and E16 may be connected to one end of the channel portions CH1, CH2, and CH6, and the second electrode portions E21, E22, and E26 may be connected to the other end of the channel portions CH1, CH2, and CH6.

[0310] The first electrode portion E11 of the first transistor T1 can be connected to the second electrode portion E22 of the second transistor T2.

[0311] The second electrode portion E21 of the first transistor T1 can be connected to the first electrode portion E16 of the sixth transistor T6.

[0312] The second gate conductive layer on the second gate insulating layer 123 may include a capacitor electrode CAE and a second light blocking layer LB2.

[0313] An additional semiconductor layer on the interlayer insulating layer 124 may include a third transistor T3 provided as an N-type MOSFET (see [link]). Figure 16 The channel portion CH4, the first electrode portion E14, and the second electrode portion E24 of each of the fourth transistor T4.

[0314] The third gate conductive layer on the third gate insulating layer 127 may include a third transistor T3 provided as an N-type MOSFET (see [link]). Figure 16 The gate electrode G4 of each of the fourth transistors T4 and T4.

[0315] In the third transistor T3 (see...) Figure 16 In each of the transistors 124 and 124, the channel portion CH4 may overlap with the second light-blocking layer LB2 beneath the interlayer insulating layer 124.

[0316] The channel portion CH4 of the fourth transistor T4 can overlap with the gate electrode G4 of the fourth transistor T4.

[0317] The first electrode portion E14 of the fourth transistor T4 can be connected to one end of the channel portion CH4 of the fourth transistor T4, and the second electrode portion E24 of the fourth transistor T4 can be connected to the other end of the channel portion CH4 of the fourth transistor T4.

[0318] Since the third transistor T3 and the fourth transistor T4 are provided as the same N-type MOSFET, any repeated detailed descriptions of them will be omitted.

[0319] The first source-drain conductive layer ANDE1 on the additional interlayer insulating layer 128 may include a first anode connection electrode ANCE1, a data connection electrode DCE, a gate initialization voltage line VGIL, and a node auxiliary connection electrode NACE.

[0320] The second source-drain conductive layer ANDE2 on the first planarization layer 125 may include a second anode connection electrode ANCE2 and a data line DL.

[0321] The data connection electrode DCE can be electrically connected to the first electrode portion E12 of the second transistor T2 through the first data connection hole DCH1.

[0322] The data cable DL can be electrically connected to the data connection electrode DCE through the second data connection hole DCH2.

[0323] Therefore, the data line DL can be electrically connected to the first electrode portion E12 of the second transistor T2 via the data connection electrode DCE.

[0324] The gate initialization voltage line VGIL can be electrically connected to the first electrode portion E14 of the fourth transistor T4 through the gate initialization voltage connection hole VGCH.

[0325] The node auxiliary connection electrode NACE can be electrically connected to the second electrode portion E24 of the fourth transistor T4 through the node auxiliary connection hole NACH.

[0326] Figure 17The component layer 130, encapsulation layer 140, touch sensor layer 150, and polarization layer 160 of the display device 100 according to the embodiment shown herein are... Figure 6 The component layer 130, encapsulation layer 140, touch sensor layer 150 and polarization layer 160 in the embodiments shown are substantially the same, and any repeated detailed descriptions of them will be omitted.

[0327] Figure 18 It is according to the embodiment along Figure 7 The cross-sectional view taken by line D-D'. Figure 19 It is according to the embodiment along Figure 7 A cross-sectional view taken from line E-E'.

[0328] In addition to circuit layer 120, it also includes an additional semiconductor layer on interlayer insulating layer 124, a third gate insulating layer 127 covering the additional semiconductor layer, a third gate conductive layer on the third gate insulating layer 127, and an additional interlayer insulating layer 128, and the gate GRD further exposes the third gate conductive layer on the third gate insulating layer 127. Figure 18 and Figure 19 The display device 100 shown according to an embodiment (see also...) Figure 1 )and Figures 1 to 15 The display device 100 shown according to the embodiment is substantially the same. Therefore, any repeated detailed descriptions of elements that are the same as or identical to those described above will be omitted.

[0329] According to the embodiments, such as Figure 18 and Figure 19 As shown, the gate GRD may be defined or formed as a portion passing through each of two or more insulating layers comprising inorganic insulating material (i.e., substrate buffer layer 121, first gate insulating layer 122, second gate insulating layer 123, interlayer insulating layer 124, third gate insulating layer 127, and additional interlayer insulating layer 128).

[0330] Therefore, the grid GRD can reach or expose a portion of each of the substrate 110, the first gate conductive layer on the first gate insulating layer 122, the second gate conductive layer on the second gate insulating layer 123, and the third gate conductive layer on the third gate insulating layer 127.

[0331] During the etching of two or more insulating layers (i.e., base buffer layer 121, first gate insulating layer 122, second gate insulating layer 123, interlayer insulating layer 124, third gate insulating layer 127, and additional interlayer insulating layer 128) to form a gate GRD, a portion of each of the base buffer layer 121, first gate insulating layer 122, second gate insulating layer 123, interlayer insulating layer 124, and third gate insulating layer 127 disposed below the third gate conductive layer may be retained due to the third gate conductive layer.

[0332] Therefore, a portion of the first gate conductive layer of the grid GRD that intersects can contact (or expose) the first gate conductive layer, another portion of the second gate conductive layer of the grid GRD that intersects can contact (or expose) the second gate conductive layer, yet another portion of the third gate conductive layer of the grid GRD that intersects can contact (or expose) the third gate conductive layer, and the remaining portion of the grid GRD can contact (or expose) the substrate 110.

[0333] In addition, a grid GRD can be formed on the light-emitting pixel driver EPD (see Figure 4 At least some of the boundaries between the multiple levels GIST, GWST and ECST are formed in the grid, and thus the grid GRD can be separated from the semiconductor layer used to provide transistors and additional semiconductor layers.

[0334] Furthermore, according to the embodiment, each of the scan write line GWL and the first gate extension line GEL1 may be disposed in one of the first gate conductive layer on the first gate insulating layer 122, the second gate conductive layer on the second gate insulating layer 123, and the third gate conductive layer on the third gate insulating layer 127, or defined by one of the first gate conductive layer on the first gate insulating layer 122, the second gate conductive layer on the second gate insulating layer 123, and the third gate conductive layer on the third gate insulating layer 127.

[0335] This invention should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art.

[0336] Although the present invention has been specifically shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit or scope of the present invention as defined by the appended claims.

Claims

1. A display device, characterized by comprising: The display device includes: The substrate includes a display area having multiple emission areas arranged therein and a non-display area disposed around the display area; A circuit layer is disposed on the substrate; and Component layer, disposed on the circuit layer, The element layer includes multiple light-emitting elements respectively disposed in the plurality of emission regions, and The circuit layer includes: Multiple light-emitting pixel drivers are electrically connected to the multiple light-emitting elements, respectively; Multiple gate lines transmit gate signals to the multiple light-emitting pixel drivers; A gate driving circuit is disposed in the gate driving region of the non-display area and includes multiple stages that are electrically connected to the multiple gate lines respectively; Two or more insulating layers are disposed on the substrate; A grid, defined by a plurality of grooves, the grid being defined in at least some of a plurality of boundaries between the plurality of light-emitting pixel drivers and in at least some of a plurality of boundaries between the plurality of levels passing through the two or more insulating layers; and A grid fill layer that fills the grid.

2. The display device according to claim 1, wherein The two or more insulating layers include: A base buffer layer is disposed on the base; A first gate insulating layer is disposed on the substrate buffer layer; A second gate insulating layer is disposed on the first gate insulating layer; and An interlayer insulating layer is disposed on the second gate insulating layer. The circuit layer further includes: A semiconductor layer is disposed between the substrate buffer layer and the first gate insulating layer; A first gate conductive layer is disposed between the first gate insulating layer and the second gate insulating layer; and A second gate conductive layer is disposed between the second gate insulating layer and the interlayer insulating layer. The grid exposes a portion of each of the substrate, the first gate conductive layer, and the second gate conductive layer, and in a plan view the grid is spaced apart from the semiconductor layer.

3. The display device according to claim 2, wherein The grid's plurality of grooves includes a plurality of first extended grooves and a plurality of second extended grooves intersecting the plurality of first extended grooves. In the extending direction of the plurality of second extending grooves, one or more of the plurality of light-emitting pixel drivers and one or more of the plurality of stages are disposed between two adjacent first extending grooves in the plurality of first extending grooves of the grid, and In the extending direction of the plurality of first extending grooves, one or more of the plurality of light-emitting pixel drivers are disposed in the plurality of second extending grooves of the grid between two adjacent second extending grooves in the display area.

4. The display device according to claim 3, wherein The plurality of gate lines include: The scan write line transmits scan write signals. Scan initialization line, transmit scan initialization signal; The transmit control line transmits transmit control signals; and Gate control line, transmits gate control signals. The plurality of stages of the gate drive circuit include: An initialization stage is arranged in the first circuit region of the gate driving region and is electrically connected to the scan initialization line and the gate control line; The write stage is disposed in the second circuit region of the gate drive region and electrically connected to the scan write line; and An emitter control stage is disposed in the third circuit region of the gate drive region and is electrically connected to the emitter control line. Wherein, at least one of the plurality of second extended grooves of the grid in the non-display area is disposed between the first circuit area, the second circuit area and the third circuit area.

5. The display device according to claim 4, wherein The non-display area also includes an extension line region disposed between the gate driving area and the display area. The circuit layer further includes gate extension lines disposed in the extension line region and electrically connected between the plurality of stages and the plurality of gate lines, and Two of the plurality of second extension grooves of the grid are respectively disposed on opposite sides of the extension line region.

6. The display device according to claim 4, wherein The circuit layer also includes: A first source-drain conductive layer is disposed on the interlayer insulating layer; A first planarization layer covers the first source-drain conductive layer and the grid. A second source-drain conductive layer is disposed on the first planarization layer; A second planarization layer covers the second source-drain conductive layer; and The supply line is located in the non-display area and surrounds three sides of the display area. The supply line is disposed in the second source-drain conductive layer, and In the plan view, a portion of the supply line overlaps with the gate drive region.

7. The display device according to claim 6, wherein Two or more exposed holes are defined to extend through the supply line and be spaced apart from each other in the plan view. The second planarization layer contacts the first planarization layer through the two or more exposed holes, and In the plan view, two or more of the intersecting portions between the plurality of first extended grooves and the plurality of second extended grooves overlap with the two or more exposed holes, respectively.

8. The display device according to claim 4, wherein One of the plurality of light-emitting pixel drivers electrically connected to a light-emitting element includes: The first transistor is electrically connected between the first node and the second node; The pixel capacitor is electrically connected between the first power line and the third node; The second transistor is electrically connected between the data line transmitting the data signal and the first node; The third transistor is electrically connected between the second node and the third node; The fourth transistor is electrically connected between the first initialization voltage line transmitting the first initialization voltage and the third node; The fifth transistor is electrically connected between the first power line and the first node; The sixth transistor is electrically connected between the second node and the fourth node; and The seventh transistor is electrically connected between the second initialization voltage line transmitting the second initialization voltage and the fourth node. The first node is electrically connected to the first electrode of the first transistor. The second node is electrically connected to the second electrode of the first transistor. The third node is electrically connected to the gate electrode of the first transistor. The fourth node is electrically connected to one of the light-emitting elements. Each of the second and third transistors is turned on by the scan write signal. The fourth transistor is turned on by the scan initialization signal. Each of the fifth and sixth transistors is turned on by the transmit control signal, and The seventh transistor is turned on by the gate control signal.

9. The display device according to claim 2, wherein The circuit layer also includes: An additional semiconductor layer is disposed on the interlayer insulating layer; A third gate insulating layer covers the additional semiconductor layer; A third gate conductive layer is disposed on the third gate insulating layer; and An additional interlayer insulating layer is added to cover the third gate conductive layer. The grid further exposes a portion of the third gate conductive layer.

10. The display device according to claim 1, characterized in that, The circuit layer further includes a grid buffer layer disposed between the grid and the grid fill layer.

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