Thinning and pressing circuit board structure
By forming alignment targets and thickness reduction grooves on the circuit board, and through fixing holes in the alignment area, and using pins for pressing, the problem of poor yield caused by excessive circuit board thickness is solved, and the circuit board structure is thinned and the yield is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- TRIPOD WUXI ELECTRONICS
- Filing Date
- 2025-07-31
- Publication Date
- 2026-05-29
AI Technical Summary
The existing circuit board structure suffers from poor yield due to the excessive thickness of the laminated circuit board.
By forming alignment targets and thickness reduction grooves on the circuit board, and through fixing holes in the alignment area, two circuit boards are pressed together using pins to form a thickness reduction and pressing circuit board structure.
It effectively reduces the thickness of the circuit board and improves the yield of the circuit board structure after lamination.
Smart Images
Figure CN224306004U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to a circuit board structure, and more particularly to a reduced-thickness laminated circuit board structure. Background Technology
[0002] In existing circuit board structures, the thickness of the laminated circuit board is too high, which easily leads to poor yield of the resulting circuit board structure. Utility Model Content
[0003] This utility model discloses a reduced-thickness lamination circuit board structure, which is mainly used to improve the problem that the existing circuit board structure is prone to poor yield due to the excessive thickness of the laminated circuit board.
[0004] One embodiment of this utility model discloses a thickness-reduced laminated circuit board structure, comprising: a first circuit board; wherein, a alignment target, a thickness-reducing groove, and a first fixing hole are formed on the surface of the first circuit board; wherein, the alignment target includes a plurality of alignment grooves and an alignment region surrounded by the alignment grooves, the thickness-reducing groove is formed in the alignment region, and the first fixing hole is formed in the alignment region and penetrates the bottom surface of the thickness-reducing groove; a second circuit board disposed on the first circuit board; wherein, the second circuit board includes a second fixing hole, and the second fixing hole corresponds in position to the first fixing hole; and a pin passing through the first fixing hole of the first circuit board and the second fixing hole of the second circuit board.
[0005] Optionally, the length of the thickness reduction groove is between 5.61 mm and 9.61 mm, and the width of the thickness reduction groove is between 3.26 mm and 7.26 mm.
[0006] Optionally, the thickness of one bottom of the thickness reduction groove is no more than 2 mm.
[0007] Optionally, the bottom thickness of the reducing groove is between 0.75 mm and 1.55 mm.
[0008] Optionally, the depth of the thickness reduction groove is not less than the bottom thickness.
[0009] Optionally, the alignment target is defined with a length direction and a width direction, and the multiple alignment slots of the alignment target are defined as a plurality of first alignment slots parallel to the length direction and a plurality of second alignment slots parallel to the width direction.
[0010] Optionally, the length of each first alignment groove is between 2.35 mm and 4.02 mm, and the length of each second alignment groove is between 2.98 mm and 6.66 mm.
[0011] Optionally, there is a distance between two adjacent first alignment slots, and the distance is between 0.82 mm and 1.4 mm.
[0012] Optionally, the number of first alignment grooves is four, and the number of second alignment grooves is two; wherein, the opening of the thickness reduction groove includes two long sides and two short sides, any two adjacent first alignment grooves are relative to the other two first alignment grooves and adjacent to one of the long sides, and one of the second alignment grooves is relative to the other second alignment groove and adjacent to one of the short sides.
[0013] Optionally, the second circuit board is another first circuit board, and the pin is two first fixing holes passing through the two first circuit boards.
[0014] In summary, one of the beneficial effects of this utility model is that the circuit board structure thickness reduction and lamination method provided by this utility model can effectively improve the problem of poor yield in the existing circuit board structure due to the excessive thickness of the laminated circuit board. This is achieved through the technical solutions of "the thickness reduction groove is formed in the alignment region, and the first fixing hole is formed in the alignment region and penetrates the bottom surface of the thickness reduction groove" and "a pin is inserted into the first fixing hole of the first circuit board and the second fixing hole of the second circuit board".
[0015] To further understand the features and technical content of this utility model, please refer to the following detailed description and drawings of this utility model. However, these descriptions and drawings are only used to illustrate this utility model and are not intended to limit the scope of protection of this utility model in any way. Attached Figure Description
[0016] Figure 1 This is a schematic diagram of the process of the circuit board structure thickness reduction and lamination method according to an embodiment of the present utility model.
[0017] Figure 2 This is a three-dimensional schematic diagram of the alignment target formation step in the circuit board structure thickness reduction and lamination method of this utility model embodiment.
[0018] Figure 3A This is a three-dimensional schematic diagram of the thickness reduction steps in the circuit board structure thickness reduction and lamination method of this utility model embodiment.
[0019] Figure 3B for Figure 3A Enlarged schematic diagram of region IIIB in the middle.
[0020] Figure 4 for Figure 3B Schematic diagram of cross section IV-IV along the center line.
[0021] Figure 5 This is a three-dimensional schematic diagram of the fixing hole formation step in the circuit board structure thickness reduction and lamination method of this utility model embodiment.
[0022] Figure 6 This is a cross-sectional schematic diagram of the fixing hole formation step in the circuit board structure thickness reduction and lamination method of this utility model embodiment.
[0023] Figure 7 This is a three-dimensional schematic diagram of the fixing hole formation step in the circuit board structure thickness reduction and lamination method of this utility model embodiment.
[0024] Figure 8 This is a schematic diagram of the circuit board structure according to an embodiment of the present invention.
[0025] Figure 9 for Figure 8 A cross-sectional view along section line IX-IX.
[0026] Figure 10 This is an exploded view of the reduced-thickness laminated circuit board structure according to an embodiment of the present invention.
[0027] Figure 11 This is an exploded view of a reduced-thickness laminated circuit board structure according to another embodiment of the present invention. Detailed Implementation
[0028] The following specific embodiments illustrate the implementation of the "thickness-reduced lamination circuit board structure" disclosed in this utility model. Those skilled in the art can understand the advantages and effects of this utility model from the content disclosed in this specification. This utility model can be implemented or applied through other different specific embodiments, and various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the concept of this utility model. Furthermore, the accompanying drawings of this utility model are for simple illustrative purposes only and are not depictions of actual dimensions, as stated in advance. The following embodiments will further describe the relevant technical content of this utility model in detail, but the disclosed content is not intended to limit the scope of protection of this utility model.
[0029] It should be understood that while terms such as "first," "second," and "third" may be used in this document to describe various components or signals, these components or signals should not be limited by these terms. These terms are primarily used to distinguish one component from another, or one signal from another. Furthermore, the term "or" as used herein should, as appropriate, include any combination of one or more of the associated listed items.
[0030] [Thickness Reduction Lamination Method for Circuit Board Structure]
[0031] Please see Figure 1 As shown, Figure 1 This is a schematic diagram illustrating the process of a circuit board structure thickness reduction and lamination method according to an embodiment of the present invention. The present invention provides a circuit board structure thickness reduction and lamination method. The circuit board structure thickness reduction and lamination method includes a target formation step S110, a thickness reduction step S120, a fixing hole formation step S130, and a lamination step S140. Of course, the circuit board structure thickness reduction and lamination method may include other steps as needed, and the present invention does not limit this.
[0032] Please see Figure 2 As shown, Figure 2 This is a perspective view of the alignment target formation step in the circuit board structure thickness reduction lamination method according to an embodiment of the present invention. In the alignment target formation step S110, an alignment target 11 is formed on a first circuit board 1. The alignment target 11 includes a plurality of alignment grooves 111 and an alignment region 112 surrounded by the alignment grooves 111. The alignment target 11 may be a non-central region formed on the surface of the first circuit board 1, but the present invention is not limited thereto. The plurality of alignment grooves 111 of the alignment target 11 may be formed by milling, but the present invention is not limited thereto.
[0033] Please see Figure 3A , Figure 3B and Figure 4 As shown, Figure 3A This is a three-dimensional schematic diagram of the thickness reduction steps in the circuit board structure thickness reduction lamination method according to an embodiment of the present invention. Figure 3B for Figure 3A An enlarged schematic diagram of region IIIB in the middle area, and Figure 4 for Figure 3B A cross-sectional view along section line IV-IV. In the thickness reduction step S120, a thickness reduction groove 12 is formed in the alignment region 112 on the first circuit board 1. The thickness reduction groove 12 can be a blind groove formed, for example, by blind tapping. Specifically, after the thickness reduction step S120, the bottom thickness T of the thickness reduction groove 12 is no greater than 2 mm, but the present invention is not limited thereto. It is worth mentioning that the bottom thickness T of the thickness reduction groove 12 can be regarded as the residual thickness of the first circuit board 1 in the alignment region 112 after the thickness reduction step S120. In other words, the thickness reduction groove 12 does not penetrate the first circuit board 1. Optionally, after the thickness reduction step S120, the bottom thickness T of the thickness reduction groove 12 is between 0.75 mm and 1.55 mm.
[0034] It is worth mentioning that if the thickness reduction step S120 is not performed, the thickness of the first circuit board 1 may be too thick, which would be detrimental to performing the lamination step S140 (e.g., by using a lamination device) or would leave room for improvement in yield after performing the lamination step S140. Through the thickness reduction step S120, the thickness of the first circuit board 1 in the alignment region 112 can be reduced, and the subsequent lamination step S140 can be performed more smoothly.
[0035] Furthermore, the length L1 of the thickness reduction groove 12 is between 5.61 mm and 9.61 mm, and the width W1 of the thickness reduction groove 12 is between 3.26 mm and 7.26 mm. However, this invention does not limit the length L1 and width W1 of the thickness reduction groove 12. Additionally, in this embodiment, the depth D of the thickness reduction groove 12 can be not less than the bottom thickness T. In other words, other thickness reduction steps that form a thickness reduction groove depth less than the thickness of the circuit board are not suitable for comparison with the thickness reduction step S120 in this embodiment.
[0036] More specifically, the alignment target 11 is defined by a length direction L and a width direction W, and the plurality of alignment grooves 111 of the alignment target 11 are defined as a plurality of first alignment grooves 111a parallel to the length direction L and a plurality of second alignment grooves 111b parallel to the width direction W. In this embodiment, the length direction L may be perpendicular to the width direction W, and the length direction L may be parallel to the connection between the alignment target 11 and the center of the first circuit board 1, but the present invention is not limited thereto.
[0037] In this embodiment, the length L2 of each of the first alignment grooves 111a is between 2.35 mm and 4.02 mm, and the length L3 of each of the second alignment grooves 111b is between 2.98 mm and 6.66 mm, but the present invention is not limited thereto.
[0038] Furthermore, in this embodiment, a distance G is spaced between two adjacent first alignment grooves 111a, and the distance is between 0.82 mm and 1.4 mm. The distance G between two adjacent first alignment grooves 111a effectively prevents adhesive from flowing into the thickness reduction groove 12 during the process, and also ensures sufficient structural strength at the position on the first circuit board 1 adjacent to the two first alignment grooves 111a.
[0039] In this embodiment, there are four first alignment grooves 111a and two second alignment grooves 111b. However, the present invention does not limit the number of the first alignment grooves 111a and the second alignment grooves 111b. Furthermore, the opening of the thickness reduction groove 12 includes two long sides 121 and two short sides 122. Any two adjacent first alignment grooves 111a are relative to the other two first alignment grooves 111a and adjacent to one of the long sides 121, and one of the second alignment grooves 111b is relative to the other second alignment groove 111b and adjacent to one of the short sides 122.
[0040] In other words, in this embodiment, two first alignment grooves 111a may be formed on each side of the thickness reduction groove 12, and one second alignment groove 111b may be formed on each of the other two sides of the thickness reduction groove 12. However, this utility model does not limit the arrangement of the first alignment grooves and the second alignment grooves.
[0041] Please see Figure 5 and Figure 6 As shown, Figure 5 This is a three-dimensional schematic diagram of the fixing hole formation step in the circuit board structure thickness reduction and lamination method according to an embodiment of the present invention. Figure 6 This is a cross-sectional view of the fixing hole forming step in the circuit board structure thickness reduction and lamination method according to an embodiment of the present invention. In the fixing hole forming step S130, a first fixing hole 13 is formed through the first circuit board 1 in the thickness reduction groove 12. Due to the alignment effect provided by the alignment groove 111, the first fixing hole 13 can be formed more accurately in the alignment region 112 in the fixing hole forming step S130.
[0042] Please see Figures 7 to 10 As shown, Figure 7 This is a three-dimensional schematic diagram of the fixing hole formation step in the circuit board structure thickness reduction and lamination method according to an embodiment of the present invention. Figure 8 This is a schematic diagram of the circuit board structure according to an embodiment of the present invention. Figure 9 for Figure 8 A cross-sectional view along section line IX-IX, and Figure 10 This is an exploded view of the reduced-thickness laminated circuit board structure according to an embodiment of this utility model. Figure 8 As shown, Figure 8This can also be seen as a three-dimensional schematic diagram of the pressing steps in the circuit board structure thickness reduction pressing method of this utility model embodiment. In the pressing step S140, a pin 3 is disposed in the first fixing hole 13 of the first circuit board 1 and the second fixing hole 21 of the second circuit board 2, and the first circuit board 1 and the second circuit board 2 are pressed together to form a thickness reduction pressing circuit board structure 100. In addition, the end of the pin 3 located on the first circuit board 1 may not have a gasket, thereby simplifying the process.
[0043] In other embodiments not shown in this utility model, a plurality of alignment targets 11, a plurality of first fixing holes 13 and a plurality of second fixing holes 21 may be formed, and a plurality of pins 3 may be disposed in the plurality of alignment targets 11, the plurality of first fixing holes 13 and the plurality of second fixing holes 21 to press the first circuit board 1 and the second circuit board 2 together.
[0044] Please see Figure 7 and Figure 11 As shown, Figure 7 This is a perspective view of the fixing hole forming step in the circuit board structure thickness reduction and lamination method according to another embodiment of the present invention. In another embodiment, before the lamination step S140, the alignment target forming step S110, the thickness reduction step S120, and the fixing hole forming step S130 are performed twice to obtain two first circuit boards 1. In the lamination step S140, the pins 3 are placed in the two first fixing holes 13 of the two first circuit boards 1 and the two first circuit boards 1 are pressed together to form the thickness reduction and lamination circuit board structure 100 (e.g., ...). Figure 11 (As shown). In other words, in this embodiment, one of the first circuit boards 1 replaces the second circuit board 2.
[0045] [Thickness Reduction Lamination Circuit Board Structure]
[0046] Please see Figures 7 to 10 As shown, Figure 7 This can also be considered a three-dimensional schematic diagram of the reduced-thickness laminated circuit board structure according to an embodiment of the present invention. The present invention also provides a reduced-thickness laminated circuit board structure 100. The reduced-thickness laminated circuit board structure 100 can be obtained by performing the aforementioned reduced-thickness laminated method for circuit board structures, but the present invention is not limited thereto. The reduced-thickness laminated circuit board structure 100 includes a first circuit board 1, a second circuit board 2, and a pin 3.
[0047] The surface of the first circuit board 1 has a pair of alignment targets 11, a thickness reduction groove 12, and a first fixing hole 13. The alignment target 11 includes a plurality of alignment grooves 111 and a pair of alignment regions 112 surrounded by the alignment grooves 111. In this embodiment, the number of alignment targets 11 is one, but the present invention does not limit the number of alignment targets 11. For example, in other embodiments not shown in the present invention, the number of alignment targets 11 can be multiple (e.g., four). The thickness reduction groove 12 is formed in the alignment region 112, and the first fixing hole 13 is formed in the alignment region 112 and penetrates the bottom of the thickness reduction groove 12. Furthermore, the number of thickness reduction grooves 12 and the number of first fixing holes 13 can correspond to the number of alignment targets 11.
[0048] The second circuit board 2 is disposed on the first circuit board 1. The second circuit board includes a second fixing hole 21, and the second fixing hole 21 corresponds in position to the first fixing hole 13. The pin 3 passes through the first fixing hole 13 of the first circuit board 1 and the second fixing hole 21 of the second circuit board 2.
[0049] In this embodiment, the length L1 of the thickness reduction groove 12 is between 5.61 mm and 9.61 mm, and the width W1 of the thickness reduction groove 12 is between 3.26 mm and 7.26 mm. Furthermore, in this embodiment, the bottom thickness T of the thickness reduction groove 12 is not greater than 2 mm. Optionally, the bottom thickness T of the thickness reduction groove 12 is between 0.75 mm and 1.55 mm. The depth of the thickness reduction groove 12 may be not less than the bottom thickness T.
[0050] The alignment target 11 is defined by a length direction L and a width direction W, and the plurality of alignment grooves 111 of the alignment target 11 are defined as a plurality of first alignment grooves 111a parallel to the length direction L and a plurality of second alignment grooves 111b parallel to the width direction W. The length L2 of each first alignment groove 111a is between 2.35 mm and 4.02 mm, and the length L3 of each second alignment groove 111b is between 2.98 mm and 6.66 mm. A distance G is spaced between two adjacent first alignment grooves 111a, and the distance G is between 0.82 mm and 1.4 mm.
[0051] In this embodiment, there are four first alignment grooves 111a and two second alignment grooves 111b. The opening of the thickness reduction groove 12 includes two long sides 121 and two short sides 122. Any two adjacent first alignment grooves 111a are relative to the other two first alignment grooves 111a and adjacent to one of the long sides 121, and one of the second alignment grooves 111b is relative to the other second alignment groove 111b and adjacent to one of the short sides 122.
[0052] Please see Figure 11 As shown, Figure 11 This is an exploded view of a reduced-thickness laminated circuit board structure according to another embodiment of the present invention. In another embodiment, the second circuit board 2 may be another first circuit board 1. In other words, the reduced-thickness laminated circuit board structure 100 in this embodiment includes two first circuit boards 1, and the pin 3 is a pin that passes through two first fixing holes 13 in the two first circuit boards 1.
[0053] [Beneficial Effects of the Embodiments of this Utility Model]
[0054] One of the beneficial effects of this utility model is that the circuit board structure thickness reduction and lamination method provided by this utility model can effectively improve the problem of poor yield in the existing circuit board structure due to the excessive thickness of the laminated circuit board. This is achieved through the technical solutions of "the thickness reduction groove is formed in the alignment region, and the first fixing hole is formed in the alignment region and penetrates the bottom surface of the thickness reduction groove" and "a pin is inserted into the first fixing hole of the first circuit board and the second fixing hole of the second circuit board".
[0055] The above description is only a preferred embodiment of the present utility model and does not limit the patent scope of the present utility model. Therefore, all equivalent technical changes made based on the contents of the present utility model specification and drawings are included within the protection scope of the present utility model.
Claims
1. A reduced-thickness laminated circuit board structure, characterized in that, The reduced-thickness laminated circuit board structure includes: A first circuit board; wherein, a pair of alignment targets, a thickness reduction groove and a first fixing hole are formed on the surface of the first circuit board; wherein, the alignment target includes a plurality of alignment grooves and a pair of alignment regions surrounded by the alignment grooves, the thickness reduction groove is formed in the alignment region, and the first fixing hole is formed in the alignment region and penetrates the bottom surface of the thickness reduction groove. A second circuit board is disposed on the first circuit board; wherein the second circuit board includes a second fixing hole, and the second fixing hole corresponds in position to the first fixing hole; and A pin is inserted into the first fixing hole of the first circuit board and the second fixing hole of the second circuit board.
2. The reduced-thickness laminated circuit board structure according to claim 1, characterized in that, The length of the thickness reduction groove is between 5.61 mm and 9.61 mm, and the width of the thickness reduction groove is between 3.26 mm and 7.26 mm.
3. The reduced-thickness laminated circuit board structure according to claim 1, characterized in that, The thickness of the bottom of the thickness reduction groove is no more than 2 mm.
4. The reduced-thickness laminated circuit board structure according to claim 3, characterized in that, The bottom thickness of the reduction groove is between 0.75 mm and 1.55 mm.
5. The reduced-thickness laminated circuit board structure according to claim 3, characterized in that, The depth of the thickness reduction groove is not less than the bottom thickness.
6. The reduced-thickness laminated circuit board structure according to claim 1, characterized in that, The alignment target is defined with a length direction and a width direction, and the plurality of alignment slots of the alignment target are defined as a plurality of first alignment slots parallel to the length direction and a plurality of second alignment slots parallel to the width direction.
7. The reduced-thickness laminated circuit board structure according to claim 6, characterized in that, The length of each of the first alignment grooves is between 2.35 mm and 4.02 mm, and the length of each of the second alignment grooves is between 2.98 mm and 6.66 mm.
8. The reduced-thickness laminated circuit board structure according to claim 6, characterized in that, There is a distance between two adjacent first alignment slots, and the distance is between 0.82 mm and 1.4 mm.
9. The reduced-thickness laminated circuit board structure according to claim 6, characterized in that, The number of first alignment grooves is four, and the number of second alignment grooves is two; wherein, the opening of the thickness reduction groove includes two long sides and two short sides, any two adjacent first alignment grooves are relative to the other two first alignment grooves and adjacent to one of the long sides, and one of the second alignment grooves is relative to the other second alignment groove and adjacent to one of the short sides.
10. The reduced-thickness laminated circuit board structure according to claim 1, characterized in that, The second circuit board is another first circuit board, and the pin is the first fixing hole that passes through the two first circuit boards.