A silicon carbide vdmos device shallow trench isolation termination structure
By employing a shallow trench insulating termination structure in silicon carbide VDMOS devices and utilizing a double-layer design where the insulating dielectric region encloses the P+ well region, the breakdown problem caused by the concentration of electric field at the device edge is solved, thereby improving the high withstand voltage capability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- GLOBAL POWER TECH CO LTD
- Filing Date
- 2025-04-24
- Publication Date
- 2026-05-29
AI Technical Summary
Traditional silicon carbide VDMOS devices have a high risk of breakdown due to the concentration of electric field at the edge, and require sacrificing area to achieve the withstand voltage, making it difficult to improve the terminal withstand voltage without increasing the width.
By employing a shallow trench insulating terminal structure, and by setting an insulating dielectric region wrapped by the first and second P+ doped regions next to the P+ well region, a double-layer cutoff and gradual suppression of the electric field are achieved.
Without increasing the device width, the voltage withstand capability of the terminal is improved, meeting the device requirements up to 1200V and reducing the risk of breakdown.
Smart Images
Figure CN224306198U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to a shallow trench insulating termination structure for a silicon carbide VDMOS device. Background Technology
[0002] Silicon carbide VDMOS is a typical example of silicon carbide power devices, widely used in electric vehicles, aerospace, and power conversion. Based on the device structure design, the edges of repeating cells experience electric field concentration due to the lateral distribution of the electric field, leading to breakdown at the device edges. Traditional cells use field-limiting ring structures with the same doping concentration to suppress this electric field concentration. However, because the doping concentration and spacing of the field-limiting rings are equal, the electric field strength gradually decreases, and there are still differences in the electric field distribution. The risk of breakdown remains high near the P+ well region, and a large number of field-limiting rings are needed to achieve the breakdown voltage at the device terminals, sacrificing area for voltage withstand capability. Utility Model Content
[0003] The technical problem to be solved by this utility model is to provide a shallow trench insulated termination structure for silicon carbide VDMOS devices. By using shallow trench insulated termination, the problem of high manufacturing difficulty in deep trench termination is avoided. At the same time, the termination withstand voltage within 1200V is achieved, and the withstand voltage capability of the average unit width of the termination is improved. That is, while ensuring the withstand voltage capability of the termination, the width of the termination structure is saved.
[0004] In a first aspect, this utility model provides a shallow trench insulating termination structure for a silicon carbide VDMOS device, comprising:
[0005] silicon carbide substrate,
[0006] A drift layer is provided, the lower side of which is connected to the upper side of the silicon carbide substrate; the drift layer is provided with a P+ well region, a first insulating dielectric region, a first P+ doped region, and a stop ring contact region; one side of the P+ well region is connected to one side of the first insulating dielectric region, the lower side of the P+ well region is connected to the first P+ doped region, the first insulating dielectric region is disposed within the first P+ doped region, and the stop ring contact region is located on one side of the first P+ doped region.
[0007] An insulating layer, the lower side of which is connected to the upper side of the first insulating dielectric region, the upper side of the first P+ doped region, and the upper side of the drift layer;
[0008] A stop ring metal layer, the lower side of which is connected to the upper side of the stop ring contact area.
[0009] The advantages of this utility model are:
[0010] I. This utility model effectively cuts off the electric field at the edge of the P+ well region by setting a first insulating dielectric region wrapped by a first P+ doped region in the terminal structure next to the P+ well region of the device; thereby suppressing the electric field intensity in the terminal region.
[0011] Second, this utility model is provided with a second insulating dielectric region wrapped by a second P+ doped region to achieve secondary cutoff and slow change suppression of strong electric fields. This double-layer structure can meet the device requirements within 1200V. Attached Figure Description
[0012] The present invention will be further described below with reference to the accompanying drawings and embodiments.
[0013] Figure 1 This is a schematic diagram of a shallow trench insulating termination structure for a silicon carbide VDMOS device according to the present invention.
[0014] Figure 2 This is a cross-sectional view of the process of a shallow trench insulating termination structure for a silicon carbide VDMOS device according to this utility model. Figure 1 .
[0015] Figure 3 This is a cross-sectional view of the process of a shallow trench insulating termination structure for a silicon carbide VDMOS device according to this utility model. Figure 2 .
[0016] Figure 4 This is a cross-sectional view of the process of a shallow trench insulating termination structure for a silicon carbide VDMOS device according to this utility model. Figure 3 .
[0017] Figure 5 This is a cross-sectional view of the process of a shallow trench insulating termination structure for a silicon carbide VDMOS device according to this utility model. Figure 4 .
[0018] Figure 6 This is a cross-sectional view of the process of a shallow trench insulating termination structure for a silicon carbide VDMOS device according to this utility model. Figure 5 .
[0019] Figure 7 This is a cross-sectional view of the process of a shallow trench insulating termination structure for a silicon carbide VDMOS device according to this utility model. Figure 6 .
[0020] Figure 8 This is a cross-sectional view of the process of a shallow trench insulating termination structure for a silicon carbide VDMOS device according to this utility model. Figure 7 .
[0021] Figure 9 This is a cross-sectional view of the process of a shallow trench insulating termination structure for a silicon carbide VDMOS device according to this utility model. Figure 8 .
[0022] Figure 10 This is a cross-sectional view of the process of a shallow trench insulating termination structure for a silicon carbide VDMOS device according to this utility model. Figure 9 .
[0023] Figure 11 This is a cross-sectional view of the process of a shallow trench insulating termination structure for a silicon carbide VDMOS device according to this utility model. Figure 10 .
[0024] Figure 12 This is a cross-sectional view of the process of a shallow trench insulating termination structure for a silicon carbide VDMOS device according to this utility model. Figure 10 one.
[0025] Figure 13 This is a cross-sectional view of the process of a shallow trench insulating termination structure for a silicon carbide VDMOS device according to this utility model. Figure 10 two. Detailed Implementation
[0026] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0028] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "in contact with," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this utility model, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion.
[0029] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figures and other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as “below,” “under,” or “below” other elements or features would be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein are interpreted accordingly.
[0030] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.
[0031] like Figure 1 As shown, this application embodiment provides a shallow trench insulating termination structure for a silicon carbide VDMOS device, including:
[0032] Silicon carbide substrate 1,
[0033] A drift layer 2 is provided, the lower side of which is connected to the upper side of the silicon carbide substrate 1; the drift layer 2 is provided with a P+ well region 21, a first insulating dielectric region 22, a first P+ doped region 23 and a stop ring contact region 24; one side of the P+ well region 21 is connected to one side of the first insulating dielectric region 22, the lower side of the P+ well region 21 is connected to the first P+ doped region 23, the first insulating dielectric region 22 is disposed in the first P+ doped region 23, and the stop ring contact region 24 is located on one side of the first P+ doped region 23.
[0034] Insulating layer 3, the lower side of which is connected to the upper side of the first insulating dielectric region 22, the upper side of the first P+ doped region 23, and the upper side of the drift layer 2;
[0035] A stop ring metal layer 4, the lower side of which is connected to the upper side of the stop ring contact area 24;
[0036] Source metal layer 5, the lower side of which is connected to P+ well region 21;
[0037] Drain metal layer 6, which is connected to the lower side of silicon carbide substrate 1.
[0038] In this embodiment, preferably, at least one field limiting ring 25 is provided in the drift layer 2, and each field limiting ring 25 includes a second insulating dielectric region 251 and a second P+ doped region 252. The second insulating dielectric region 251 is disposed in the second P+ doped region 252, and the second P+ doped region 252 is located between the first P+ doped region 23 and the stop ring contact region 24. The lower side of the insulating layer 3 is connected to the upper side of the second insulating dielectric region 251 and the upper side of the second P+ doped region 252.
[0039] In this embodiment, preferably, the depth of the first insulating dielectric region 22 is less than the depth of the second insulating dielectric region 251; and the depth of the first P+ doped region 23 is less than the depth of the second P+ doped region 252.
[0040] In this embodiment, preferably, the width of the second P+ doped region 252 located to the left of the second insulating dielectric region 251 is smaller than the width of the second P+ doped region 252 located to the right of the second insulating dielectric region 251.
[0041] In this embodiment, preferably, the width of the first P+ doped region 23 located to the left of the first insulating dielectric region 22 is smaller than the width of the first P+ doped region 23 located to the right of the first insulating dielectric region 22.
[0042] like Figures 1 to 13 As shown, the method for preparing the above-mentioned terminal structure includes the following steps:
[0043] Step 1: Epitaxial growth is performed on silicon carbide substrate 1 to form drift layer 2;
[0044] Step 2: Form a barrier layer 7 above the drift layer 2, etch the barrier layer 7 to form a via, and implant ions to form the first left P+ doped region 231;
[0045] Step 3: Remove the barrier layer 7, reform the barrier layer 7 above the N-type drift layer 2, etch the barrier layer 7 to form a via, and implant ions to form the second left P+ doped region 2521.
[0046] Step 4: Remove the barrier layer 7, reform the barrier layer 7, etch the barrier layer 7 to form a via, and implant ions to form the P+ well region 21 and the stop ring contact region 24.
[0047] Step 5: Remove the barrier layer 7, reform the barrier layer 7, etch the barrier layer 7 to form vias, deposit highly p-type doped silicon carbide material, and form a second right P+ doped region 2522 through thermal diffusion. The second P+ doped region 252 includes a second left P+ doped region 2521 and a second right P+ doped region 2522. Since thermal diffusion requires a concentration gradient, it will not affect the doping concentration of the second left P+ doped region 2521 formed in the previous process steps.
[0048] Step 6: Remove the barrier layer 7, reform the barrier layer 7, etch the barrier layer 7 to form a via, deposit highly P-type doped silicon carbide material, and form a first right P+ doped region 232 through thermal diffusion. The first P+ doped region 23 includes a first left P+ doped region 231 and a first right P+ doped region 232.
[0049] Step 7: Remove the barrier layer 7, reform the barrier layer 7, etch the barrier layer 7 to form a via, etch the second P+ doped region 252 to form the second trench 2523, and deposit to form the second insulating dielectric region 251.
[0050] Step 8: Remove the barrier layer 7, reform the barrier layer 7, etch the barrier layer 7 to form a via, etch the first P+ doped region 23 to form the first trench 233, and deposit to form the first insulating dielectric region 22.
[0051] Step 9: Remove the barrier layer 7, reform the barrier layer 7, etch the barrier layer 7 to form a via, deposit metal to form the source metal layer 5 and the stop ring metal layer 4.
[0052] Step 10: Remove barrier layer 7, reform barrier layer 7, etch barrier layer 7 to form vias, deposit insulating layer 3, and remove barrier layer 7.
[0053] In another embodiment of this invention, the termination structure is applied to the termination of a planar gate silicon carbide VDMOS device. The description uses a single-sided termination structure as an example; the termination structure on the other side is a mirror image of the structure in this embodiment. The doping concentration of the N-type silicon carbide substrate 1 is 2-8e18cm⁻¹. -3 The doping concentration of the N-type drift layer 2 is 5-9e16cm. -3 The doping concentration of both the first P+ doped region 23 and the second P+ doped region 252 is 1-5e18cm. -3 The doping concentration of P+ well region 21 is 5-8e18cm. -3 The doping concentration of the stop ring contact region 24 is 5-8e18cm. -3 The insulating layer 3 can be made of silicon dioxide, and the first insulating dielectric region 22 and the second insulating dielectric region 251 can be made of either SiN or diamond.
[0054] The doping concentrations of the N-type silicon carbide substrate 1, the N-type drift layer 2, and the P+ well region 21 are considered in the traditional design structure of planar gate silicon carbide VDMOS devices. The doping concentrations of the first P+ doped region 23 and the second P+ doped region 252 are to diffuse the electric field distribution of the P+ well region 21 downwards after the first insulating dielectric region 22 and the second insulating dielectric region 251 laterally share the main electric field, thereby reducing the electric field strength and improving the reliability of the device.
[0055] In the terminal structure, the width d1 of the first P+ doped region 23 located to the right of the first insulating dielectric region 22 is 1 μm, and the width w of the first insulating dielectric region 22 is 1 μm; the width w1 of the first P+ doped region 23 located to the left of the first insulating dielectric region 22 is 300 nm, and the maximum depth of the first P+ doped region 23 is 1.3 μm; in the terminal structure, the width d2 of the second P+ doped region 252 located to the right of the second insulating dielectric region 251 is 1.5 μm, and the width w of the second insulating dielectric region 251 is 1 μm; the width w2 of the second P+ doped region 252 located to the left of the second insulating dielectric region 251 is 200 nm, and the maximum depth of the second P+ doped region 252 is 1.7 μm; the minimum distance between the first insulating dielectric region 22 and the second insulating dielectric region 251 is 2 μm; the thickness of the insulating layer 3, the source metal layer 5, and the stop ring metal layer 4 is all 300 nm. The thickness of the insulating layer 3 is to ensure that after the electric field is applied, the device's top interconnect structure is not affected during the breakdown voltage test;
[0056] By setting a first insulating dielectric region 22 wrapped by a first P+ doped region 23 in the terminal structure next to the P+ well region 21 of the device, the electric field at the edge of the P+ well region 21 is effectively cut off, thereby suppressing the electric field strength in the terminal region. A second insulating dielectric region 251 wrapped by a second P+ doped region 252 is set to achieve secondary cutoff and gradual suppression of strong electric fields. This double-layer structure can meet the device requirements within 1200V.
[0057] The device termination structure is expandable. When the device withstands higher voltage, more structures can be designed according to the electric field distribution. However, the termination structure parameters need to be optimized according to the electric field distribution.
[0058] While specific embodiments of the present invention have been described above, those skilled in the art should understand that the specific embodiments described are merely illustrative and not intended to limit the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should be covered within the scope of protection of the claims of the present invention.
Claims
1. A shallow trench insulating termination structure for a silicon carbide VDMOS device, characterized in that: include: silicon carbide substrate, A drift layer, wherein the lower side of the drift layer is connected to the upper side of the silicon carbide substrate; The drift layer is provided with a P+ well region, a first insulating dielectric region, a first P+ doped region, and a stop ring contact region; One side of the P+ well region is connected to one side of the first insulating dielectric region, the lower side of the P+ well region is connected to the first P+ doped region, the first insulating dielectric region is disposed within the first P+ doped region, and the cut-off ring contact region is located on one side of the first P+ doped region. An insulating layer, the lower side of which is connected to the upper side of the first insulating dielectric region, the upper side of the first P+ doped region, and the upper side of the drift layer; A stop ring metal layer, the lower side of which is connected to the upper side of the stop ring contact area.
2. The shallow trench insulating termination structure for a silicon carbide VDMOS device as described in claim 1, characterized in that: The drift layer is provided with at least one field limiting ring, each field limiting ring including a second insulating dielectric region and a second P+ doped region, the second insulating dielectric region being disposed within the second P+ doped region, the second P+ doped region being located between the first P+ doped region and the stop ring contact region; the lower side of the insulating layer is connected to the upper side of the second insulating dielectric region and the upper side of the second P+ doped region.
3. The shallow trench insulating termination structure for a silicon carbide VDMOS device as described in claim 2, characterized in that: The depth of the first insulating dielectric region is less than the depth of the second insulating dielectric region; the depth of the first P+ doped region is less than the depth of the second P+ doped region.
4. The shallow trench insulating termination structure for a silicon carbide VDMOS device as described in claim 2, characterized in that: The width of the second P+ doped region located to the left of the second insulating dielectric region is smaller than the width of the second P+ doped region located to the right of the second insulating dielectric region.
5. The shallow trench insulating termination structure for a silicon carbide VDMOS device as described in claim 1, characterized in that: The width of the first P+ doped region located to the left of the first insulating dielectric region is smaller than the width of the first P+ doped region located to the right of the first insulating dielectric region.