Chip structure, package structure, circuit board assembly and electronic device

Abstract

The present disclosure relates to a chip structure, a packaging structure, a circuit board assembly and an electronic device. The chip structure comprises a chip, a capacitor layer and an electrical connector. The chip comprises a first surface and a second surface facing away from each other. The capacitor layer is connected to the second surface of the chip, and the capacitor layer is provided with a capacitor. The electrical connector is arranged on the capacitor layer. The first end of the electrical connector is electrically connected to the chip, and the second end of the electrical connector is exposed on the surface of the capacitor layer away from the chip. The capacitor layer and the electrical connector make the arrangement of the capacitor no longer limited by space, and can shorten the distance between the capacitor and the chip, provide higher capacitor arrangement density for the chip, improve the signal quality of the power signal of the chip, and thus improve the overall performance of the chip structure.

Description

Technical Field

[0001] This disclosure relates to the field of chip packaging, specifically a chip structure, packaging structure, circuit board assembly, and electronic device. Background Technology

[0002] In recent years, with the rapid development of chip technology, various types of chips, such as System-on-Chips (SOCs), have been widely used in many electronic devices. The power supply signal of a chip is a key factor in ensuring its normal operation, and the signal quality of the power supply signal affects multiple aspects of the chip, including performance, stability, and power consumption. Utility Model Content

[0003] To overcome the problems existing in the related technologies, this disclosure provides a chip structure, a packaging structure, a circuit board assembly, and an electronic device.

[0004] According to a first aspect of the present disclosure, a chip structure is provided, the chip structure comprising:

[0005] A chip, the chip including a first surface and a second surface that are opposite to each other;

[0006] A capacitor layer is connected to the second surface of the chip, and a capacitor is disposed in the capacitor layer;

[0007] An electrical connector is disposed on the capacitor layer. The first end of the electrical connector is electrically connected to the chip, and the second end of the electrical connector is exposed away from the surface of the chip through the capacitor layer.

[0008] In this embodiment, a capacitor is disposed within the capacitor layer, and the capacitor layer is connected to the second surface of the chip, achieving capacitor placement in close proximity to the chip. An electrical connector is disposed within the capacitor layer, with its first end electrically connected to the chip and its second end exposed away from the chip surface through the capacitor layer, enabling signal extraction from the chip for subsequent chip packaging. The capacitor layer and electrical connector remove spatial limitations on capacitor placement and shorten the distance between the capacitor and the chip, providing a higher capacitor density. The capacitor's characteristics of reducing impedance, suppressing noise, providing transient response support, and improving signal integrity enhance the signal quality of the chip's power supply signals, thereby improving the overall performance of the chip structure.

[0009] In some embodiments of this disclosure, the capacitor is electrically connected to the electrical connector.

[0010] In this embodiment, the capacitor is electrically connected to an electrical connector. The electrical connector enables the capacitor to be electrically connected to the chip and to external circuits or devices, thereby connecting the capacitor to the signal transmission path between external circuits or devices. This facilitates the realization of the capacitor's function and helps to further improve the signal quality of the chip's power signal.

[0011] In some embodiments of this disclosure, the capacitor includes a deep trench capacitor, wherein the trench of the deep trench capacitor is formed on the surface of the capacitor layer facing the chip.

[0012] In this embodiment, a deep trench capacitor is used as the capacitor in the capacitor layer. The characteristics of the deep trench capacitor are used to improve the performance of the capacitor and ensure the density of the capacitor arrangement. The trenches of the deep trench capacitor are opened on the surface of the capacitor layer facing the chip, which further shortens the distance between the capacitor and the chip, thereby further improving the signal quality of the chip's power signal.

[0013] In some embodiments of this disclosure, the thickness of the capacitor layer is 15–20 μm, and the trench depth of the deep trench capacitor is 8–12 μm.

[0014] In this embodiment, the thickness of the capacitor layer is set to 15-20 μm, and the trench depth of the deep trench capacitor is set to 8-12 μm. By controlling the thickness and depth, as well as the ratio between the two, the capacitor arrangement density is improved, the electrical performance of the capacitor is improved, and the implementation of process steps is facilitated, thereby further enhancing the overall performance of the chip structure.

[0015] In some embodiments of this disclosure, multiple capacitors and electrical connectors are provided, and the projection of each electrical connector on the first surface is located between the projections of adjacent capacitors on the first surface.

[0016] In this embodiment, multiple capacitors and electrical connectors are provided to ensure the density of capacitor arrangement and the interconnection density between the chip and external circuits or devices. Each electrical connector is configured such that its projection on the first surface is located between the projections of adjacent capacitors on the first surface, so that the electrical connectors and capacitors can be arranged at intervals in this direction. This improves the uniformity of capacitor and electrical connector arrangement, ensures the space utilization of the capacitor layer, and is beneficial to improving the electrical performance, heat dissipation effect, process convenience and structural reliability of the chip structure.

[0017] In some embodiments of this disclosure, the chip includes a processor region and a non-processor region, and the capacitor layer includes a first region and a second region. In a direction perpendicular to the chip, the processor region corresponds to the first region, and the non-processor region corresponds to the second region.

[0018] The capacitors are provided in multiple ways, and the arrangement density of the capacitors in the first region is greater than the arrangement density of the capacitors in the second region.

[0019] In this embodiment, multiple capacitors are provided, and the arrangement density of capacitors in the first region is greater than that in the second region. This provides a higher capacitor density for the processor region corresponding to the chip in the first region, prioritizing the improvement of the power signal quality of the processor region to support the complex functions and high-power operation of the processor region, thereby improving the overall performance of the chip structure.

[0020] In some embodiments of this disclosure, the chip structure further includes:

[0021] A connection layer that connects the second surface of the chip to the capacitor layer.

[0022] In this embodiment, the chip structure is provided with a connection layer, which can connect the second surface of the chip to the capacitor layer, ensuring the connection strength between the chip and the capacitor layer. Furthermore, the connection layer can improve the heat dissipation and electrical performance between the chip and the capacitor layer, which is beneficial to improving the overall performance and structural stability of the chip structure.

[0023] In some embodiments of this disclosure, the connection layer includes a hybrid bonding layer.

[0024] In this embodiment, the hybrid bonding layer fabricated by the hybrid bonding process is used as the connection layer. The stable connection between the chip and the capacitor layer is achieved through the hybrid bonding layer, so that the chip, the connection layer and the capacitor layer are tightly attached. It has the characteristics of high integration density, excellent electrical and thermal performance, and reduced stress damage, which is beneficial to improving the overall performance and structural stability of the chip structure.

[0025] In some embodiments of this disclosure, the hybrid bonding layer includes a metal pad, one side of which is electrically connected to the chip, and the other side of which is electrically connected to the electrical connector.

[0026] In this embodiment, one end of the metal pad in the hybrid bonding layer is electrically connected to the chip, and the other side of the metal pad is electrically connected to the electrical connector. The metal pad enables the electrical connection between the chip and the electrical connector, which facilitates the signal output of the chip and ensures the stability of the electrical connection between the chip and the electrical connector, thereby improving the overall performance of the chip structure.

[0027] In some embodiments, the capacitor is electrically connected to the chip via a connection layer.

[0028] In some embodiments of this disclosure, the capacitor is electrically connected to the chip through the connection layer.

[0029] In this embodiment, the capacitor is electrically connected to the chip through a connection layer. The connection layer enables the electrical connection between the capacitor and the chip, thereby facilitating the realization of the capacitor's function and helping to further improve the signal quality of the chip's power supply signal.

[0030] In some embodiments of this disclosure, the electrical connector includes a first connection portion and a second connection portion. The first connection portion penetrates the capacitor layer, and the second connection portion is disposed on the surface of the capacitor layer opposite to the chip. The first connection portion is used to electrically connect the chip and the second connection portion.

[0031] In this embodiment, the capacitor is electrically connected to the chip through a connection layer. The connection layer enables the electrical connection between the capacitor and the chip, thereby facilitating the realization of the capacitor's function and helping to further improve the signal quality of the chip's power supply signal.

[0032] In some embodiments of this disclosure, the first connection portion includes a through-silicon via (TSV), and the second connection portion includes a metal bump.

[0033] In this embodiment, a through-silicon via (TSV) is used as the first connection part, and a metal bump is used as the second connection part. The electrical connection between the chip and external circuits or devices is achieved through the electrical connector formed by the TSV and the metal bump. This allows the electrical connector to have the characteristics of both TSV and metal bump, ensuring the rationality of the structure and the stability of the electrical connection, and further improving the overall performance of the chip structure.

[0034] In some embodiments of this disclosure, the capacitor layer comprises a silicon wafer layer.

[0035] In this embodiment, the silicon wafer layer is selected as the capacitor layer. The stable physical and chemical properties and excellent electrical performance of the silicon wafer layer can be utilized, which has a high degree of compatibility with the capacitor setting. This is beneficial to improving the performance, integration and frequency characteristics of the capacitor, thereby improving the overall performance of the chip structure.

[0036] In some embodiments of this disclosure, the chip includes any one of a logic chip, a system-on-a-chip, or a memory chip.

[0037] In this embodiment, logic chips, memory chips, or system-on-a-chips are used as chips in the chip structure. The capacitors are arranged and the signals of the chips are brought out through capacitor layers and electrical connections. This can improve the signal quality of the power signals of logic chips, memory chips, or system-on-a-chips, so as to meet the high requirements of logic chips, memory chips, and system-on-a-chips for the signal quality of power signals, and improve the performance of logic chips, memory chips, or system-on-a-chips.

[0038] According to a second aspect of the present disclosure, a packaging structure is provided, the packaging structure including the chip structure as described in the first aspect, the packaging structure further including a packaging substrate, and a second end of the electrical connector being electrically connected to the packaging substrate.

[0039] In this embodiment, the chip structure included in the packaging structure has the advantage of improving the signal quality of the chip's power signal, so that the packaging structure and the chip structure it includes have the same advantages.

[0040] According to a third aspect of the present disclosure, a circuit board assembly is provided, the circuit board assembly further comprising a circuit board electrically connected to the packaging substrate of the packaging structure.

[0041] In this embodiment, the packaging structure included in the circuit board assembly has the advantage of improving the signal quality of the power supply signal of the chip, so that the circuit board assembly and its included packaging structure have the same advantages.

[0042] According to a fourth aspect of the present disclosure, an electronic device is provided, the electronic device including a chip structure as described in the first aspect, or the electronic device including a packaging structure as described in the second aspect, or the electronic device including a circuit board assembly as described in the third aspect.

[0043] In this embodiment, the chip structure, packaging structure, or circuit board assembly included in the electronic device all have the advantage of improving the signal quality of the chip's power signal, thus giving the electronic device the same advantage.

[0044] The technical solutions provided by the embodiments of this disclosure may include the following beneficial effects: the capacitor layer and electrical connectors make the placement of capacitors no longer limited by space, and can shorten the distance between capacitors and chips, providing higher capacitor placement density for chips, improving the signal quality of power signals of chips, thereby improving the overall performance of chip structure.

[0045] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0046] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0047] Figure 1 This is a schematic diagram of a circuit board assembly.

[0048] Figure 2 This is a schematic diagram of a chip structure according to an exemplary embodiment.

[0049] Figure 3 This is a schematic diagram of the packaging structure according to an exemplary embodiment.

[0050] Figure 4 This is a schematic diagram of the structure of a circuit board assembly according to an exemplary embodiment.

[0051] In the picture:

[0052] 10-Chip; 20-Capacitor layer; 21-Capacitor; 30-Electrical connector; 31-First connector; 32-Second connector; 40-Connector layer; 41-Metal pad; 50-Packaging substrate; 60-Circuit board. Detailed Implementation

[0053] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0054] In one exemplary embodiment, a chip structure is provided, which can, for example, form a package structure with a packaging substrate and be embedded in an electronic device such as a mobile phone, tablet computer, or smart band.

[0055] In one embodiment, reference Figure 1 As shown, this embodiment provides a circuit board assembly, which includes a chip 10, a packaging substrate 50, and a circuit board 60. Since the capacitor 21 has the characteristics of reducing impedance, suppressing noise, providing transient response support, and improving signal integrity, the capacitor 21 can be disposed on the surface of the packaging substrate 50 facing the circuit board 60 to form a back-mounted capacitor of the packaging substrate 50. Alternatively, the capacitor 21 can be disposed on both sides of the circuit board 60 to form a front-mounted capacitor or a back-mounted capacitor of the circuit board 60.

[0056] Using the above-mentioned circuit board assembly, the chip 10 and the packaging substrate 50 need to be electrically connected through bumps, which restricts the space between the chip 10 and the packaging substrate 50. It is difficult to place the capacitor 21 between the chip 10 and the packaging substrate 50. The distance between the capacitor 21 and the chip 10 is too far, and the arrangement density of the capacitor 21 is difficult to meet the requirements, resulting in poor signal quality of the power signal of the chip 10 and a decrease in the performance of the chip 10.

[0057] In another embodiment, reference Figure 2As shown, the chip structure includes a chip 10, a capacitor layer 20, and an electrical connector 30. The chip 10 includes a first surface and a second surface that are opposite to each other. The capacitor layer 20 is connected to the second surface of the chip 10, and a capacitor 21 is disposed in the capacitor layer 20. The electrical connector 30 is disposed on the capacitor layer 20. The first end of the electrical connector 30 is electrically connected to the chip 10, and the second end of the electrical connector 30 is exposed through the capacitor layer 20 away from the surface of the chip 10.

[0058] Chip 10 in the chip structure can have different functions, types, or processes. Chip 10 may include, for example, a logic chip or a system-on-a-chip. Chip 10 includes a first surface and a second surface that are opposite to each other. Figure 2 In the chip structure shown, the first surface of chip 10 is the upper surface A, and the second surface is the lower surface B. For example, chip 10 is a flip chip, and the second surface of chip 10 is an active surface with a circuit pattern.

[0059] The capacitor layer 20 is connected to the second surface of the chip 10. The capacitor layer 20 may, for example, comprise a silicon wafer layer obtained after wafer dicing. The capacitor layer 20 can be connected to the second surface of the chip 10 via a connection layer 40 disposed between the capacitor layer 20 and the chip 10. Alternatively, the capacitor layer 20 can be directly deposited on the second surface for connection. The capacitor layer 20 and the chip 10 may have the same shape and size in the X direction parallel to the first surface, such that the edges of the capacitor layer 20 and the chip 10 are flush in the X direction.

[0060] A capacitor 21 is disposed in the capacitor layer 20. The capacitor 21 in the capacitor layer 20 may include, for example, a deep trench capacitor formed by deep trench technology and deposition process. The capacitor 21 can be used for filtering, bypassing (decoupling), temperature compensation, energy storage, etc., and can improve the signal quality of the power signal of the chip 10. The placement position and number of capacitors 21 in the capacitor layer 20 can be selected according to requirements. For example, multiple capacitors 21 are disposed in the capacitor layer 20. The distance between the surface of the capacitor layer 20 facing the chip 10 and the capacitor 21 is smaller than the distance between the surface of the capacitor layer 20 away from the chip 10 and the capacitor 21. That is, the placement position of the capacitor 21 is closer to the surface of the capacitor layer 20 where it is connected to the chip 10.

[0061] An electrical connector 30 is also provided in the capacitor layer 20. The electrical connector 30 may include, for example, a metal component. The first end of the electrical connector 30 is electrically connected to the chip 10, and the second end of the electrical connector 30 passes through the capacitor layer 20 and is exposed away from the surface of the chip 10. This enables signal output from the chip 10, allowing the chip 10 to be electrically connected to external circuits or devices to ensure the normal operation of the chip 10. For example, the second end of the electrical connector 30 is exposed away from the surface of the chip 10 through the capacitor layer 20 and is electrically connected to the packaging substrate 50, thereby forming an electrical connection path of chip 10-electrical connector 30-packaging substrate 50. This ensures that the chip 10 can be electrically connected to the packaging substrate 50 with its second surface facing it, thereby allowing a capacitor 21 to be provided between the chip 10 and the packaging substrate 50 for subsequent packaging of the chip 10.

[0062] In this embodiment, a capacitor 21 is disposed in the capacitor layer 20, and the capacitor layer 20 is connected to the second surface of the chip 10, thus achieving the placement of the capacitor 21 in close proximity to the chip 10. An electrical connector 30 is disposed in the capacitor layer 20, with its first end electrically connected to the chip 10 and its second end exposed away from the surface of the chip 10 through the capacitor layer 20, enabling signal extraction from the chip 10 for subsequent chip 10 packaging. The capacitor layer 20 and the electrical connector 30 remove spatial limitations on the placement of the capacitor 21 and shorten the distance between the capacitor 21 and the chip 10, providing a higher capacitor 21 placement density for the chip 10. The capacitor 21's characteristics of reducing impedance, suppressing noise, providing transient response support, and improving signal integrity enhance the signal quality of the chip 10's power supply signal, thereby improving the overall performance of the chip structure.

[0063] In some embodiments, capacitor 21 can be independently disposed in capacitor layer 20 without being electrically connected to other devices. For example, capacitor 21 may be an energy storage capacitor. In other embodiments, capacitor 21 is electrically connected to electrical connector 30 to connect to chip 10 via electrical connector. For example, capacitor 21 may be a decoupling capacitor, filtering capacitor, etc. Additionally, capacitor 21 can also be electrically connected to other circuits or devices electrically connected to the second end of electrical connector 30 to connect capacitor 21 to the signal transmission path of external circuits or devices, thereby fulfilling the decoupling or filtering functions of capacitor 21. For example, capacitor 21 may be electrically connected to electrical connector 30 via a metal wiring structure disposed in capacitor layer 20.

[0064] In this embodiment, capacitor 21 is electrically connected to electrical connector 30. Electrical connector 30 enables the electrical connection between capacitor 21 and chip 10, as well as between capacitor 21 and external circuits or devices, so as to connect capacitor 21 to the signal transmission path between external circuits or devices, thereby facilitating the realization of the function of capacitor 21 and helping to further improve the signal quality of power supply signal of chip 10.

[0065] In some embodiments, capacitor 21 includes a deep trench capacitor, wherein the trench of the deep trench capacitor is formed on the surface of capacitor layer 20 facing chip 10.

[0066] The capacitor 21 disposed in the capacitor layer 20 can be a deep trench capacitor (DTC). A deep trench capacitor may include trenches and alternating electrode and dielectric layers within the trenches, and is fabricated through processes such as etching, deposition, and planarization. It features high capacitor density, low parasitic parameters, good electrical performance, and adjustable capacitance. The trenches of the deep trench capacitor are formed on the surface of the capacitor layer 20 facing the chip 10, i.e., the surface where the capacitor layer 20 connects to the second surface of the chip 10. This allows the deep trench capacitor in the capacitor layer 20 to be positioned closest to the chip 10, further shortening the distance between the capacitor 21 and the chip 10.

[0067] In this embodiment, a deep trench capacitor is used as capacitor 21 in capacitor layer 20. The characteristics of deep trench capacitors are used to improve the performance of capacitor 21 and ensure the arrangement density of capacitor 21. The trenches of the deep trench capacitor are opened on the surface of capacitor layer 20 facing chip 10, which further shortens the distance between capacitor 21 and chip 10, thereby further improving the signal quality of power signal of chip 10.

[0068] In some embodiments, the thickness of the capacitor layer 20 is 15–20 μm, and the trench depth of the deep trench capacitor is 8–12 μm.

[0069] By setting the thickness of capacitor layer 20 to 15–20 μm and the trench depth of deep trench capacitor (i.e., the height of capacitor 21) to 8–12 μm, the space utilization of capacitor layer 20 is optimized, the voltage withstand capability of capacitor layer 20 is enhanced, the effective surface area of ​​capacitor 21 electrode is increased, the equivalent series resistance of capacitor 21 is reduced, and the etching uniformity of trench is improved. For example, the thickness of capacitor layer 20 is 20 μm, the trench depth of deep trench capacitor is 10 μm, and the ratio of trench depth to thickness of capacitor layer 20 is 1:2.

[0070] In this embodiment, the thickness of the capacitor layer 20 is set to 15-20 μm, and the trench depth of the deep trench capacitor is set to 8-12 μm. By controlling the thickness and depth and the ratio between the two, the arrangement density of the capacitor 21 is improved, the electrical performance of the capacitor 21 is improved, and the implementation of the process steps is facilitated, thereby further improving the overall performance of the chip structure.

[0071] In some embodiments, multiple capacitors 21 and electrical connectors 30 are provided, and the projection of each electrical connector 30 on the first surface is located between the projections of adjacent capacitors 21 on the first surface.

[0072] like Figure 2 As shown, there are multiple capacitors 21 and electrical connectors 30 disposed in the capacitor layer 20. The projection of each electrical connector 30 on the first surface is located between the projections of adjacent capacitors 21 on the first surface. That is, the electrical connector 30 is located between two capacitors 21 in the X direction, so that the electrical connectors 30 and capacitors 21 can be disposed at intervals in this direction.

[0073] In this embodiment, multiple capacitors 21 and electrical connectors 30 are provided to ensure the arrangement density of capacitors 21 and the interconnection density between chip 10 and external circuits or devices. Each electrical connector 30 is configured such that its projection on the first surface is located between the projections of adjacent capacitors 21 on the first surface, so that electrical connectors 30 and capacitors 21 can be arranged at intervals in this direction. This improves the uniformity of the arrangement of capacitors 21 and electrical connectors 30, ensures the space utilization of capacitor layer 20, and is conducive to improving the electrical performance, heat dissipation effect, process convenience and structural reliability of chip structure.

[0074] In some embodiments, the chip 10 includes a processor region and a non-processor region, and the capacitor layer 20 includes a first region and a second region. In a direction perpendicular to the chip 10, the processor region corresponds to the first region, and the non-processor region corresponds to the second region. Multiple capacitors 21 are provided, and the arrangement density of capacitors 21 in the first region is greater than the arrangement density of capacitors 21 in the second region.

[0075] For example, a system-on-a-chip (SoC) or chip 10 may include multiple functional areas. These functional areas may include processor areas corresponding to processors such as the Central Processing Unit (CPU) and Graphics Processing Unit (GPU), as well as non-processor areas corresponding to other functions. Because the processor areas of chip 10 have complex functions and high operating power, it is necessary to prioritize ensuring the signal quality of the power signals in the processor areas.

[0076] In the direction perpendicular to chip 10, i.e. Figure 2In the Y direction shown, the processor region of chip 10 corresponds to the first region of capacitor layer 20, and the non-processor region of chip 10 corresponds to the second region of capacitor layer 20. When multiple capacitors 21 are provided, the arrangement density of capacitors 21 in the first region is greater than that in the second region. This allows capacitor layer 20 to provide a higher arrangement density of capacitors 21 in the direction perpendicular to chip 10 for the processor region of chip 10, thereby prioritizing the signal quality of the power supply signal in the processor region.

[0077] In this embodiment, multiple capacitors 21 are provided, and the arrangement density of capacitors 21 in the first region is greater than that in the second region. This provides a higher arrangement density of capacitors 21 for the processor region corresponding to the chip 10 in the first region, thereby prioritizing the improvement of the power signal quality of the processor region to support the complex functions and high-power operation of the processor region and improving the overall performance of the chip structure.

[0078] In some embodiments, the chip structure further includes a connection layer 40, which connects the second surface of the chip 10 to the capacitor layer 20.

[0079] The chip structure also includes a connection layer 40 disposed between the chip 10 and the capacitor layer 20. The connection layer 40 can connect the second surface of the chip 10 and the capacitor layer 20 to fix the chip 10 and the capacitor layer 20 to each other. For example, the connection layer 40 may include a layered structure formed by processes such as hybrid bonding, eutectic bonding, conductive adhesive bonding, and silver paste bonding.

[0080] In this embodiment, the chip structure is provided with a connection layer 40, which can connect the second surface of the chip 10 and the capacitor layer 20, ensuring the connection strength between the chip 10 and the capacitor layer 20. Furthermore, the connection layer 40 can improve the heat dissipation and electrical performance between the chip 10 and the capacitor layer 20, which is beneficial to improving the overall performance and structural stability of the chip structure.

[0081] In some embodiments, the connection layer 40 includes a hybrid bonding layer.

[0082] The connection layer 40 connecting the second surface of chip 10 and capacitor layer 20 may include a hybrid bonding layer, which is a layered structure formed by a hybrid bonding process. The hybrid bonding layer can be fabricated through processes such as surface cleaning, surface activation, room temperature bonding, and annealing. The hybrid bonding layer combines dielectric bonding and metal bonding, eliminating the need for traditional solder bumps, and enabling face-to-face connections and high-density, high-performance electrical interconnections between chips 10 or wafers.

[0083] In this embodiment, the hybrid bonding layer made by the hybrid bonding process is used as the connection layer 40. The stable connection between the chip 10 and the capacitor layer 20 is achieved through the hybrid bonding layer, so that the chip 10, the connection layer 40 and the capacitor layer 20 are tightly attached. It has the characteristics of high integration density, excellent electrical and thermal performance, and reduced stress damage, which is beneficial to improving the overall performance and structural stability of the chip structure.

[0084] In some embodiments, the hybrid bonding layer includes a metal pad 41, one side of which is electrically connected to the chip 10 and the other side of which is electrically connected to the electrical connector 30.

[0085] The hybrid bonding layer may include a metal pad 41 formed by metal bonding, thereby achieving electrical interconnection of the hybrid bonding layer. One side of the metal pad 41 is electrically connected to the chip 10, and the other side of the metal pad 41 is electrically connected to the first end of the electrical connector 30, forming an electrical connection path of chip 10-metal pad 41-electrical connector 30, thereby realizing the electrical connection between chip 10 and electrical connector 30 and ensuring that the signals of chip 10 can be led out through electrical connector 30.

[0086] In this embodiment, one end of the metal pad 41 in the hybrid bonding layer is electrically connected to the chip 10, and the other side of the metal pad 41 is electrically connected to the electrical connector 30. The metal pad 41 realizes the electrical connection between the chip 10 and the electrical connector 30, so as to facilitate the signal output of the chip 10 and ensure the stability of the electrical connection between the chip 10 and the electrical connector 30, which is beneficial to improving the overall performance of the chip structure.

[0087] In some embodiments, capacitor 21 is electrically connected to chip 10 via connection layer 40.

[0088] As previously described, capacitor 21 can be electrically connected to electrical connector 30, so that capacitor 21 is electrically connected to chip 10 via electrical connector 30. In this case, capacitor 21 is also electrically connected to an external circuit or device electrically connected to the second end of electrical connector 30. Capacitor layer 20 can also be electrically connected to chip 10 via bonding layer 40, for example, via metal pad 41 in hybrid bonding layer, to realize the function of capacitor 21. In this case, capacitor 21 can be electrically connected only to chip 10 and is not connected to the signal transmission path of external circuits or devices.

[0089] In this embodiment, capacitor 21 is electrically connected to chip 10 through connection layer 40. The connection layer 40 realizes the electrical connection between capacitor 21 and chip 10, which facilitates the function realization of capacitor 21 and helps to further improve the signal quality of power signal of chip 10.

[0090] In some embodiments, the electrical connector 30 includes a first connection portion 31 and a second connection portion 32. The first connection portion 31 penetrates through the capacitor layer 20, and the second connection portion 32 is disposed on the surface of the capacitor layer 20 away from the chip 10. The first connection portion 31 is used to electrically connect the chip 10 and the second connection portion 32.

[0091] like Figure 2 As shown, the electrical connector 30 includes a first connecting portion 31 and a second connecting portion 32. The first connecting portion 31 penetrates the capacitor layer 20 and extends from the capacitor layer 20 toward the surface of the chip 10 to the surface of the capacitor layer 20 away from the chip 10. The second connecting portion 32 is disposed on the surface of the capacitor layer 20 away from the chip 10, so that the second end of the electrical connector 30 is exposed through the surface of the capacitor layer 20 away from the chip 10. The first connecting portion 31 and the second connecting portion 32 are electrically connected, so that the second connecting portion 32 can be electrically connected to the chip 10 through the first connecting portion 31, forming an electrical connection path of chip 10-first connecting portion 31-second connecting portion 32. External circuits or devices can be electrically connected to the electrical connector 30 and the chip 10 by connecting to the exposed second connecting portion 32, so that the signal output of the chip 10 can be realized through the electrical connector 30.

[0092] In this embodiment, the electrical connector 30 is provided with a first connecting portion 31 and a second connecting portion 32. The first connecting portion 31 can penetrate the capacitor layer 20, serving as a signal transmission path within the capacitor layer 20. The second connecting portion 32 is disposed on the surface of the capacitor layer 20 facing away from the chip 10, allowing the second end of the electrical connector 30 to be exposed beyond the surface of the capacitor layer 20 facing away from the chip 10, facilitating signal extraction from the chip 10 via the electrical connector 30. By selecting the size and type of the first connecting portion 31 and the second connecting portion 32, the structural design of the capacitor layer 20 and the electrical connection stability of the electrical connector 30 can be optimized, which is beneficial for improving the overall performance of the chip structure.

[0093] In some embodiments, the first connection portion 31 includes a through-silicon via, and the second connection portion 32 includes a metal bump.

[0094] The first connection portion 31 includes a through-silicon via (TSV) for electrical connection to the chip 10 and through the capacitor layer 20, featuring high signal transmission speed, low power consumption, flexible layout, and high mechanical strength. The second connection portion 32 includes metal bumps, such as copper pillar bumps, for electrical connection to external circuits or devices, exhibiting excellent conductivity, thermal performance, and reliability, facilitating the formation of high-density, low-resistance electrical connections between the chip structure and the packaging substrate 50.

[0095] In this embodiment, a through-silicon via (TSV) is used as the first connection part 31, and a metal bump is used as the second connection part 32. The electrical connection 30, which is composed of TSV and metal bump, realizes the electrical connection between the chip 10 and external circuits or devices. This allows the electrical connection 30 to have the characteristics of TSV and metal bump, ensuring the rationality of the structure and the stability of the electrical connection, and further improving the overall performance of the chip structure.

[0096] In some embodiments, capacitor layer 20 includes a silicon wafer layer.

[0097] The capacitor layer 20 includes a silicon wafer layer, which can be obtained, for example, by dicing a silicon wafer. The silicon wafer layer has stable physical and chemical properties as well as excellent electrical performance, and the processing technology of the silicon wafer layer is mature. Therefore, setting the capacitor 21 in the silicon wafer layer can have advantages such as high stability, low loss, high reliability, high integration, and high compatibility.

[0098] In this embodiment, a silicon wafer layer is selected as the capacitor layer 20. The stable physical and chemical properties and excellent electrical performance of the silicon wafer layer can be utilized, and the fit with the capacitor 21 is relatively high. This is beneficial to improving the performance, integration and frequency characteristics of the capacitor 21, thereby improving the overall performance of the chip structure.

[0099] In some embodiments, chip 10 includes any one of a logic chip, a system-on-a-chip, or a memory chip.

[0100] In this embodiment, a logic chip, memory chip, or system-on-a-chip is used as chip 10 in the chip structure. The capacitor 21 is arranged and the signal output of chip 10 is realized through capacitor layer 20 and electrical connection. This can improve the signal quality of power supply signals of logic chip, memory chip, or system-on-a-chip, so as to meet the high requirements of logic chip, memory chip, and system-on-a-chip for power supply signal quality and improve the performance of logic chip, memory chip, or system-on-a-chip.

[0101] In one exemplary embodiment, reference Figure 3 As shown, a packaging structure is provided, including the chip structure as described above. The packaging structure also includes a packaging substrate 50, and the second end of the electrical connector 30 is electrically connected to the packaging substrate 50, enabling the chip 10 in the chip structure to be electrically connected to the packaging substrate 50. The packaging structure also includes encapsulating material, which wraps the chip structure to encapsulate the chip structure on the packaging substrate 50.

[0102] In this embodiment, since the chip structure included in the packaging structure has the advantage of improving the signal quality of the power signal of the chip 10, the packaging structure has the same advantage as the chip structure it includes.

[0103] In one exemplary embodiment, reference Figure 4 As shown, a circuit board assembly is provided, which includes the packaging structure described above. The circuit board assembly also includes a circuit board 60, which is electrically connected to the packaging structure via a ball grid array or bumps.

[0104] In this embodiment, since the packaging structure included in the circuit board assembly has the advantage of improving the signal quality of the power signal of the chip 10, the circuit board assembly and its included packaging structure have the same advantages.

[0105] In one exemplary embodiment, an electronic device is provided, which includes at least one of the chip structure, packaging structure and circuit board assembly as described above. The electronic device may be, for example, a mobile phone, a tablet computer, a smart bracelet, etc.

[0106] In this embodiment, since the chip structure, packaging structure or circuit board assembly included in the electronic device all have the advantage of improving the signal quality of the power signal of the chip 10, the electronic device has the same advantage.

[0107] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered illustrative only, and the true scope and spirit of this disclosure are indicated by the following claims.

[0108] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A chip structure, characterized in that, The chip structure includes: A chip, the chip including a first surface and a second surface that are opposite to each other; A capacitor layer is connected to the second surface of the chip, and a capacitor is disposed in the capacitor layer; An electrical connector is disposed on the capacitor layer. The first end of the electrical connector is electrically connected to the chip, and the second end of the electrical connector is exposed away from the surface of the chip through the capacitor layer.

2. The chip structure according to claim 1, characterized in that, The capacitor is electrically connected to the electrical connector.

3. The chip structure according to claim 1, characterized in that, The capacitor includes a deep trench capacitor, wherein the trench of the deep trench capacitor is formed on the surface of the capacitor layer facing the chip.

4. The chip structure according to claim 3, characterized in that, The thickness of the capacitor layer is 15–20 μm, and the trench depth of the deep trench capacitor is 8–12 μm.

5. The chip structure according to claim 1, characterized in that, Multiple capacitors and electrical connectors are provided, and the projection of each electrical connector on the first surface is located between the projections of adjacent capacitors on the first surface.

6. The chip structure according to claim 1, characterized in that, The chip includes a processor region and a non-processor region, and the capacitor layer includes a first region and a second region. In a direction perpendicular to the chip, the processor region corresponds to the first region, and the non-processor region corresponds to the second region. The capacitors are provided in multiple ways, and the arrangement density of the capacitors in the first region is greater than the arrangement density of the capacitors in the second region.

7. The chip structure according to any one of claims 1 to 6, characterized in that, The chip structure also includes: A connection layer that connects the second surface of the chip to the capacitor layer.

8. The chip structure according to claim 7, characterized in that, The connecting layer includes a hybrid bonding layer.

9. The chip structure according to claim 8, characterized in that, The hybrid bonding layer includes a metal pad, one side of which is electrically connected to the chip, and the other side of which is electrically connected to the electrical connector.

10. The chip structure according to claim 7, characterized in that, The capacitor is electrically connected to the chip through the connection layer.

11. The chip structure according to any one of claims 1 to 6, characterized in that, The electrical connector includes a first connection portion and a second connection portion. The first connection portion penetrates the capacitor layer, and the second connection portion is disposed on the surface of the capacitor layer opposite to the chip. The first connection portion is used to electrically connect the chip and the second connection portion.

12. The chip structure according to claim 11, characterized in that, The first connection portion includes a through-silicon via, and the second connection portion includes a metal bump.

13. The chip structure according to any one of claims 1 to 6, characterized in that, The capacitor layer includes a silicon wafer layer.

14. The chip structure according to any one of claims 1 to 6, characterized in that, The chip includes any one of a logic chip, a system-on-a-chip, or a memory chip.

15. A packaging structure, characterized in that, The packaging structure includes the chip structure as described in any one of claims 1 to 14, and the packaging structure further includes a packaging substrate, wherein the second end of the electrical connector is electrically connected to the packaging substrate.

16. A circuit board assembly, characterized in that, The circuit board assembly includes the packaging structure as described in claim 15, and the circuit board assembly further includes a circuit board, the circuit board being electrically connected to the packaging substrate of the packaging structure.

17. An electronic device, characterized in that, The electronic device includes a chip structure as described in any one of claims 1 to 14, or the electronic device includes a packaging structure as described in claim 15, or the electronic device includes a circuit board assembly as described in claim 16.

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