Mim capacitor and pixel circuit, imaging device
By setting trenches in the insulating layer, the upper and lower electrode plates of the MIM capacitor extend into the trenches, increasing the capacitance depth and effective area. This solves the problem of the difficulty in reducing the area of MIM capacitors and improves the dynamic range and sensitivity of the image sensor.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- SMARTSENS TECH (SHANGHAI) CO LTD
- Filing Date
- 2025-04-10
- Publication Date
- 2026-05-29
Smart Images
Figure CN224306309U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the technical field of capacitor processing, and in particular to a MIM capacitor, pixel circuit, and imaging device. Background Technology
[0002] A CMOS image sensor (CIS) is a semiconductor device that converts optical images into digital images. To achieve noise levels and sensitivity comparable to CCD converters, CMOS image sensors utilize active pixels. Furthermore, CMOS image sensors employ CMOS integrated circuit technology, integrating the pixel array photosensitive structure and other CMOS analog and digital circuits onto a single chip. This high level of integration not only reduces the number of chips in the entire device, lowering power consumption and packaging costs, but also allows for direct signal connections within the chip, improving signal transmission quality and speed, thereby enhancing image conversion quality. In recent years, CMOS image sensors have continued to evolve towards being "faster, smaller, lighter, and cheaper," while consumers' demands for image quality have also increased.
[0003] The key factors determining the image quality of a CMOS image sensor are dark current and dynamic range. The dynamic range of a CMOS image sensor is determined by the amount of charge that the photodiode (PD) can accumulate. However, since the amount of charge that can be detected when converted into a voltage signal depends on the voltage amplitude and capacitance of the floating diffusion region (FD), the voltage amplitude and capacitance of the FD determine the actual dynamic range of the image sensor; the larger the capacitance value, the higher the image quality.
[0004] Metal-insulator-metal (MIM) capacitors are a type of capacitor commonly used in traditional CMOS processes to store photogenerated charge. MIM capacitors are important components in many circuits, such as many analog, mixed-signal, and radio frequency complementary metal-oxide-semiconductor (RFCMOS) circuits. Due to lower resistance, better matching, and / or better signal-to-noise ratio, MIM capacitors typically offer better performance than alternatives such as POP (polymer-oxide-polymer) capacitors and MOM (metal-oxide-metal lateral flux) capacitors.
[0005] MIM capacitors are typically located only beneath the top metal layer. For example, an existing top metal layer can be used as a substrate, and a top plate with different metals (e.g., titanium or titanium nitride (Ti / TiN), tantalum or titanium nitride (Ta / TaN), or tungsten (W)) can be constructed. The overlying top metal layer is then connected to the top and bottom plates of the capacitor via corresponding vias. The top plate typically has a higher resistance than the bottom plate, for example, because the top plate may be constrained by thickness limitations and the selection of materials for integration, thus limiting the performance of conventional MIM capacitors. The capacitance of a MIM capacitor is proportional to its area, but increasing the area of the storage capacitance requires reducing the photosensitive area of the photodiode, which reduces the sensitivity of the pixel unit.
[0006] Therefore, how to reduce the size of MIM capacitors without affecting their capacitance value is a technical problem that the industry urgently needs to solve. Utility Model Content
[0007] In order to overcome the shortcomings and deficiencies of the existing technology, the purpose of this utility model is to provide a MIM capacitor, pixel circuit, and imaging device to solve the problem that the MIM capacitor cannot be made smaller in area under the same capacitance value in the existing technology.
[0008] The objective of this utility model is achieved through the following technical solution:
[0009] This utility model provides a MIM capacitor, comprising:
[0010] The device comprises an upper electrode plate, a dielectric layer, and a lower electrode plate. The dielectric layer is disposed between the upper electrode plate and the lower electrode plate. The upper electrode plate is provided with an upper electrode plate connecting electrode, one end of which is electrically connected to the upper electrode plate. The lower electrode plate is provided with a lower electrode plate connecting electrode, one end of which is electrically connected to the lower electrode plate.
[0011] A first insulating layer, a first metal wire disposed on the first insulating layer, a second insulating layer disposed on the first insulating layer and covering the first metal wire, a second metal wire disposed on the second insulating layer, and a third insulating layer disposed on the second insulating layer and covering the second metal wire;
[0012] The second insulating layer has a first trench, and the third insulating layer has a second trench that corresponds to and communicates with the first trench. The upper electrode plate, the dielectric layer, and the lower electrode plate all extend at least into the first trench and the second trench.
[0013] This application also provides a pixel circuit, including:
[0014] At least one photodiode;
[0015] At least one MIM capacitor as described above, the MIM capacitor being used to store the photogenerated charge generated by the photodiode or to increase the gain.
[0016] This application also provides an imaging device, including:
[0017] A pixel array comprising a plurality of pixel circuits as described above, arranged in rows and columns;
[0018] The peripheral circuit controls the pixel array and quantizes and processes the pixel signals output by the pixel array.
[0019] The beneficial effects of this invention are as follows: by setting a first trench in the second insulating layer and a second trench corresponding to and connected to the first trench in the third insulating layer, the upper electrode plate, the dielectric layer, and the lower electrode plate all extend at least into the first and second trenches, thereby allowing the MIM capacitor to be made deeper, increasing the effective area of the MIM capacitor and thus increasing the capacitance value of the MIM capacitor; with the same capacitance value, the top-view area of the MIM capacitor can be made smaller, allowing more MIM capacitors to be set on the image sensor and enhancing the dynamic range. Attached Figure Description
[0020] Figure 1 This is a schematic diagram of the cross-sectional structure of the MIM capacitor in Embodiment 1 of this utility model.
[0021] Figure 2 This is a top view schematic diagram of the MIM capacitor structure in Embodiment 1 of this utility model.
[0022] Figures 3a-3j This is a schematic diagram of the manufacturing process of the MIM capacitor in Embodiment 1 of this utility model.
[0023] Figure 4 This is a schematic diagram of the planar structure of the MIM capacitor in Embodiment 2 of this utility model.
[0024] Figures 5a-5i This is a schematic diagram of the manufacturing process of the MIM capacitor in Embodiment 2 of this utility model.
[0025] Figure 6 This is a schematic diagram of the cross-sectional structure of the MIM capacitor in Embodiment 3 of this utility model.
[0026] Figure 7 This is a schematic diagram of the cross-sectional structure of the MIM capacitor in Embodiment 4 of this utility model.
[0027] Figure 8 This is a pixel circuit diagram in this utility model.
[0028] Figure 9 This is another pixel circuit diagram in this utility model.
[0029] Figure 10 This is a schematic diagram of the structure of an imaging device according to this utility model. Detailed Implementation
[0030] To further illustrate the technical means and effects adopted by this utility model to achieve its intended purpose, the following detailed description, in conjunction with the accompanying drawings and preferred embodiments, details the specific implementation methods, structures, features, and effects of the MIM capacitor, pixel circuit, and imaging device proposed according to this utility model:
[0031] [Example 1]
[0032] Figure 1 This is a schematic diagram of the cross-sectional structure of the MIM capacitor in Embodiment 1 of this utility model. Figure 1 As shown in Embodiment 1 of this utility model, a MIM capacitor includes: an upper electrode plate 11, a dielectric layer 12, and a lower electrode plate 13. The dielectric layer 12 is disposed between the upper electrode plate 11 and the lower electrode plate 13 and serves to insulate and separate the upper electrode plate 11 and the lower electrode plate 13 from each other. The upper electrode plate 11 is provided with an upper electrode plate connecting electrode 111, one end of which is electrically connected to the upper electrode plate 11. The lower electrode plate 13 is provided with a lower electrode plate connecting electrode 131, one end of which is electrically connected to the lower electrode plate 13. The upper electrode plate 11, the dielectric layer 12, and the lower electrode plate 13 together form a MIM capacitor. The upper electrode plate connecting electrode 111 and the lower electrode plate connecting electrode 131 are respectively used to connect the upper electrode plate 11 and the lower electrode plate 13 to an external circuit, such as an external control chip.
[0033] The MIM capacitor further includes: a first insulating layer 101, a first metal interconnect 14 disposed on the first insulating layer 101, a second insulating layer 102 disposed on the first insulating layer 101 and covering the first metal interconnect 14, a second metal interconnect 15 disposed on the second insulating layer 102, and a third insulating layer 103 disposed on the second insulating layer 102 and covering the second metal interconnect 15. A first trench 51 is provided in the second insulating layer 102. Figure 3f The third insulating layer 103 is provided with a second groove 52 that corresponds to and communicates with the first groove 51. Figure 3fThe upper electrode plate 11, dielectric layer 12, and lower electrode plate 13 all extend at least into the first trench 51 and the second trench 52, thereby allowing the MIM capacitor to be made deeper, increasing the effective area of the MIM capacitor and thus increasing its capacitance value. The depth of a conventional MIM capacitor is approximately 1500A, while the MIM capacitor in this application, after passing through at least one metal layer and one third insulating layer 103, can reach a depth of 3500A. Therefore, with the same capacitance value, the top-view area (i.e., the projected area on the image sensor) of the MIM capacitor can be made smaller, allowing more MIM capacitors to be placed on the image sensor and enhancing the dynamic range. The first metal interconnect 14 and the second metal interconnect 15 are connection lines for transistors in the image sensor, such as bit lines (configured to read the pixel signal of the pixel to be read to the ADC analog-to-digital converter circuit), lcg lines (lines for reading low-gain signals), etc.
[0034] Figure 2 This is a top view schematic diagram of the MIM capacitor in Embodiment 1 of this utility model. Figure 2 As shown, for example, in a group of MIM capacitors, the spacing CD1 between two adjacent rows of MIM capacitors is ≥0.16, the spacing CD2 between two adjacent groups of MIM capacitors is ≥0.28, and the width of the MIM capacitor is CD3 ≥0.11. Assuming n is the number of MIM capacitors within a 2*2 pixel range, 0.11n+(n-1)0.16+0.28≤2*pixel size. Calculate n and round it to get the maximum number of MIM capacitors. The smaller MIM capacitor size is mainly due to the increased depth of the MIM capacitors, which increases the effective area of the MIM capacitors and increases the capacitance value of the MIM capacitors. Therefore, more quantization of FWC can be achieved, enhancing the dynamic range.
[0035] like Figure 1 As shown, in this embodiment, the upper electrode connecting electrode 111 includes a first upper electrode connecting electrode 111a and a second upper electrode connecting electrode 111b. The first upper electrode connecting electrode 111a is electrically connected to the upper electrode plate 11, and one end of the second upper electrode connecting electrode 111b is electrically connected to the first upper electrode connecting electrode 111a. The first upper electrode connecting electrode 111a and the second upper electrode connecting electrode 111b are formed using different masking processes and etched from different metal film layers. The first upper electrode connecting electrode 111a is located at the bottom of the upper electrode plate 11 and is in conductive contact with the upper electrode plate 11. The second upper electrode connecting electrode 111b and the lower electrode connecting electrode 131 can be formed using the same masking process and etched from the same metal film layer.
[0036] In this embodiment, the first upper electrode connecting electrode 111a is disposed on the first insulating layer 101 and is etched from the same metal layer as the first metal connection line 14. The first upper electrode connecting electrode 111a is exposed from the first trench 51. By etching the first upper electrode connecting electrode 111a and the first metal connection line 14 from the same metal layer, not only can one metal film layer be reduced, but the first upper electrode connecting electrode 111a can also block the etching of the first trench 51 and the second trench 52, preventing etching to the first insulating layer 101, which greatly simplifies the manufacturing process.
[0037] Furthermore, a fourth insulating layer 104 is also provided on the third insulating layer 103, covering the upper electrode plate 11, the dielectric layer 12, and the lower electrode plate 13. The lower electrode plate connecting electrode 131 and the second upper electrode plate connecting electrode 111b are both disposed on the fourth insulating layer 104 and etched from the same metal layer. One end of the lower electrode plate connecting electrode 131 extends to the lower electrode plate 13 and is electrically connected to the lower electrode plate 13. One end of the second upper electrode plate connecting electrode 111b extends to the first upper electrode plate connecting electrode 111a and is electrically connected to the first upper electrode plate connecting electrode 111a. Optionally, a fifth insulating layer 105 is also provided on the fourth insulating layer 104, covering the lower electrode plate connecting electrode 131 and the second upper electrode plate connecting electrode 111b, thereby protecting the lower electrode plate connecting electrode 131 and the second upper electrode plate connecting electrode 111b.
[0038] Figures 3a-3j This is a structural schematic diagram of the manufacturing process of the MIM capacitor in Embodiment 1 of this utility model. Figures 3a-3j As shown, this embodiment also provides a method for manufacturing a MIM capacitor, used to manufacture the MIM capacitor as described above. The manufacturing method includes:
[0039] like Figures 3a-3b As shown, a semiconductor substrate 20 is provided, and a first insulating layer 101 is covered on the semiconductor substrate 20. The semiconductor substrate 20 has a photosensitive region 21. Before covering with the first insulating layer 101, various transistors, such as a transfer transistor TX, a reset transistor RST, a source follower transistor SF, and a row select transistor RS, are fabricated on the semiconductor substrate 20. The fabrication of the photosensitive region 21, the transfer transistor TX, the reset transistor RST, the source follower transistor SF, and the row select transistor RS can be referred to existing technologies and will not be elaborated here.
[0040] like Figure 3cAs shown, a first metal layer 31 is formed on the first insulating layer 101. The first metal layer 31 is etched to form at least a patterned first metal interconnect 14. In this embodiment, the upper electrode connecting electrode 111 includes a first upper electrode connecting electrode 111a and a second upper electrode connecting electrode 111b. The first upper electrode connecting electrode 111a is electrically connected to the upper electrode plate 11, and one end of the second upper electrode connecting electrode 111b is electrically connected to the first upper electrode connecting electrode 111a. During the etching of the first metal layer 31, a patterned first upper electrode connecting electrode 111a is also formed. By etching the first upper electrode connecting electrode 111a and the first metal interconnect 14 from the same metal layer, not only can one metal film layer be reduced, but the first upper electrode connecting electrode 111a can also block the etching of the first trench 51 and the second trench 52, preventing etching to the first insulating layer 101, greatly simplifying the manufacturing process.
[0041] like Figure 3d As shown, a second insulating layer 102 covering the first metal layer 31 is formed on the first insulating layer 101, and the second insulating layer 102 is etched to form a first trench 51. Figure 3f ).
[0042] like Figure 3e As shown, a second metal layer 32 is formed on the second insulating layer 102, and the second metal layer 32 is etched to form at least patterned second metal interconnects 15. The first metal interconnect 14 and the second metal interconnect 15 are connection lines of transistors in an image sensor, such as bit lines (configured to read pixel signals of the pixels to be read to an ADC analog-to-digital converter circuit), lcg lines (lines for reading low-gain signals), etc.
[0043] like Figure 3f As shown, a third insulating layer 103 covering the second metal layer 32 is formed on the second insulating layer 102. The third insulating layer 103 is etched to form a second trench 52. The second trench 52 corresponds to and is interconnected with the first trench 51. The first upper electrode connecting electrode 111a is exposed from the first trench 51 and the second trench 52. In this embodiment, after covering the third insulating layer 103, the second insulating layer 102 and the third insulating layer 103 are etched simultaneously to form the first trench 51 and the second trench 52, thereby simplifying the manufacturing process. Of course, in other embodiments, the second insulating layer 102 and the third insulating layer 103 can also be etched separately, but this would add an additional etching process.
[0044] like Figure 3gAs shown, an upper electrode film 41, a dielectric film 42, and a lower electrode film 42 are sequentially formed on the third insulating layer 103. The upper electrode film 41, the dielectric film 42, and the lower electrode film 42 are simultaneously etched. The upper electrode film 41 forms a patterned upper electrode plate 11, the dielectric film 42 forms a patterned dielectric layer 12, and the lower electrode film 42 forms a patterned lower electrode plate 13. The upper electrode plate 11, the dielectric layer 12, and the lower electrode plate 13 are all partially disposed in the first trench 51 and the second trench 52. The upper electrode plate 11 is in conductive contact with the surface of the first upper electrode plate connecting electrode 111a.
[0045] like Figure 3h As shown, a fourth insulating layer 104 is formed on the third insulating layer 103, covering the upper electrode plate 11, the dielectric layer 12, and the lower electrode plate 13. The fourth insulating layer 104, the third insulating layer 103, and the second insulating layer 102 are simultaneously etched to form a first contact hole 61 corresponding to the lower electrode plate 13 and a second contact hole 62 corresponding to the first upper electrode plate connecting electrode 111a. The lower electrode plate 13 is exposed through the first contact hole 61, and the first upper electrode plate connecting electrode 111a is exposed through the second contact hole 62. The first contact hole 61 penetrates the fourth insulating layer 104, and the second contact hole 62 penetrates the fourth insulating layer 104, the third insulating layer 103, and the second insulating layer 102.
[0046] like Figure 3i As shown, a third metal layer 33 is formed on the fourth insulating layer 104. The third metal layer 33 is etched to form a patterned second upper electrode connecting electrode 111b and a lower electrode connecting electrode 131. The lower electrode connecting electrode 131 is electrically connected to the lower electrode plate 13 through the first contact hole 61, and the second upper electrode connecting electrode 111b is electrically connected to the first upper electrode connecting electrode 111a through the second contact hole 62. The first upper electrode connecting electrode 111a and the second upper electrode connecting electrode 111b together form the upper electrode connecting electrode 11.
[0047] like Figure 3j As shown, a fifth insulating layer 105 is formed on the fourth insulating layer 104 to cover the lower electrode connecting electrode 131 and the second upper electrode connecting electrode 111b, thereby protecting the lower electrode connecting electrode 131 and the second upper electrode connecting electrode 111b.
[0048] In this application, reducing the size of the MIM capacitor will affect the uniformity of the MIM capacitor depth, and may also affect the wafer bow value (the curvature of the silicon substrate) or cause other process problems. The following solutions can be adopted:
[0049] 1. Uniformity issues: Improve uniformity within the wafer surface by adjusting the gas concentration and etching intensity during dry etching;
[0050] 2. Bow value issue: After the MIM capacitor is fabricated, a SiN thin film is grown to correct the excessive bow value caused by the MIM capacitor process.
[0051] New problems arise when MIM capacitors are made deeper, such as the trench sidewalls not being smooth enough. The trench sidewalls can be improved by post-etch treatment after etching. CF4 and O2 can be used to etch part of the trench and then oxidize the rest to ensure smooth sidewalls and good filling effect.
[0052] [Example 2]
[0053] Figure 4 This is a schematic diagram of the planar structure of the MIM capacitor in Embodiment 2 of this utility model. Figure 4 As shown, the MIM capacitor and manufacturing method provided in Embodiment 2 of this utility model are the same as those in Embodiment 1. Figures 1 to 3j The MIM capacitors and their manufacturing methods are basically the same, except that:
[0054] In this embodiment, the first upper electrode connecting electrode 111a is disposed on the second insulating layer 102 and is etched from the same metal layer as the second metal connection line 15. A portion of the first upper electrode connecting electrode 111a extends into the first trench 51. By etching the first upper electrode connecting electrode 111a and the second metal connection line 15 from the same metal layer, not only can one metal film layer be reduced, but the first upper electrode connecting electrode 111a can also block the etching of the second trench 52, greatly simplifying the manufacturing process. Furthermore, the fact that the first upper electrode connecting electrode 111a is partially disposed within the first trench 51 increases the contact area between the first upper electrode connecting electrode 111a and the bottom of the upper electrode plate 11, enhancing the conductive connection effect.
[0055] Figures 5a-5i This is a structural schematic diagram of the manufacturing process of the MIM capacitor in Embodiment 2 of this utility model. Figures 5a-5i As shown, this embodiment also provides a method for manufacturing a MIM capacitor, used to manufacture the MIM capacitor as described above. The manufacturing method includes:
[0056] like Figure 5aAs shown, a semiconductor substrate 20 is provided, and a first insulating layer 101 is covered on the semiconductor substrate 20. The semiconductor substrate 20 has a photosensitive region 21. Before covering with the first insulating layer 101, various transistors, such as a transfer transistor TX, a reset transistor RST, a source follower transistor SF, and a row select transistor RS, are fabricated on the semiconductor substrate 20. The fabrication of the photosensitive region 21, the transfer transistor TX, the reset transistor RST, the source follower transistor SF, and the row select transistor RS can be referred to existing technologies and will not be elaborated here.
[0057] like Figure 5b As shown, a first metal layer 31 is formed on the first insulating layer 101, and the first metal layer 31 is etched to form at least a patterned first metal line 14.
[0058] like Figure 5c As shown, a second insulating layer 102 covering the first metal layer 31 is formed on the first insulating layer 101, and the second insulating layer 102 is etched to form a first trench 51. That is, in this embodiment, the second insulating layer 102 is etched to form the first trench 51 after the second insulating layer 102 is formed and before the second metal layer 32 is formed.
[0059] like Figure 5d As shown, a second metal layer 32 is formed on the second insulating layer 102, and the second metal layer 32 is etched to form at least patterned second metal interconnects 15. The first metal interconnect 14 and the second metal interconnect 15 are connection lines of transistors in an image sensor, such as bit lines (configured to read pixel signals of the pixels to be read to an ADC analog-to-digital converter circuit), lcg lines (lines for reading low-gain signals), etc. In this embodiment, the upper electrode connection electrode 111 includes a first upper electrode connection electrode 111a and a second upper electrode connection electrode 111b. The first upper electrode connection electrode 111a is electrically connected to the upper electrode plate 11, and one end of the second upper electrode connection electrode 111b is electrically connected to the first upper electrode connection electrode 111a. During the etching of the second metal layer 32, a patterned first upper electrode plate connecting electrode 111a is also formed. By etching the first upper electrode plate connecting electrode 111a and the second metal connection line 15 from the same metal layer, not only can one metal film layer be reduced, but the first upper electrode plate connecting electrode 111a can also block the etching of the second trench 52, greatly simplifying the manufacturing process. Moreover, since the first upper electrode plate connecting electrode 111a is partially located in the first trench 51, the contact area between the first upper electrode plate connecting electrode 111a and the bottom of the upper electrode plate 11 can be increased, thereby enhancing the conductive connection effect.
[0060] like Figure 5eAs shown, a third insulating layer 103 covering the second metal layer 32 is formed on the second insulating layer 102. The third insulating layer 103 is etched to form a second trench 52. The second trench 52 corresponds to and is interconnected with the first trench 51. The first upper electrode connecting electrode 111a is exposed from the second trench 52. That is, in this embodiment, the second insulating layer 102 and the third insulating layer 103 are etched using different masking processes.
[0061] like Figure 5f As shown, an upper electrode film 41, a dielectric film 42, and a lower electrode film 42 are sequentially formed on the third insulating layer 103. The upper electrode film 41, the dielectric film 42, and the lower electrode film 42 are simultaneously etched. The upper electrode film 41 forms a patterned upper electrode plate 11, the dielectric film 42 forms a patterned dielectric layer 12, and the lower electrode film 42 forms a patterned lower electrode plate 13. The upper electrode plate 11, the dielectric layer 12, and the lower electrode plate 13 are all partially disposed in the first trench 51 and the second trench 52. The upper electrode plate 11 is in conductive contact with the surface of the first upper electrode plate connecting electrode 111a.
[0062] like Figure 5g As shown, a fourth insulating layer 104 is formed on the third insulating layer 103, covering the upper electrode plate 11, the dielectric layer 12, and the lower electrode plate 13. The fourth insulating layer 104 and the third insulating layer 103 are simultaneously etched to form a first contact hole 61 corresponding to the lower electrode plate 13 and a second contact hole 62 corresponding to the first upper electrode plate connecting electrode 111a. The lower electrode plate 13 is exposed through the first contact hole 61, and the first upper electrode plate connecting electrode 111a is exposed through the second contact hole 62. The first contact hole 61 penetrates the fourth insulating layer 104, and the second contact hole 62 penetrates both the fourth insulating layer 104 and the third insulating layer 103.
[0063] like Figure 5h As shown, a third metal layer 33 is formed on the fourth insulating layer 104. The third metal layer 33 is etched to form a patterned second upper electrode connecting electrode 111b and a lower electrode connecting electrode 131. The lower electrode connecting electrode 131 is electrically connected to the lower electrode plate 13 through the first contact hole 61, and the second upper electrode connecting electrode 111b is electrically connected to the first upper electrode connecting electrode 111a through the second contact hole 62. The first upper electrode connecting electrode 111a and the second upper electrode connecting electrode 111b together form the upper electrode connecting electrode 11.
[0064] like Figure 5i As shown, a fifth insulating layer 105 is formed on the fourth insulating layer 104 to cover the lower electrode connecting electrode 131 and the second upper electrode connecting electrode 111b, thereby protecting the lower electrode connecting electrode 131 and the second upper electrode connecting electrode 111b.
[0065] Those skilled in the art should understand that the remaining structures and working principles of this embodiment are the same as those of Embodiment 1, and will not be repeated here.
[0066] [Example 3]
[0067] Figure 6 This is a schematic diagram of the cross-sectional structure of the MIM capacitor in Embodiment 3 of this utility model. Figure 6 As shown, the MIM capacitor and manufacturing method provided in Embodiment 3 of this utility model are the same as those in Embodiment 1. Figures 1 to 3j The MIM capacitors and their manufacturing methods are basically the same, except that:
[0068] In this embodiment, a third trench 53 is provided in the first insulating layer 101. The third trench 53 corresponds to and is interconnected with the first trench 51. The upper electrode plate 11, the dielectric layer 12, and the lower electrode plate 13 all extend at least into the first trench 51, the second trench 52, and the third trench 53. By extending the upper electrode plate 11, the dielectric layer 12, and the lower electrode plate 13 at least into the first trench 51, the second trench 52, and the third trench 53, the depth of the MIM capacitor can be made deeper, increasing the effective area of the MIM capacitor and thus increasing its capacitance value. Therefore, with the same capacitance value, the top-view area of the MIM capacitor (i.e., the projected area on the image sensor) can be made smaller, allowing more MIM capacitors to be placed on the image sensor and enhancing the dynamic range.
[0069] In this embodiment, the first upper electrode connecting electrode 111a is disposed on the first insulating layer 101 and is etched from the same metal layer as the first metal connection line 14. A portion of the first upper electrode connecting electrode 111a extends into the third trench 53. By etching the first upper electrode connecting electrode 111a and the second metal connection line 15 from the same metal layer, not only can one metal film layer be reduced, but the first upper electrode connecting electrode 111a can also block the etching of the second trench 52, greatly simplifying the manufacturing process. Furthermore, extending a portion of the first upper electrode connecting electrode 111a into the third trench 53 increases the contact area between the first upper electrode connecting electrode 111a and the bottom of the upper electrode plate 11, enhancing the conductive connection effect.
[0070] refer to Figures 3a-3j As shown, this embodiment also provides a method for manufacturing a MIM capacitor, used to manufacture the MIM capacitor as described above. The manufacturing method includes:
[0071] refer to Figures 3a-3bAs shown, a semiconductor substrate 20 is provided, and a first insulating layer 101 is covered on the semiconductor substrate 20. The first insulating layer 101 is etched to form a third trench 53. The semiconductor substrate 20 has a photosensitive region 21. Before covering the first insulating layer 101, various transistors, such as a transfer transistor TX, a reset transistor RST, a source follower transistor SF, and a row select transistor RS, are fabricated on the semiconductor substrate 20. The fabrication of the photosensitive region 21, the transfer transistor TX, the reset transistor RST, the source follower transistor SF, and the row select transistor RS can be referred to existing technologies and will not be elaborated here.
[0072] refer to Figure 3c As shown, a first metal layer 31 is formed on the first insulating layer 101. The first metal layer 31 is etched to form at least a patterned first metal interconnect 14. In this embodiment, the upper electrode connecting electrode 111 includes a first upper electrode connecting electrode 111a and a second upper electrode connecting electrode 111b. The first upper electrode connecting electrode 111a is electrically connected to the upper electrode plate 11, and one end of the second upper electrode connecting electrode 111b is electrically connected to the first upper electrode connecting electrode 111a. During the etching of the first metal layer 31, a patterned first upper electrode connecting electrode 111a is also formed. By etching the first upper electrode connecting electrode 111a and the first metal interconnect 14 from the same metal layer, not only can one metal film layer be reduced, but the first upper electrode connecting electrode 111a can also block the etching of the first trench 51 and the second trench 52, preventing etching to the first insulating layer 101, greatly simplifying the manufacturing process. Furthermore, the fact that the first upper electrode plate connecting electrode 111a is partially disposed within the third groove 53 can increase the contact area between the first upper electrode plate connecting electrode 111a and the bottom of the upper electrode plate 11, thereby enhancing the conductive connection effect.
[0073] refer to Figure 3d As shown, a second insulating layer 102 covering the first metal layer 31 is formed on the first insulating layer 101, and the second insulating layer 102 is etched to form a first trench 51. Figure 3f ).
[0074] refer to Figure 3e As shown, a second metal layer 32 is formed on the second insulating layer 102, and the second metal layer 32 is etched to form at least patterned second metal interconnects 15. The first metal interconnect 14 and the second metal interconnect 15 are connection lines of transistors in an image sensor, such as bit lines (configured to read pixel signals of the pixels to be read to an ADC analog-to-digital converter circuit), lcg lines (lines for reading low-gain signals), etc.
[0075] refer to Figure 3fAs shown, a third insulating layer 103 covering the second metal layer 32 is formed on the second insulating layer 102. The third insulating layer 103 is etched to form a second trench 52. The second trench 52 corresponds to and is interconnected with the first trench 51. The first upper electrode connecting electrode 111a is exposed from the first trench 51 and the second trench 52. In this embodiment, after covering the third insulating layer 103, the second insulating layer 102 and the third insulating layer 103 are etched simultaneously to form the first trench 51 and the second trench 52, thereby simplifying the manufacturing process. Of course, in other embodiments, the second insulating layer 102 and the third insulating layer 103 can also be etched separately, but this would add an additional etching process.
[0076] refer to Figure 3g As shown, an upper electrode film 41, a dielectric film 42, and a lower electrode film 42 are sequentially formed on the third insulating layer 103. The upper electrode film 41, the dielectric film 42, and the lower electrode film 42 are simultaneously etched. The upper electrode film 41 forms a patterned upper electrode plate 11, the dielectric film 42 forms a patterned dielectric layer 12, and the lower electrode film 42 forms a patterned lower electrode plate 13. The upper electrode plate 11, the dielectric layer 12, and the lower electrode plate 13 are all partially disposed in the first trench 51, the second trench 52, and the third trench 53. The upper electrode plate 11 is in conductive contact with the surface of the first upper electrode plate connecting electrode 111a.
[0077] refer to Figure 3h As shown, a fourth insulating layer 104 is formed on the third insulating layer 103, covering the upper electrode plate 11, the dielectric layer 12, and the lower electrode plate 13. The fourth insulating layer 104, the third insulating layer 103, and the second insulating layer 102 are simultaneously etched to form a first contact hole 61 corresponding to the lower electrode plate 13 and a second contact hole 62 corresponding to the first upper electrode plate connecting electrode 111a. The lower electrode plate 13 is exposed through the first contact hole 61, and the first upper electrode plate connecting electrode 111a is exposed through the second contact hole 62. The first contact hole 61 penetrates the fourth insulating layer 104, and the second contact hole 62 penetrates the fourth insulating layer 104, the third insulating layer 103, and the second insulating layer 102.
[0078] refer to Figure 3i As shown, a third metal layer 33 is formed on the fourth insulating layer 104. The third metal layer 33 is etched to form a patterned second upper electrode connecting electrode 111b and a lower electrode connecting electrode 131. The lower electrode connecting electrode 131 is electrically connected to the lower electrode plate 13 through the first contact hole 61, and the second upper electrode connecting electrode 111b is electrically connected to the first upper electrode connecting electrode 111a through the second contact hole 62. The first upper electrode connecting electrode 111a and the second upper electrode connecting electrode 111b together form the upper electrode connecting electrode 11.
[0079] refer to Figure 3j As shown, a fifth insulating layer 105 is formed on the fourth insulating layer 104 to cover the lower electrode connecting electrode 131 and the second upper electrode connecting electrode 111b, thereby protecting the lower electrode connecting electrode 131 and the second upper electrode connecting electrode 111b.
[0080] Those skilled in the art should understand that the remaining structures and working principles of this embodiment are the same as those of Embodiment 1, and will not be repeated here.
[0081] [Example 4]
[0082] Figure 7 This is a schematic diagram of the cross-sectional structure of the MIM capacitor in Embodiment 4 of this utility model. Figure 7 As shown, the MIM capacitor and manufacturing method provided in Embodiment 4 of this utility model are similar to those in Embodiment 2. Figures 4 to 5i The MIM capacitors and their manufacturing methods are basically the same, except that:
[0083] In this embodiment, a third trench 53 is provided in the first insulating layer 101. The third trench 53 corresponds to and is interconnected with the first trench 51. The upper electrode plate 11, the dielectric layer 12, and the lower electrode plate 13 all extend at least into the first trench 51, the second trench 52, and the third trench 53. By extending the upper electrode plate 11, the dielectric layer 12, and the lower electrode plate 13 at least into the first trench 51, the second trench 52, and the third trench 53, the depth of the MIM capacitor can be made deeper, increasing the effective area of the MIM capacitor and thus increasing its capacitance value. Therefore, with the same capacitance value, the top-view area of the MIM capacitor (i.e., the projected area on the image sensor) can be made smaller, allowing more MIM capacitors to be placed on the image sensor and enhancing the dynamic range.
[0084] In this embodiment, the first upper electrode connecting electrode 111a is disposed on the second insulating layer 102 and is etched from the same metal layer as the second metal connection line 15. The first upper electrode connecting electrode 111a extends partially into the first trench 51 and the third trench 53. By etching the first upper electrode connecting electrode 111a and the second metal connection line 15 from the same metal layer, not only can one metal film layer be reduced, but the first upper electrode connecting electrode 111a can also block the etching of the second trench 52, greatly simplifying the manufacturing process. Furthermore, it can increase the contact area between the first upper electrode connecting electrode 111a and the bottom of the upper electrode plate 11, enhancing the conductive connection effect.
[0085] refer to Figures 5a-5i As shown, this embodiment also provides a method for manufacturing a MIM capacitor, used to manufacture the MIM capacitor as described above. The manufacturing method includes:
[0086] refer to Figure 5a As shown, a semiconductor substrate 20 is provided, and a first insulating layer 101 is covered on the semiconductor substrate 20. The first insulating layer 101 is etched to form a third trench 53. The semiconductor substrate 20 has a photosensitive region 21. Before covering the first insulating layer 101, various transistors, such as a transfer transistor TX, a reset transistor RST, a source follower transistor SF, and a row select transistor RS, are fabricated on the semiconductor substrate 20. The fabrication of the photosensitive region 21, the transfer transistor TX, the reset transistor RST, the source follower transistor SF, and the row select transistor RS can be referred to existing technologies and will not be elaborated here.
[0087] refer to Figure 5b As shown, a first metal layer 31 is formed on the first insulating layer 101, and the first metal layer 31 is etched to form at least a patterned first metal line 14.
[0088] refer to Figure 5c As shown, a second insulating layer 102 covering the first metal layer 31 is formed on the first insulating layer 101. The second insulating layer 102 is then etched to form a first trench 51. That is, in this embodiment, the second insulating layer 102 is etched to form the first trench 51 after the second insulating layer 102 is formed and before the second metal layer 32 is formed. Optionally, the first insulating layer 101 and the second insulating layer 102 can be etched simultaneously to form a third trench 53 and a first trench 51, respectively, to simplify the manufacturing process.
[0089] refer to Figure 5dAs shown, a second metal layer 32 is formed on the second insulating layer 102, and the second metal layer 32 is etched to form at least patterned second metal interconnects 15. The first metal interconnect 14 and the second metal interconnect 15 are connection lines of transistors in an image sensor, such as bit lines (configured to read pixel signals of the pixels to be read to an ADC analog-to-digital converter circuit), lcg lines (lines for reading low-gain signals), etc. In this embodiment, the upper electrode connection electrode 111 includes a first upper electrode connection electrode 111a and a second upper electrode connection electrode 111b. The first upper electrode connection electrode 111a is electrically connected to the upper electrode plate 11, and one end of the second upper electrode connection electrode 111b is electrically connected to the first upper electrode connection electrode 111a. During the etching of the second metal layer 32, a patterned first upper electrode plate connecting electrode 111a is also formed. By etching the first upper electrode plate connecting electrode 111a and the second metal connection line 15 from the same metal layer, not only can one metal film layer be reduced, but the first upper electrode plate connecting electrode 111a can also block the etching of the second trench 52, greatly simplifying the manufacturing process. Moreover, since the first upper electrode plate connecting electrode 111a is partially located in the first trench 51 and the third trench 53, the contact area between the first upper electrode plate connecting electrode 111a and the bottom of the upper electrode plate 11 can be increased, thereby enhancing the conductive connection effect.
[0090] refer to Figure 5e As shown, a third insulating layer 103 covering the second metal layer 32 is formed on the second insulating layer 102. The third insulating layer 103 is etched to form a second trench 52. The second trench 52 corresponds to and is interconnected with the first trench 51. The first upper electrode connecting electrode 111a is exposed from the second trench 52. That is, in this embodiment, the second insulating layer 102 and the third insulating layer 103 are etched using different masking processes.
[0091] refer to Figure 5f As shown, an upper electrode film 41, a dielectric film 42, and a lower electrode film 42 are sequentially formed on the third insulating layer 103. The upper electrode film 41, the dielectric film 42, and the lower electrode film 42 are simultaneously etched. The upper electrode film 41 forms a patterned upper electrode plate 11, the dielectric film 42 forms a patterned dielectric layer 12, and the lower electrode film 42 forms a patterned lower electrode plate 13. The upper electrode plate 11, the dielectric layer 12, and the lower electrode plate 13 are all partially disposed in the first trench 51, the second trench 52, and the third trench 53. The upper electrode plate 11 is in conductive contact with the surface of the first upper electrode plate connecting electrode 111a.
[0092] refer to Figure 5gAs shown, a fourth insulating layer 104 is formed on the third insulating layer 103, covering the upper electrode plate 11, the dielectric layer 12, and the lower electrode plate 13. The fourth insulating layer 104 and the third insulating layer 103 are simultaneously etched to form a first contact hole 61 corresponding to the lower electrode plate 13 and a second contact hole 62 corresponding to the first upper electrode plate connecting electrode 111a. The lower electrode plate 13 is exposed through the first contact hole 61, and the first upper electrode plate connecting electrode 111a is exposed through the second contact hole 62. The first contact hole 61 penetrates the fourth insulating layer 104, and the second contact hole 62 penetrates both the fourth insulating layer 104 and the third insulating layer 103.
[0093] refer to Figure 5h As shown, a third metal layer 33 is formed on the fourth insulating layer 104. The third metal layer 33 is etched to form a patterned second upper electrode connecting electrode 111b and a lower electrode connecting electrode 131. The lower electrode connecting electrode 131 is electrically connected to the lower electrode plate 13 through the first contact hole 61, and the second upper electrode connecting electrode 111b is electrically connected to the first upper electrode connecting electrode 111a through the second contact hole 62. The first upper electrode connecting electrode 111a and the second upper electrode connecting electrode 111b together form the upper electrode connecting electrode 11.
[0094] refer to Figure 5i As shown, a fifth insulating layer 105 is formed on the fourth insulating layer 104 to cover the lower electrode connecting electrode 131 and the second upper electrode connecting electrode 111b, thereby protecting the lower electrode connecting electrode 131 and the second upper electrode connecting electrode 111b.
[0095] Those skilled in the art should understand that the remaining structure and working principle of this embodiment are the same as those of Embodiment 2, and will not be repeated here.
[0096] The MIM capacitors provided in the first to fourth embodiments can be used in integrated circuit chips. Figure 8 This is a pixel circuit diagram from this utility model. For example... Figure 8 As shown, a first pixel circuit 200 using a MIM capacitor as the DCG capacitor of this invention is provided. The first pixel circuit 200 includes a photodiode PD, a transfer transistor TX, a reset transistor RST, a source follower transistor SF, and a row selection transistor RS. Furthermore, the pixel circuit also includes a high-density MIM capacitor Cdcg used as the DCG capacitor. Because the capacitance value of Cdcg is significantly increased, the Double Conversion Gain (DCG) effect is improved, thereby enhancing image quality in low light conditions.
[0097] Figure 9 This is another pixel circuit diagram in this utility model. For example... Figure 9As shown, a second pixel circuit 300 using the MIM capacitor Csig of this invention to store signal signals is provided. The second pixel circuit 300 includes a photodiode PD and a transfer transistor TX. The transfer transistor TX is connected to a floating diffusion region FD. The floating diffusion region FD is connected to a reset transistor RST and a first source follower transistor SF.
[0098] Furthermore, the second pixel circuit 300 includes a second source follower transistor GSF and a row selection transistor GSW, which can form an output circuit to provide an output signal. Capacitors Csig and Crst, along with corresponding switches GS_SIG and GS_RST, are connected between the first source follower transistor SF and the second source follower transistor GSF.
[0099] In global shutter mode, the photogenerated charge of the photodiode PD is transferred to the floating diffusion region FD and then stored in the capacitor Csig. Because the capacitance of capacitor Csig is significantly increased, the noise during readout of the pixel circuit is very low, greatly improving the signal-to-noise ratio. Furthermore, the number of photodiodes in the pixel circuit can be further increased to improve image resolution.
[0100] Figure 8 and Figure 9 The pixel circuit shown is only one possible implementation; the pixel circuit of this invention can also include other structures. Since the MIM capacitor increases the capacitance value without occupying the original photosensitive area of the photodiode, it improves dynamic range and image quality without sacrificing the sensitivity of the pixel circuit.
[0101] Figure 10 This is a schematic diagram of the structure of an imaging device according to this utility model. Figure 10 As shown, an imaging device 400 employing the high-density MIM capacitor of this invention is provided, particularly an image sensor, such as... Figure 10 As shown, the image sensor also includes a pixel array 410. The pixel array 410 contains multiple pixel units arranged in rows and columns. Each column of pixels in the pixel array 410 is selectively connected by a column selection line and driven by a column driving unit 430; each row of pixels is selectively output by a row selection line and driven by a row driving unit 420. Specifically, each pixel unit includes a pixel circuit, wherein at least one pixel circuit uses the high-density MIM capacitor of this invention as a storage capacitor to store the photogenerated charge of the photodiode. The readout image signal is transmitted to the image processing unit 460 via the column A / D conversion unit 450 for signal processing to synthesize a high dynamic range image. The logic control unit 440 controls the various functional units, including the row driving unit 420, column driving unit 430, column A / D conversion unit 450, and image processing unit 460.
[0102] The image sensor 400 can be used in various processing systems that include the image sensor. Without limitation, such processing systems may include computer systems, camera systems, scanners, machine vision systems, vehicle navigation systems, video phones, surveillance systems, autofocus systems, star tracker systems, motion detection systems, image stabilization systems, and data compression systems.
[0103] In this document, the directional terms such as up, down, left, right, front, and back are defined according to the position of the structures in the accompanying drawings and the relative positions of the structures, and are only used for clarity and convenience in expressing the technical solution. It should be understood that the use of these directional terms should not limit the scope of protection claimed in this application. It should also be understood that the terms "first" and "second," etc., used herein are only used for distinction in name and are not used to limit the number or order.
[0104] The above description is merely a preferred embodiment of the present utility model and is not intended to limit the present utility model in any way. Although the present utility model has been disclosed above with reference to a preferred embodiment, it is not intended to limit the present utility model. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content without departing from the scope of the technical solution of the present utility model. These are equivalent embodiments with equivalent changes. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present utility model without departing from the scope of the technical solution of the present utility model shall still fall within the protection scope of the technical solution of the present utility model.
Claims
1. A MIM capacitor, characterized in that, include: The upper electrode plate (11), the dielectric layer (12), and the lower electrode plate (13) are provided. The dielectric layer (12) is disposed between the upper electrode plate (11) and the lower electrode plate (13). The upper electrode plate (11) is provided with an upper electrode plate connecting electrode (111), one end of which is electrically connected to the upper electrode plate (11). The lower electrode plate (13) is provided with a lower electrode plate connecting electrode (131), one end of which is electrically connected to the lower electrode plate (13). A first insulating layer (101), a first metal wire (14) disposed on the first insulating layer (101), a second insulating layer (102) disposed on the first insulating layer (101) and covering the first metal wire (14), a second metal wire (15) disposed on the second insulating layer (102), and a third insulating layer (103) disposed on the second insulating layer (102) and covering the second metal wire (15); The second insulating layer (102) has a first trench (51), and the third insulating layer (103) has a second trench (52) that corresponds to and communicates with the first trench (51). The upper electrode plate (11), the dielectric layer (12) and the lower electrode plate (13) all extend at least into the first trench (51) and the second trench (52).
2. The MIM capacitor according to claim 1, characterized in that, The upper electrode connecting electrode (111) includes a first upper electrode connecting electrode (111a) and a second upper electrode connecting electrode (111b). The first upper electrode connecting electrode (111a) is electrically connected to the upper electrode plate (11), and one end of the second upper electrode connecting electrode (111b) is electrically connected to the first upper electrode connecting electrode (111a).
3. The MIM capacitor according to claim 2, characterized in that, The first upper electrode connecting electrode (111a) is disposed on the first insulating layer (101) and is etched from the same metal layer as the first metal connection line (14). The first upper electrode connecting electrode (111a) is exposed from the first trench (51).
4. The MIM capacitor according to claim 2, characterized in that, The first upper electrode connecting electrode (111a) is disposed on the second insulating layer (102) and is etched from the same metal layer as the second metal connection line (15). The first upper electrode connecting electrode (111a) extends into the first trench (51).
5. The MIM capacitor according to claim 2, characterized in that, The first insulating layer (101) has a third trench (53) which corresponds to and is connected to the first trench (51). The upper electrode plate (11), the dielectric layer (12) and the lower electrode plate (13) all extend into the first trench (51), the second trench (52) and the third trench (53).
6. The MIM capacitor according to claim 5, characterized in that, The first upper electrode connecting electrode (111a) is disposed on the first insulating layer (101) and is etched from the same metal layer as the first metal connection line (14). The first upper electrode connecting electrode (111a) extends into the third trench (53).
7. The MIM capacitor according to claim 5, characterized in that, The first upper electrode connecting electrode (111a) is disposed on the second insulating layer (102) and is etched from the same metal layer as the second metal connection line (15). The first upper electrode connecting electrode (111a) extends into the first trench (51) and the third trench (53).
8. The MIM capacitor according to claim 2, characterized in that, The third insulating layer (103) is provided with a fourth insulating layer (104) covering the upper electrode plate (11), the dielectric layer (12) and the lower electrode plate (13). The lower electrode plate connecting electrode (131) and the second upper electrode plate connecting electrode (111b) are both disposed on the fourth insulating layer (104) and are etched from the same metal layer. One end of the lower electrode plate connecting electrode (131) extends to the lower electrode plate (13) and is electrically connected to the lower electrode plate (13). One end of the second upper electrode plate connecting electrode (111b) extends to the first upper electrode plate connecting electrode (111a) and is electrically connected to the first upper electrode plate connecting electrode (111a).
9. A pixel circuit, characterized in that, include: At least one photodiode; At least one MIM capacitor as claimed in any one of claims 1-8, the MIM capacitor being used to store photogenerated charge generated by the photodiode or to increase gain.
10. An imaging device, characterized in that, include: A pixel array comprising a plurality of pixel circuits as described in claim 9, arranged in rows and columns; The peripheral circuit controls the pixel array and quantizes and processes the pixel signals output by the pixel array.