An Lrms input / output module

Abstract

The utility model discloses a kind of LRMs input-output module, including processing unit, input-output unit, communication unit, power supply unit and LRM connector, wherein: processing unit includes mutually communicating FPGA and MCU, FPGA is connected with LRM connector by input-output unit;MCU is connected with LRM connector by CAN interface chip, isolation interface chip;The one end of power supply unit is connected with LRM connector, provides double-path power supply for the processing unit after filtering and conversion to input voltage.The input-output module proposed by the utility model can process multiple input-output IO switch quantity signals, has multiple isolated communication interfaces, has double-path power supply function and flexible programmable characteristics, is highly universal, and is very beneficial to be applied in artillery electronics, electrical system.

Description

Technical Field

[0001] This utility model relates to the field of integrated electronic systems for artillery, specifically to an LRMs input / output module. Background Technology

[0002] Traditional artillery's I / O switching control function is not handled by standard input / output modules. Instead, a small number of input / output interface circuits are used on various circuit boards to collect signals related to the equipment itself and then perform simple logic combinations. There is no overall system-wide consideration, and the timing of various I / O switching control is not unified. Some key logic functions require coordination of multiple components to be realized. As equipment continues to develop and the number of input / output signals increases, the shortcomings of this approach become more prominent. Summary of the Invention

[0003] The purpose of this invention is to provide an LRMs input / output module that can realize the acquisition and control of IO switch quantities in the artillery integrated electronic system, and can also be used for the acquisition and control of switch quantities in the artillery electrical manager.

[0004] To achieve the above objectives, the present invention adopts the following technical solution:

[0005] An LRM input / output module includes a processing unit, an input / output unit, a communication unit, a power supply unit, and an LRM connector, wherein:

[0006] The processing unit includes an FPGA and an MCU that communicate with each other. The FPGA is connected to the LRM connector through an input / output unit; the MCU is connected to the LRM connector through a CAN interface chip and an isolation interface chip; one end of the power supply unit is connected to the LRM connector, and provides dual power supply to the processing unit after filtering and converting the input voltage.

[0007] Furthermore, the input / output unit includes an input unit and an output unit, wherein the input unit uses multiple bidirectional optocouplers for isolation to acquire and level-convert external switch input signals; the output unit uses multiple optocouplers + PMOS.

[0008] Furthermore, the input unit includes multiple D001 units, each D001 unit containing a bidirectional optocoupler; the first input terminal IN1 of the bidirectional optocoupler receives external switch input signals, and the second input terminal IN2 of the bidirectional optocouplers of a preset number of D001 units adopts a common ground; the output IN1_c of the bidirectional optocoupler is a switch input signal after optocoupler isolation and level conversion processing.

[0009] Furthermore, the output unit includes multiple D002 units; each D002 unit includes an NPN transistor, an optocoupler, and a P-channel MOS; wherein, the base of the NPN transistor is used to receive the switching output signal OUT1 from the processing unit, the emitter is grounded, and the collector is connected to the optocoupler; the output of the optocoupler is used to generate an isolated and level-converted switching output signal OUT1_C after passing through the P-channel MOS; the drive voltage supply of the P-channel MOS is provided to the outside through the LRM connector.

[0010] Furthermore, the communication unit includes four-channel timing communication, two-channel CAN communication, and one-channel RS422 / 485 communication. The four-channel timing communication features isolated transmission, and the timing signals are programmed via FPGA to input or output timing signals. The FPGA in the processing unit configures the input or output status, sets the period and duty cycle of the output timing signal, and the trigger time of the input timing signal. The two-channel CAN communication features isolated transmission, and the CAN control function is implemented through the MCU in the processing unit. The one-channel RS422 / 485 communication features isolated transmission, and the control function is implemented through the MCU in the processing unit.

[0011] Furthermore, the timing communication, CAN communication, and RS422 / 485 communication of the communication unit are all isolated by an isolation interface chip; the isolation interface chip includes an integrated isolation chip, optocoupler isolation, and digital isolator; the timing output signal adopts differential serial port transmission; the CAN communication and RS422 / 485 communication are implemented by the CAN controller, CAN interface chip, and UART controller on the MCU, and then isolated by the isolation interface chip.

[0012] Furthermore, the power supply unit includes a TVS protection unit, a filtering unit, a dual-channel power supply control unit, a DC-DC converter unit, and an LDO chip, wherein:

[0013] The power supply unit supports dual input voltages. After the dual input voltages are processed by the TVS protection unit for overvoltage protection and the filtering unit, they enter the dual power supply control circuit. After the DC-DC conversion unit converts the level, the first power supply is output, and then the second power supply is output after passing through the LDO chip.

[0014] Furthermore, the filtering unit uses a common-mode inductor for filtering, and the dual-power supply control unit uses an ideal diode to connect two NMOS transistors, which are then connected to the DC-DC conversion unit. The output voltage is selectively controlled by the ideal diode. The higher input voltage can pass through the corresponding NMOS transistor to generate the output voltage, which then enters the DC-DC conversion unit to output the first power supply, and then passes through the LDO chip to output the second power supply.

[0015] Furthermore, the LRMs input / output module also includes a housing, in which the processing unit, input / output unit, communication unit, and power supply unit are integrated inside the housing, and the LRM connector is located at the outer end of the housing; the housing is also provided with a puller and a locking device; the LRMs input / output module is installed in the chassis through the housing, the housing is installed and locked using the puller and the locking device, and interconnection with the LRM socket in the chassis is achieved through the LRM connector.

[0016] Compared with the prior art, this utility model has the following technical features:

[0017] The input / output module proposed in this invention can process multiple input / output IO switch signals, has multiple isolated communication interfaces, dual power supply function and flexible programmability, and is highly versatile, making it very suitable for application in artillery electronic and electrical systems. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the overall design of this utility model;

[0019] Figure 2 This is a schematic diagram of the shell structure in one embodiment of the present invention;

[0020] Figure 3 This is a schematic diagram of the input unit in this utility model;

[0021] Figure 4 This is a schematic diagram of the output unit in this utility model;

[0022] Figure 5 This is a schematic diagram of the communication unit in this utility model;

[0023] Figure 6 This is a schematic diagram of the power supply unit in this utility model. Detailed Implementation

[0024] See Figures 1 to 6 This utility model provides an LRM input / output module, designed with modularity, combination, and serialization in mind; it includes a processing unit, an input / output unit, a communication unit, a power supply unit, and an LRM connector, wherein:

[0025] The processing unit includes an FPGA and an MCU that communicate with each other. The FPGA is connected to the LRM connector through an input / output unit; the MCU is connected to the LRM connector through a CAN interface chip and an isolation interface chip; one end of the power supply unit is connected to the LRM connector, and provides dual power supply to the processing unit after filtering and converting the input voltage.

[0026] The processing unit of this utility model adopts an MCU+FPGA combined framework. The MCU is responsible for processing transactional tasks, and the FPGA is responsible for the logical calculation of signals. Data is transmitted between the MCU and the FPGA via a parallel port or SPI serial bus. The FPGA can also be replaced by a CPLD.

[0027] Various signals in the LRM input / output modules are transmitted to external devices through LRM connectors. All IO digital signals (digital input / output signals), timing signals, and serial communication signals are electrically isolated. Digital input signals are isolated and level-shifted within the input / output unit before entering the FPGA. The MCU processes the digital input signals through communication with the FPGA. Communication between the MCU and FPGA is via SPI, parallel port, and IO signals. Digital output signals are isolated and level-shifted by the FPGA through the internal optocoupler +P-channel MOS of the input / output unit. Timing signals are implemented through FPGA programming, using the transmit and receive enable pins of the isolation interface chip in the communication unit to be configured as either output or input timing signals. The timing settings are implemented internally by the FPGA. External CAN and RS422 / 485 communication are implemented by the MCU and the isolation interface chip and CAN interface chip in the communication unit. The power supply unit is powered externally through the LRM connector in a non-isolated manner, using a TVS protection unit, filtering unit, dual-power supply control unit, DC-DC converter unit, and LDO chip for dual-power supply.

[0028] See Figure 2 The LRMs input / output module of this invention also includes a housing, in which the processing unit, input / output unit, communication unit, and power supply unit are integrated, and the LRM connector is located on the outer end of the housing. The housing also has a puller and a locking device. The LRMs input / output module is installed inside a chassis via the housing, and the puller and locking device are used to secure the housing. Interconnection with the LRM socket in the chassis is achieved through the LRM connector. When this invention is used alone, a suitable mounting structure needs to be added to the outside of the housing, but the style of the LRMs input / output module and the housing does not need to be changed.

[0029] The casing is made of metal and adopts a standardized structural design, enabling mechanical and electrical connection with standard chassis.

[0030] The composition and structure of each part of this utility model will be further described below with reference to the accompanying drawings.

[0031] 1. Input / output unit.

[0032] The input / output unit of this utility model is mainly divided into two parts, namely the input unit and the output unit.

[0033] The input unit uses more than 50 bidirectional optocouplers for isolation to acquire and convert external switch input signals. When the external input voltage is high (12V~40V), it corresponds to the acquisition logic "1" of the processing unit; when the external input voltage is low (0~2)V, it corresponds to the acquisition logic "0" of the processing unit.

[0034] The output unit is implemented using 32 optocouplers + 32 PMOS; the output state is controlled by the processing unit. When the processing unit outputs a low level, the output level of the output unit is configured to be high; when the processing unit outputs a high level, the output level of the output unit is the external power supply level (an external power supply interface is provided, and the output level supports a range of 5V to 40V).

[0035] Figure 3 This is the circuit diagram of the input unit. In this embodiment, it consists of 52 D001 units, each containing a bidirectional optocoupler. The first input terminal IN1 of the bidirectional optocoupler receives external switch input signals. The second input terminal IN2 of the bidirectional optocouplers of a preset number of D001 units uses a common ground. The bidirectional optocoupler is supplied with 3.3V by the power supply unit. The output IN1_c of the bidirectional optocoupler is the switch input signal after optocoupler isolation and level conversion processing. Figure 4 In the example, IN2 of every eight D001 units uses a common ground, and the last four D001 units use a common ground.

[0036] Figure 4 This is the circuit diagram of the output unit, which in this embodiment consists of 32 D002 units. Each D002 unit includes an NPN transistor, an optocoupler, and a P-channel MOSFET. The base of the NPN transistor receives the switching output signal OUT1 from the processing unit, the emitter is grounded, and the collector is connected to the optocoupler. The output of the optocoupler, after passing through the P-channel MOSFET, generates an isolated and level-converted switching output signal OUT1_C. In this circuit, the NPN transistor further reduces the power consumption of the processing unit pins. When the processing unit outputs a high-level switching output signal, the NPN transistor, optocoupler, and P-channel MOSFET are all turned on, outputting OUT1_C. When the processing unit outputs a low-level signal, the P-channel MOSFET is turned off, and the output is in a high-level configuration. A reverse diode is added between the source and ground of the P-channel MOSFET to prevent impact from the downstream inductive load. The drive voltage VCC of the P-channel MOSFET is supplied externally through an LRM connector pin, allowing for flexibility in the output voltage.

[0037] 2. Communication unit.

[0038] The communication unit of this invention includes four-channel timing communication, two-channel CAN communication, and one-channel RS422 / 485 communication. The four-channel timing communication features isolated transmission. The timing signals are programmed via FPGA to be either input or output timing signals. When set as an input timing signal, it cannot be set as an output timing signal. The FPGA in the processing unit configures the input or output state, sets the period and duty cycle of the output timing signal (a square wave signal), and the trigger time of the input timing signal. The two-channel CAN communication features isolated transmission, and the CAN control function is implemented through the MCU of the processing unit. The one-channel RS422 / 485 communication features isolated transmission, and the control function is implemented through the MCU of the processing unit.

[0039] Figure 6 This is the circuit diagram of the communication unit. Time synchronization communication, CAN communication, and RS422 / 485 communication are all isolated through isolation interface chips. The isolation interface chips adopt various forms, including integrated isolation chips, optocoupler isolation, and digital isolators. In particular, the time synchronization output signal adopts differential serial port transmission to ensure that it is not affected by interference and has a long transmission distance. CAN communication and RS422 / 485 communication are implemented using the CAN controller, CAN interface chip, and UART controller on the MCU, and then isolated through the isolation interface chip.

[0040] 3. Power supply unit.

[0041] See Figure 1 The power supply unit includes a TVS protection unit, a filtering unit, a dual-channel power supply control unit, a DC-DC converter unit, and an LDO chip, wherein:

[0042] The power supply unit supports dual input voltages of 22-36V DC. After the dual input voltages are processed by the TVS protection unit for overvoltage protection and the filtering unit, they enter the dual power supply control circuit. After the DC-DC conversion unit converts the voltage level, the first 5V power supply is output, and then the second 3.3V power supply is output after passing through the LDO chip. The dual power supply provides power to different modules, units and chips in the processing unit and input / output unit.

[0043] See Figure 6 In one embodiment of this utility model, the filtering unit uses a common-mode inductor for filtering, and the dual-power supply control unit uses an ideal diode to connect two NMOS transistors, which are then connected to the DC-DC conversion unit. The output voltage is selectively controlled by the ideal diode, meaning that the higher input voltage can pass through the corresponding NMOS transistor to generate an output voltage, which then enters the DC-DC conversion unit to output a 5V voltage, and then passes through the LDO chip to output a 3.3V voltage.

[0044] When the switching control resources of an LRM input / output module are insufficient, an additional identical module needs to be added and installed together in a compatible standardized chassis. The switching resources can be expanded through communication via CAN bus or RS422 / 485.

[0045] In summary, this invention enables the unified consideration and centralized processing of multiple I / O switch signals. By using a standard-sized and interface-compatible metal casing, the circuit board is packaged into a standardized module, achieving standardization, universality, and serialization, while also possessing high mechanical strength. This invention has independent control and processing capabilities; it can be combined with various standard modules to perform specific control functions, or it can independently implement switch signal processing and control functions when installed in other types of electrical enclosures. The use of dual power supplies improves overall reliability.

[0046] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. An LRMs input / output module, characterized in that, It includes a processing unit, an input / output unit, a communication unit, a power supply unit, and an LRM connector, wherein: The processing unit includes an FPGA and an MCU that communicate with each other. The FPGA is connected to the LRM connector through an input / output unit; the MCU is connected to the LRM connector through a CAN interface chip and an isolation interface chip; one end of the power supply unit is connected to the LRM connector, and provides dual power supply to the processing unit after filtering and converting the input voltage.

2. The LRMs input / output module according to claim 1, characterized in that, The input / output unit includes an input unit and an output unit. The input unit uses multiple bidirectional optocouplers for isolation to acquire and convert external switch input signals. The output unit uses multiple optocouplers and PMOS.

3. The LRMs input / output module according to claim 2, characterized in that, The input unit contains multiple D001 units, each of which contains a bidirectional optocoupler. The first input terminal IN1 of the bidirectional optocoupler receives external switch input signals. The second input terminal IN2 of the bidirectional optocouplers of a preset number of D001 units uses a common ground. The output IN1_c of the bidirectional optocoupler is a switch input signal that has been isolated and level-converted by the optocoupler.

4. The LRMs input / output module according to claim 2, characterized in that, The output unit contains multiple D002 units; each D002 unit contains an NPN transistor, an optocoupler, and a P-channel MOS; the base of the NPN transistor is used to receive the switching output signal OUT1 from the processing unit, the emitter is grounded, and the collector is connected to the optocoupler; the output of the optocoupler is converted into an isolated and level-shifted switching output signal OUT1_C after passing through the P-channel MOS; the drive voltage supply for the P-channel MOS is provided externally through the LRM connector pin.

5. The LRMs input / output module according to claim 1, characterized in that, The communication unit includes four-channel timing communication, two-channel CAN communication, and one-channel RS422 / 485 communication. The four-channel timing communication features isolated transmission, and the timing signals are programmed via FPGA to input or output timing signals. The FPGA in the processing unit configures the input or output status, sets the period and duty cycle of the output timing signal, and the trigger time of the input timing signal. The two-channel CAN communication features isolated transmission, and the CAN control function is implemented through the MCU in the processing unit. The one-channel RS422 / 485 communication features isolated transmission, and the control function is implemented through the MCU in the processing unit.

6. The LRMs input / output module according to claim 5, characterized in that, The timing communication, CAN communication, and RS422 / 485 communication of the communication unit are all isolated by an isolation interface chip. The isolation interface chip includes an integrated isolation chip, optocoupler isolation, and digital isolator. The timing output signal adopts differential serial port transmission. The CAN communication and RS422 / 485 communication are implemented by the CAN controller, CAN interface chip, and UART controller on the MCU, and then isolated by the isolation interface chip.

7. The LRMs input / output module according to claim 1, characterized in that, The power supply unit includes a TVS protection unit, a filtering unit, a dual-channel power supply control unit, a DC-DC converter unit, and an LDO chip, wherein: The power supply unit supports dual input voltages. After the dual input voltages are processed by the TVS protection unit for overvoltage protection and the filtering unit, they enter the dual power supply control circuit. After the DC-DC conversion unit converts the voltage level, the first power supply is output, and then the second power supply is output after passing through the LDO chip.

8. The LRMs input / output module according to claim 7, characterized in that, The filtering unit uses a common-mode inductor for filtering. The dual-power supply control unit uses an ideal diode to connect two NMOS transistors, which are then connected to the DC-DC conversion unit. The output voltage is selectively controlled by the ideal diode. The higher input voltage can pass through the corresponding NMOS transistor to generate the output voltage, which then enters the DC-DC conversion unit to output the first power supply, and then passes through the LDO chip to output the second power supply.

9. The LRMs input / output module according to claim 1, characterized in that, The LRMs input / output module also includes a housing, in which the processing unit, input / output unit, communication unit, and power supply unit are integrated inside the housing, and the LRM connector is located at the outer end of the housing; the housing is also provided with a puller and a locking device; the LRMs input / output module is installed in the chassis through the housing, the housing is installed and locked using the puller and locking device, and interconnection with the LRM socket in the chassis is achieved through the LRM connector.

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