Transposed sram cell, memory module, memory and electronic device
By designing cross-coupled inverters and NMOS transistors, row and column read/write functions of transposed SRAM cells were realized, solving the problem of low efficiency of matrix transpose operations in existing SRAM structures and improving storage density and data processing speed.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- SHENZHEN STATE MICROELECTRONICS CO LTD
- Filing Date
- 2025-08-01
- Publication Date
- 2026-06-05
Smart Images
Figure CN224328499U_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of electronic circuit technology, and in particular relates to a transposed SRAM cell, a storage module, a memory, and an electronic device. Background Technology
[0002] Matrix transpose is a fundamental operation in linear algebra that interchanges the rows and columns of a matrix, resulting in a transposed matrix. In the computational process of artificial intelligence (AI) training, backpropagation requires frequent matrix transpose operations, and many mainstream transformation structures also incorporate matrix transpose. Improving the efficiency of matrix transpose implementation is crucial for AI computation.
[0003] However, in common static random-access memory (SRAM) architectures, data read and write operations are typically performed row-by-row. Accessing the original row-based data matrix is highly efficient because its access pattern matches the physical characteristics of SRAM, allowing for fast, direct row-by-row reading. That is, each access only reads the entire row of data in the storage array, not a specific column. If a specific column of information needs to be read in a practical application, each row must be read sequentially, and the required column data extracted. The write operation is similar. This process not only requires additional logic circuitry to temporarily store and filter the target column's data but also significantly increases the time required to complete a full column read. This bottleneck in transpose matrix access speed severely impacts the real-time performance and throughput of applications heavily reliant on matrix operations, such as artificial intelligence, image processing, and scientific computing.
[0004] Therefore, there is an urgent need to provide a transpose SRAM cell to improve the efficiency of matrix transpose operations. Utility Model Content
[0005] The purpose of this application is to provide a transposed SRAM cell, a storage module, a memory, and an electronic device, aiming to solve the problem of low efficiency in matrix transpose operations of related transposed SRAM cells.
[0006] This application provides a transposed SRAM cell, including a first inverter, a second inverter, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor;
[0007] The first inverter and the second inverter are cross-coupled to form a first memory node and a second memory node;
[0008] The first NMOS transistor and the third NMOS transistor are both connected to the first memory node;
[0009] The second NMOS transistor and the fourth NMOS transistor are both connected to the second memory node;
[0010] The first NMOS transistor and the second NMOS transistor are used for row writing and row reading;
[0011] The third and fourth NMOS transistors are used for column writing and column reading.
[0012] In one embodiment, the output of the first inverter, the input of the second inverter, the source of the first NMOS transistor, and the drain of the third NMOS transistor are connected together to form a first memory node;
[0013] The input terminal of the first inverter, the output terminal of the second inverter, the drain of the second NMOS transistor, and the source of the fourth NMOS transistor are connected together to form a second memory node;
[0014] The gates of the first NMOS transistor and the second NMOS transistor are connected to the same row word line;
[0015] The gate of the third NMOS transistor and the gate of the fourth NMOS transistor are connected to the column word line.
[0016] The drain of the first NMOS transistor is connected to the first row bit line;
[0017] The source of the second NMOS transistor is connected to the second row bit line;
[0018] The source of the third NMOS transistor is connected to the first column bit line;
[0019] The drain of the fourth NMOS transistor is connected to the second column bit line.
[0020] In one embodiment, the line character line is connected to the line character line driving circuit and the line position line driving circuit;
[0021] Both the first row bit line and the second row bit line are connected to the first sensitive amplifier.
[0022] In one embodiment, the column word line is connected to the column word line driving circuit;
[0023] Both the first column bit line and the second column bit line are connected to the second sensitive amplifier and the column bit line drive circuit.
[0024] In one embodiment, the first inverter includes a first PMOS transistor and a fifth NMOS transistor;
[0025] The gate of the first PMOS transistor and the gate of the fifth NMOS transistor are connected to form the input terminal of the first inverter, which is connected to the second memory node.
[0026] The drain of the first PMOS transistor and the drain of the fifth NMOS transistor are connected to form the output terminal of the first inverter, which is connected to the first memory node.
[0027] The source of the first PMOS transistor is connected to a high voltage source;
[0028] The source of the fifth NMOS transistor is connected to a low-voltage source.
[0029] In one embodiment, the second inverter includes a second PMOS transistor and a sixth NMOS transistor;
[0030] The gate of the second PMOS transistor and the gate of the sixth NMOS transistor are connected to form the input terminal of the second inverter, which is connected to the first memory node.
[0031] The drain of the second PMOS transistor and the drain of the sixth NMOS transistor are connected to form the output terminal of the second inverter, which is connected to the second memory node.
[0032] The source of the second PMOS transistor is connected to a high-voltage source;
[0033] The source of the sixth NMOS transistor is connected to a low-voltage source.
[0034] This utility model embodiment also provides a storage module, which includes the above-described transposed SRAM cells with m rows and n columns, where m and n are both integers greater than 1.
[0035] In one embodiment, the row word lines of each row of the transposed SRAM cells are shared; the column word lines of each column of the transposed SRAM cells are shared; the first row bit lines of each column of the transposed SRAM cells are shared; the second row bit lines of each column of the transposed SRAM cells are shared; the first column bit lines of each row of the transposed SRAM cells are shared; and the second column bit lines of each row of the transposed SRAM cells are shared.
[0036] This utility model embodiment also provides a memory, the memory comprising L of the above-described memory modules; wherein L is a positive integer;
[0037] The row word lines of the i-th row in the L storage modules are connected together; the column word lines of the j-th column in the L storage modules are connected together; i is a positive integer less than or equal to m, and j is a positive integer less than or equal to n.
[0038] This utility model embodiment also provides an electronic device, which includes the memory described above.
[0039] The beneficial effects of this utility model embodiment compared with the prior art are as follows: a first storage node and a second storage node are formed by cross-coupling the first inverter and the second inverter; a first NMOS transistor and a third NMOS transistor are connected to the first storage node; a second NMOS transistor and a fourth NMOS transistor are connected to the second storage node; the first NMOS transistor and the second NMOS transistor are used for row writing and row reading; the third NMOS transistor and the fourth NMOS transistor are used for column writing and column reading; since the first inverter and the second inverter constitute a bistable unit, the row reading and column reading and writing functions of the transposed SRAM cell are realized by using only the above 4 NMOS transistors in conjunction with the above bistable unit, without having to read each row sequentially and extract the required column data from it, and without having additional logic circuits to temporarily store and filter the data of the target column to be written, which improves the efficiency of matrix transpose operation and simplifies the hardware structure. Attached Figure Description
[0040] To more clearly illustrate the technical utility model in the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0041] Figure 1 A schematic diagram of a transposed SRAM cell provided in an embodiment of this application;
[0042] Figure 2 This is a schematic diagram of another structure of a transposed SRAM cell provided in an embodiment of this application;
[0043] Figure 3 This is a schematic diagram of another structure of a transposed SRAM cell provided in an embodiment of this application;
[0044] Figure 4 A partial example circuit schematic of a transposed SRAM cell provided in an embodiment of this application;
[0045] Figure 5 This is a schematic diagram of the structure of a storage module provided in one embodiment of this application;
[0046] Figure 6 This is a schematic diagram of a memory structure provided in an embodiment of this application. Detailed Implementation
[0047] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.
[0048] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.
[0049] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.
[0050] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.
[0051] Figure 1 A schematic diagram of the transposed SRAM cell provided in a preferred embodiment of this application is shown. For ease of explanation, only the parts relevant to this embodiment are shown, and are described in detail below:
[0052] The aforementioned transposed SRAM cell includes a first inverter U1, a second inverter U2, a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, and a fourth NMOS transistor N4;
[0053] The first inverter U1 and the second inverter U2 are cross-coupled to form the first storage node Q and the second storage node QB;
[0054] The first NMOS transistor N1 and the third NMOS transistor N3 are both connected to the first memory node Q;
[0055] The second NMOS transistor N2 and the fourth NMOS transistor N4 are connected together to the second memory node QB;
[0056] The first NMOS transistor N1 and the second NMOS transistor N2 are used for row writing and row reading;
[0057] The third NMOS transistor N3 and the fourth NMOS transistor N4 are used for column writing and column reading.
[0058] It should be noted that the first inverter U1 and the second inverter U2 constitute a bistable unit.
[0059] The above technical solution achieves row and column read / write functions for transposed SRAM cells using only 4 NMOS transistors, resulting in a simple structure and reliable performance.
[0060] Please continue to refer to this. Figure 1 The output terminal of the first inverter U1, the input terminal of the second inverter U2, the source of the first NMOS transistor N1, and the drain of the third NMOS transistor N3 are connected together to form the first storage node Q.
[0061] The input terminal of the first inverter U1, the output terminal of the second inverter U2, the drain of the second NMOS transistor N2, and the source of the fourth NMOS transistor N4 are connected together to form the second memory node QB.
[0062] The gate of the first NMOS transistor N1 and the gate of the second NMOS transistor N2 are connected to the row word line HWL;
[0063] The gates of the third NMOS transistor N3 and the fourth NMOS transistor N4 are connected to the column word line VWL.
[0064] The drain of the first NMOS transistor N1 is connected to the first row bit line HBL;
[0065] The source of the second NMOS transistor N2 is connected to the second row bit line HBLB;
[0066] The source of the third NMOS transistor N3 is connected to the first column bit line VBL;
[0067] The drain of the fourth NMOS transistor N4 is connected to the second column bit line VBLB.
[0068] It should be noted that the first inverter U1 and the second inverter U2 constitute a bistable unit. During a row-direction write operation, taking writing "1" as an example, the first row bit line HBL is first driven high, and the second row bit line HBLB is driven low. Then, the row word line HWL is pulled high, rewriting the stored value of the bistable unit. During a row-direction read operation, taking reading "1" as an example, both the first row bit line HBL and the second row bit line HBLB are pre-charged high. Then, the first row bit line HBL and the second row bit line HBLB are kept floating, and the row word line HWL is pulled high. The charge on the second row bit line HBLB is discharged through the low-level path in the bistable unit. The first row bit line HBL remains high, and the voltage difference between the second row bit line HBL and HBLB is detected by the first sensitive amplifier, outputting the read result. It is worth emphasizing that during row-direction read and write operations, VWL needs to be kept low.
[0069] During a column-wise write operation, taking writing "1" as an example, first drive the first column bit line VBL to a high level and the second column bit line VBLB to a low level. Then, pull the column word line VWL high to rewrite the stored value of the bistable cell. During a column-wise read operation, taking reading "1" as an example, first precharge both the first column bit line VBL and the second column bit line VBLB to a high level. Then, keep the first column bit line VBL and the second column bit line VBLB floating, pull the column word line VWL high, and discharge the charge on the second column bit line VBLB through the low-level path in the bistable cell. The first column bit line VBL remains high, and the voltage difference between the first column bit line VBL and the second column bit line VBLB will be detected by the sensitive amplifier, outputting the read result. During column-wise read and write operations, the row word line HWL needs to be kept low.
[0070] The above technical solutions improve the efficiency and reliability of matrix transpose operations and simplify the hardware structure.
[0071] like Figure 2 As shown, the row word line HWL is connected to the row word line driving circuit 01; the first row bit line HBL and the second row bit line HBLB are both connected to the first sensitive amplifier 02 and the row bit line driving circuit 03.
[0072] Understandably, the row word line driving circuit is used to select the transposed SRAM cell for read / write operations; the first sensitive amplifier is used to obtain the data stored in the transposed SRAM cell based on the voltage difference between the first row bit line HBL and the second row bit line HBLB; and the row bit line driving circuit is used to provide the driving voltage for the transposed SRAM cell to perform write operations.
[0073] The above technical solution enables the peripheral circuitry for row read / write operations of transposed SRAM cells.
[0074] like Figure 3As shown, the column word line VWL is connected to the column word line drive circuit 04; the first column bit line VBL and the second column bit line VBLB are both connected to the second sensitive amplifier 05 and the column bit line drive circuit 06.
[0075] Understandably, the column word line driving circuit is used to select the transposed SRAM cell for column read / write operations; the second sensitive amplifier is used to obtain the data stored in the transposed SRAM cell based on the voltage difference between the first column bit line VBL and the second column bit line VBLB; and the column bit line driving circuit is used to provide the driving voltage for the transposed SRAM cell to perform column write operations.
[0076] The above technical solution enables the peripheral circuitry for column read / write operations of transposed SRAM cells.
[0077] Figure 4 The illustration shows a partial example circuit structure of a transposed SRAM cell provided in an embodiment of the present invention. For ease of explanation, only the parts relevant to the embodiment of the present invention are shown, and are described in detail below:
[0078] The first inverter U1 includes a first PMOS transistor P1 and a fifth NMOS transistor N5;
[0079] The gate of the first PMOS transistor P1 and the gate of the fifth NMOS transistor N5 are connected to form the input terminal of the first inverter U1, which is connected to the second memory node QB.
[0080] The drain of the first PMOS transistor P1 and the drain of the fifth NMOS transistor N5 are connected to form the output terminal of the first inverter U1, which is connected to the first storage node Q.
[0081] The source of the first PMOS transistor P1 is connected to the high voltage source VDD.
[0082] The source of the fifth NMOS transistor N5 is connected to the low-voltage source VSS.
[0083] The circuit of the first inverter U1 is simple, reliable, and low in cost.
[0084] The second inverter U2 includes a second PMOS transistor P2 and a sixth NMOS transistor N6;
[0085] The gate of the second PMOS transistor P2 and the gate of the sixth NMOS transistor N6 are connected to form the input terminal of the second inverter U2, which is connected to the first memory node Q.
[0086] The drain of the second PMOS transistor P2 and the drain of the sixth NMOS transistor N6 are connected to form the output terminal of the second inverter U2, which is connected to the second memory node QB.
[0087] The source of the second PMOS transistor P2 is connected to the high voltage source VDD;
[0088] The source of the sixth NMOS transistor N6 is connected to the low voltage source VSS.
[0089] The circuit of the second inverter U2 is simple, reliable, and low in cost.
[0090] It is important to note that memory density is a key indicator for measuring performance and cost-effectiveness. With the rapid development of artificial intelligence, big data, and high-performance computing, the demand for data processing speed and storage capacity is growing exponentially. High storage density means that more data can be accommodated in the same physical space, improving system storage efficiency and effectively reducing unit storage costs. In chip design, higher storage density helps reduce chip area and increase integration, thereby achieving a lower power consumption and higher performance computing architecture. Compared to the 12T SRAM cell of a related transposed SRAM cell, the 8T SRAM cell proposed in this application has two-thirds the number of transistors, and the resulting SRAM memory array has a storage density approximately 1.5 times higher (the specific improvement depends on the transistor layout and cannot be given precise data), demonstrating a significant improvement.
[0091] This utility model embodiment also provides a storage module, characterized in that the storage module includes the above-described transposed SRAM units with m rows and n columns, wherein m and n are both integers greater than 1.
[0092] As an example rather than a limitation, such as Figure 5 The storage module shown includes m rows and n columns of the aforementioned transposed SRAM cells, where m and n are both equal to 3. The row word lines HWL of each row of transposed SRAM cells are connected together; the column word lines VWL of each column of transposed SRAM cells are connected together; the first row bit lines HBL of each column of transposed SRAM cells are connected together; the second row bit lines HBLB of each column of transposed SRAM cells are connected together; the first column bit lines VBL of each row of transposed SRAM cells are connected together; and the second column bit lines VBLB of each row of transposed SRAM cells are connected together.
[0093] It is understandable that by raising the row word line HWL of each row of transposed SRAM cells, data read and write operations can be performed on the first row bit line HBL and the second row bit line HBLB of each column of transposed SRAM cells to achieve horizontal read and write functions; by raising the column word line VWL of each column of transposed SRAM cells, data read and write operations can be performed on the first column bit line VBL and the second column bit line VBLB of each row of transposed SRAM cells to achieve vertical read and write functions; thus realizing transpose matrix operations.
[0094] It should be noted that this storage module can be used to store transpose matrices, where the number of rows 'a' of the transpose matrix is equal to m, and the number of columns 'b' of the transpose matrix is equal to n.
[0095] The above technical solution expands the transposed SRAM cell, increases the capacity of the storage module, and enables matrix transpose read / write functionality in the case of multi-bit data.
[0096] This utility model embodiment also provides a memory, characterized in that the memory includes L of the above-mentioned storage modules; wherein L is a positive integer;
[0097] As an example rather than a limitation, such as Figure 6 The memory shown includes L of the above-mentioned memory modules, where L equals 4, the row word lines HWL of the i-th row in the L memory modules are connected together; the column word lines VWL of the j-th column in the L memory modules are connected together; i is a positive integer less than or equal to m, and j is a positive integer less than or equal to n.
[0098] It is understandable that by raising the row word line HWL of each row of transposed SRAM cells in the L storage modules, data read and write operations can be performed on the first row bit line HBL and the second row bit line HBLB of each column of transposed SRAM cells to achieve horizontal read and write functions; by raising the column word line VWL of each column of transposed SRAM cells in the L storage modules, data read and write operations can be performed on the first column bit line VBL and the second column bit line VBLB of each row of transposed SRAM cells to achieve vertical read and write functions; thus, transpose matrix operations are realized.
[0099] It should be noted that in practical applications, such as digital signal processing, L can be equal to bit precision a; thus, the accuracy of information acquisition is improved through the above memory scheme.
[0100] The above technical solution expands the storage module, increases the memory capacity, and enables matrix transpose read / write functionality in the case of multi-bit data.
[0101] This utility model embodiment also provides an electronic device, which includes the memory described above.
[0102] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.
[0103] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.
Claims
1. A transposed SRAM cell, characterized in that, It includes a first inverter, a second inverter, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor; The first inverter and the second inverter are cross-coupled to form a first memory node and a second memory node; The first NMOS transistor and the third NMOS transistor are both connected to the first memory node; The second NMOS transistor and the fourth NMOS transistor are both connected to the second memory node; The first NMOS transistor and the second NMOS transistor are used for row writing and row reading; The third and fourth NMOS transistors are used for column writing and column reading.
2. The transposed SRAM cell as described in claim 1, characterized in that, The output terminal of the first inverter, the input terminal of the second inverter, the source of the first NMOS transistor, and the drain of the third NMOS transistor are connected together to form a first memory node; The input terminal of the first inverter, the output terminal of the second inverter, the drain of the second NMOS transistor, and the source of the fourth NMOS transistor are connected together to form a second memory node; The gates of the first NMOS transistor and the second NMOS transistor are connected to the same row word line; The gate of the third NMOS transistor and the gate of the fourth NMOS transistor are connected to the column word line. The drain of the first NMOS transistor is connected to the first row bit line; The source of the second NMOS transistor is connected to the second row bit line; The source of the third NMOS transistor is connected to the first column bit line; The drain of the fourth NMOS transistor is connected to the second column bit line.
3. The transposed SRAM cell as described in claim 2, characterized in that, The row character line is connected to the row character line driving circuit and the row position line driving circuit; Both the first row bit line and the second row bit line are connected to the first sensitive amplifier.
4. The transposed SRAM cell as described in claim 2, characterized in that, The column word lines are connected to the column word line driving circuit; Both the first column bit line and the second column bit line are connected to the second sensitive amplifier and the column bit line drive circuit.
5. The transposed SRAM cell as described in any one of claims 1 to 4, characterized in that, The first inverter includes a first PMOS transistor and a fifth NMOS transistor; The gate of the first PMOS transistor and the gate of the fifth NMOS transistor are connected to form the input terminal of the first inverter, which is connected to the second memory node. The drain of the first PMOS transistor and the drain of the fifth NMOS transistor are connected to form the output terminal of the first inverter, which is connected to the first memory node. The source of the first PMOS transistor is connected to a high voltage source; The source of the fifth NMOS transistor is connected to a low-voltage source.
6. The transposed SRAM cell as described in any one of claims 1 to 4, characterized in that, The second inverter includes a second PMOS transistor and a sixth NMOS transistor; The gate of the second PMOS transistor and the gate of the sixth NMOS transistor are connected to form the input terminal of the second inverter, which is connected to the first memory node. The drain of the second PMOS transistor and the drain of the sixth NMOS transistor are connected to form the output terminal of the second inverter, which is connected to the second memory node. The source of the second PMOS transistor is connected to a high-voltage source; The source of the sixth NMOS transistor is connected to a low-voltage source.
7. A storage module, characterized in that, The storage module comprises m rows and n columns of transposed SRAM cells as described in any one of claims 1 to 6, wherein m and n are both integers greater than 1.
8. The storage module as described in claim 7, characterized in that, The row word lines of each row of the transposed SRAM cells are connected together; the column word lines of each column of the transposed SRAM cells are connected together; the first row bit lines of each column of the transposed SRAM cells are connected together; the second row bit lines of each column of the transposed SRAM cells are connected together; the first column bit lines of each row of the transposed SRAM cells are connected together; and the second column bit lines of each row of the transposed SRAM cells are connected together.
9. A memory, characterized in that, The memory includes L storage modules as described in any one of claims 7 to 8; wherein L is a positive integer; The row word lines of the i-th row in the L storage modules are connected together; the column word lines of the j-th column in the L storage modules are connected together; i is a positive integer less than or equal to m, and j is a positive integer less than or equal to n.
10. An electronic device, characterized in that, The electronic device includes the memory as described in claim 9.