An integrated high-voltage starting device and high-voltage starting circuit

Abstract

The utility model relates to the technical field of switching power supply, especially to an integrated high-voltage starting device and high-voltage starting circuit. Wherein, the integrated high-voltage starting device comprises: JFET pipe M3, first MOS pipe M1 and second MOS pipe M2, the drain electrode of JFET pipe M3, the drain electrode of first MOS pipe M1 and the drain electrode of second MOS pipe M2 are connected VCC end, the gate of JFET pipe M3 is grounded, and the gate of first MOS pipe M1 and the gate of second MOS pipe M2 are connected. The parasitic capacitance of JFET pipe M3 is smaller than MOS device, and the response speed is faster, so that the capacitor C1 can be quickly recharged. At the same time, the starting circuit structure of integrated high-voltage starting device is completed after power-on, and the leakage current size is equivalent to the conventional starting circuit structure, so that no additional power consumption is caused.

Description

Technical Field

[0001] This utility model relates to the field of switching power supply technology, and in particular to an integrated high-voltage starting device and a high-voltage starting circuit. Background Technology

[0002] Currently, switching power supply circuits utilize PWM (Pulse Width Modulation) control chips to control the power transistors to turn on or off, thereby achieving the required voltage or current frequency for subsequent stages, or maintaining a constant voltage in the capacitors of subsequent stages. The PWM control chip typically integrates a startup circuit containing high-voltage components to complete the initial startup upon power-on, converting the higher external input voltage into the lower operating voltage required by the PWM chip internally.

[0003] like Figure 1 As shown, the part enclosed by the dashed box is a high-voltage starting device or a high-voltage starting part that can be manufactured using the same process. It is manufactured separately and then connected to the remaining circuit through a package and wire bonding.

[0004] In this circuit structure, MOSFETs M1, M2, and M3 are power MOSFETs of the same type but different areas. The resistor HR is a high-value resistor with a resistance range of 20~40MΩ. The circuit operates as follows:

[0005] (1) During the power-on process of VCC, when the voltage difference Vgs between the gate and source terminals of MOS transistor M3 is greater than the threshold voltage Vth of M3, MOS transistor M3 is in the conducting state, and the current flowing through it charges the bypass capacitor C1.

[0006] (2) The voltage value on the bypass capacitor C1 is compared with the Ref signal generated by the internal circuit of the PWM controller through a voltage comparator. When the voltage value on the bypass capacitor C1 reaches a certain voltage, the voltage comparator outputs a high level, turning on the MOSFET M4. Consequently, the gate voltage of the MOSFET M1 is pulled to approximately GND, and the MOSFET M1 turns off, completing the power-on process. After the bypass capacitor C1 is fully charged, there is a leakage current loop from VCC to ground through resistors HR and R2:

[0007]

[0008] (3) When the voltage on the bypass capacitor C1 is lower than a certain threshold, the voltage comparator outputs a low level to turn off the MOS transistor M4. Then the MOS transistor M1 reaches the conduction condition to charge the bypass capacitor C1. This is a repetitive process.

[0009] Figure 1Because of the presence of resistor HR, the RC circuit on the gate of MOSFET M3 causes a significant delay in the power-on process. Furthermore, after power-on, VCC is connected to ground via resistor HR and R2, resulting in substantial static leakage current loss. Increasing the resistance of HR to reduce static leakage current loss (R2 is located within the PWM controller and cannot be made very large) requires accepting a significant power-on delay. Therefore, this circuit fails to reduce the power-on delay while ensuring adequate static leakage current loss. Summary of the Invention

[0010] This invention provides an integrated high-voltage starting device and high-voltage starting circuit to solve the technical problems mentioned in the background art, and can reduce power-on delay without increasing static leakage loss.

[0011] One technical solution of this utility model is as follows: An integrated high-voltage starting device includes: a JFET M3, a first MOS transistor M1, and a second MOS transistor M2. The drain of the JFET M3, the drain of the first MOS transistor M1, and the drain of the second MOS transistor M2 are connected to the VCC terminal. The gate of the JFET M3 is grounded, and the gate of the first MOS transistor M1 and the gate of the second MOS transistor M2 are connected.

[0012] Another technical solution of this utility model is as follows: a high-voltage starting circuit integrating a high-voltage starting device, comprising: a high-voltage starting peripheral circuit and the above-mentioned integrated high-voltage starting device, wherein the high-voltage starting peripheral circuit comprises: a voltage comparator, a power transistor control module and a capacitor C1, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fourth MOSFET M4, a fifth MOSFET M5, and a sixth MOSFET M6.

[0013] The source of JFET M3 is connected to one end of the second resistor R2 and one end of the third resistor R3. The other end of the second resistor R2 is connected to the drain and gate of the fourth MOSFET M4, the gate of the fifth MOSFET M5, and one end of the fourth resistor R4. The source of the fourth MOSFET M4, the source of the fifth MOSFET M5, the first input terminal of the power transistor control module, the first input terminal of the voltage comparator, and one end of the capacitor C1 are connected to the VDD terminal. The other end of the fourth resistor R4 is connected to the drain of the sixth MOSFET M6. The gate of the sixth MOSFET M6 is connected to the output terminal of the voltage comparator. The second input terminal of the voltage comparator is connected to the reference voltage REF. The gates of the first MOSFET M1 and the second MOSFET M2 are connected to the output terminal of the power transistor control module. The second input terminal of the power transistor control module is connected to the source of the second MOSFET M2 and one end of the first resistor R1. The source of the first MOSFET M1 is connected to the output terminal. The source of the sixth MOSFET M6, the other end of the capacitor C1, and the other end of the first resistor R1 are grounded.

[0014] Furthermore, the power transistor control module includes: a power transistor control logic circuit and an overcurrent detection circuit. The first input terminal of the power transistor control logic circuit is connected to the VDD terminal, and the output terminal is connected to the gate of the first MOS transistor M1 and the gate of the second MOS transistor M2. The second input terminal is connected to the output terminal of the overcurrent detection circuit, and the input terminal of the overcurrent detection circuit is connected to the source of the second MOS transistor M2 and one end of the first resistor R1.

[0015] Furthermore, the first MOSFET M1 and the second MOSFET M2 are N-type power transistors.

[0016] Furthermore, the fourth MOSFET M4, the fifth MOSFET M5, and the sixth MOSFET M6 are N-type switching transistors.

[0017] Furthermore, the substrates of the fourth MOS transistor M4, the fifth MOS transistor M5, and the sixth MOS transistor M6 are all grounded.

[0018] Furthermore, the JFET transistor M3 is a startup transistor.

[0019] The beneficial effects of this utility model are:

[0020] JFET M3, first MOSFET M1, and second MOSFET M2 are fabricated simultaneously, eliminating the need for additional photolithography and high-resistivity ion implantation. The absence of high-resistivity resistors reduces the overall device area and saves manufacturing costs.

[0021] The parasitic capacitance of JFET M3 is smaller than that of MOS devices, resulting in a faster response speed and quicker charging of capacitor C1. At the same time, after power-on, the leakage current of this startup circuit structure is comparable to that of startup circuit structures in the background technology, without causing additional power consumption.

[0022] The gate of JFET M3 is connected to the lowest potential, and the turn-on and turn-off are achieved by the potential difference between the source and gate of JFET M3, without the need for additional gate control circuitry for JFET M3. Attached Figure Description

[0023] Figure 1 This is a structural diagram of the high-voltage starting circuit mentioned in the background art.

[0024] Figure 2 This is a schematic diagram of the integrated high-voltage starting device of this utility model.

[0025] Figure 3 This is a cross-sectional structural diagram of the integrated high-voltage starting device in this utility model.

[0026] Figure 4 The circuit diagram provided for the high-voltage starting circuit of the integrated high-voltage starting device in this utility model.

[0027] Figure 5 This is a cross-sectional view corresponding to the manufacturing method S10 of the integrated high-voltage starting device in this utility model.

[0028] Figure 6 This is one of the cross-sectional views corresponding to the manufacturing method S20 of the integrated high-voltage starting device in this utility model.

[0029] Figure 7 The second cross-sectional view corresponds to the manufacturing method S20 of the integrated high-voltage starting device in this utility model.

[0030] Figure 8 This is a cross-sectional view corresponding to the manufacturing method S30 of the integrated high-voltage starting device in this utility model.

[0031] Figure 9 This is one of the cross-sectional views corresponding to the manufacturing method S40 of the integrated high-voltage starting device in this utility model.

[0032] Figure 10 The second cross-sectional view corresponding to the integrated high-voltage starting device fabrication method S40.

[0033] Figure 11 One of the cross-sectional views corresponding to the integrated high-voltage starting device fabrication method S50.

[0034] Figure 12 The second cross-sectional view corresponding to the integrated high-voltage starting device fabrication method S50.

[0035] Figure 13 One of the cross-sectional views corresponding to the integrated high-voltage starting device fabrication method S60.

[0036] Figure 14 The second cross-sectional view corresponding to the integrated high-voltage starting device fabrication method S60.

[0037] Figure 15 A cross-sectional view corresponding to the integrated high-voltage starting device fabrication method S70.

[0038] Figure 16 A cross-sectional view corresponding to the S80 method for fabricating integrated high-voltage starting devices.

[0039] Figure 17 A cross-sectional view corresponding to the S90 method for fabricating integrated high-voltage starting devices.

[0040] Figure 18 This is a cross-sectional view of the integrated high-voltage starting device fabrication method S100.

[0041] Figure 19 One of the cross-sectional views corresponding to the integrated high-voltage starting device fabrication method S110.

[0042] Figure 20 The second cross-sectional view corresponding to the integrated high-voltage starting device fabrication method S110.

[0043] Figure 21 A cross-sectional view corresponding to the integrated high-voltage starting device fabrication method S120.

[0044] Figure 22 One of the cross-sectional views corresponding to the integrated high-voltage starting device fabrication method S130.

[0045] Figure 23 The second cross-sectional view corresponding to the integrated high-voltage starting device fabrication method S130.

[0046] Figure 24 A cross-sectional view corresponding to the integrated high-voltage starting device fabrication method S140.

[0047] Figure reference numerals: 1. N-type substrate; 2. N-type epitaxial layer; 3. First oxide layer; 4. Photoresist; 5. Termination ring; 6. Second oxide layer; 7. Barrier oxide layer; 8. Active region; 9. Gate oxide layer; 10. Gate polystyrene; 11. P-type body region; 12. N-type heavily doped region; 13. Insulating layer; 14. P-type heavily doped region; 15. Dielectric isolation layer; 16. Metal dielectric. Detailed Implementation

[0048] It should be noted that, where there is no conflict, the embodiments and features in the embodiments of this utility model can be combined with each other. The present utility model will now be described in detail with reference to the accompanying drawings and embodiments.

[0049] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. The described embodiments are merely some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of the present invention.

[0050] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this utility model are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of the utility model described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or device that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.

[0051] In one technical solution of this utility model, Figure 2 This is a schematic diagram of an integrated high-voltage starting device provided according to this technical solution. Figure 3 According to the cross-sectional diagram provided by the integrated high-voltage starting device, such as Figure 2 and Figure 3 As shown, this utility model includes: a JFET M3, a first MOS transistor M1, and a second MOS transistor M2. The drains of the JFET M3, the first MOS transistor M1, and the second MOS transistor M2 are connected to the VCC terminal. The gate of the JFET M3 is grounded, and the gates of the first MOS transistor M1 and the second MOS transistor M2 are connected.

[0052] In the second technical solution of this utility model, Figure 4 This is a circuit diagram provided by a high-voltage starting circuit integrating a high-voltage starting device according to the present technical solution, such as... Figure 4 As shown, this technical solution includes:

[0053] The high-voltage starting peripheral circuit and the aforementioned integrated high-voltage starting device, wherein the high-voltage starting peripheral circuit includes: a voltage comparator, a power transistor control module and capacitor C1, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fourth MOSFET M4, a fifth MOSFET M5, and a sixth MOSFET M6.

[0054] The source of the JFET M3 is connected to one end of the second resistor R2 and one end of the third resistor R3. The other end of the second resistor R2 is connected to the drain and gate of the fourth MOSFET M4, the gate of the fifth MOSFET M5, and one end of the fourth resistor R4. The source of the fourth MOSFET M4, the source of the fifth MOSFET M5, the first input terminal of the power transistor control module, the first input terminal of the voltage comparator, and one end of the capacitor C1 are connected to the VDD terminal. The other end of the fourth resistor R4 is connected to the drain of the sixth MOSFET M6. The gate of the sixth MOSFET M6 is connected to the output terminal of the voltage comparator. The second input terminal of the voltage comparator is connected to the reference voltage REF. The gate of the first MOSFET M1 and the gate of the second MOSFET M2 are connected to the output terminal of the power transistor control module. The second input terminal of the power transistor control module is connected to the source of the second MOSFET M2 and one end of the first resistor R1. The source of the first MOSFET M1 is connected to the output terminal. The gate of the JFET M3, the source of the sixth MOSFET M6, the other end of the capacitor C1, and the other end of the first resistor R1 are grounded.

[0055] The power transistor control module includes a power transistor control logic circuit and an overcurrent detection circuit. The first input terminal of the power transistor control logic circuit is connected to the VDD terminal, and the output terminal is connected to the gate of the first MOSFET M1 and the gate of the second MOSFET M2. The second input terminal is connected to the output terminal of the overcurrent detection circuit, and the input terminal of the overcurrent detection circuit is connected to the source of the second MOSFET M2 and one end of the first resistor R1. It should be noted that both the power transistor control logic circuit and the overcurrent detection circuit are the same as those mentioned in the background section, representing conventional techniques in this field; their specific structures will not be described in detail here.

[0056] In one embodiment of this technical solution, the first MOS transistor M1 and the second MOS transistor M2 are N-type power transistors.

[0057] In one embodiment of this technical solution, the fourth MOS transistor M4, the fifth MOS transistor M5, and the sixth MOS transistor M6 are N-type switching transistors.

[0058] In one embodiment of this technical solution, the substrates of the fourth MOS transistor M4, the fifth MOS transistor M5, and the sixth MOS transistor M6 are all grounded.

[0059] In one embodiment of this technical solution, the JFET transistor M3 is a startup transistor.

[0060] It should be noted that the high-voltage starting circuit integrating the high-voltage starting device in this embodiment is only a small part of the internal circuit of the entire PWM controller. Figure 2The other internal circuits of the PWM controller are not shown; only the parts related to the high-voltage startup circuit with the integrated high-voltage startup device are shown. For other functional chips, in scenarios involving the conversion of high voltage to low voltage during startup, the high-voltage startup circuit with the integrated high-voltage startup device proposed in this invention can also be used.

[0061] The working process of this utility model is as follows:

[0062] Figure 2 JFET M3 is normally on when not powered. The first MOSFET M1 and the second MOSFET M2 are both N-type power transistors, of the same type but different sizes. More specifically, both the first MOSFET M1 and the second MOSFET M2 are two conventional VDMOS transistors; the first MOSFET M1 is the main power transistor, and the second MOSFET M2 is the sampling transistor. JFET M3, the first MOSFET M1, and the second MOSFET M2 are all manufactured simultaneously using the same process flow.

[0063] 1) During VCC power-on, JFET M3 is initially in a normally on state, charging the gates of MOSFETs M4 and M5 through the second resistor R2. When the gate voltage reaches the threshold voltage of MOSFETs M4 and M5, they turn on. Subsequently, VCC charges capacitor C1 through two branches, R2-M4 and R3-M5. These two branches form a current mirror circuit. The R3-M5 branch is used for power supply, while the R2-M4 branch mainly prevents burnout caused by excessive voltage changes in the R3-M5 branch.

[0064] 2) The voltage value on capacitor C1 is compared with the Ref signal generated by the internal circuit of the PWM controller through a voltage comparator. When the voltage value on capacitor C1 reaches a certain voltage, the voltage comparator outputs a high level, and the sixth MOSFET M6 is turned on. The gates of the fourth MOSFET M4 and the fifth MOSFET M5 are then pulled to ground potential, and the fourth MOSFET M4 and the fifth MOSFET M5 are turned off, and the charging circuit of capacitor C1 is also turned off.

[0065] 3) The parasitic capacitance at node A will be quickly charged to the pinch-off voltage V of JFET M3. pinch-off JFET M3 carries most of the voltage drop across VCC. At this time, there is a leakage current from node A to ground.

[0066]

[0067] 4) When the voltage across capacitor C1 is lower than a certain value, the voltage comparator outputs a low level, the sixth MOSFET M6 is turned off, and then steps 1), 2), and 3) are repeated.

[0068] for, Figure 1 The integration of resistor HR in the high-voltage startup device section of the circuit structure requires an additional high-resistance injection layer. Furthermore, achieving a large resistance value while maintaining resistance uniformity necessitates a significant increase in layout area. For Figure 2 In the circuit structure, M3, as a JFET device, has a smaller parasitic capacitance than a MOS device, resulting in a faster response speed. It can quickly charge capacitor C1. In addition, M3 has the same layer as M1 and M2, so there is no need to add an extra high-resistance injection process. It also reduces the layout area and saves more manufacturing costs.

[0069] To further illustrate the specific manufacturing process of the integrated high-voltage starting device, Figures 5-24 It provides a breakdown diagram of the process flow, such as... Figures 5-24 As shown, this method includes:

[0070] S10: As Figure 5 As shown, an N-type substrate 1 is provided, an N-type epitaxial layer 2 is formed on the surface of the N-type substrate 1, and a first oxide layer 3 is grown on the surface of the N-type epitaxial layer 2, wherein the thickness of the first oxide layer 3 is 3500 Å.

[0071] S20: As Figure 6 and Figure 7 As shown, photoresist 4 is deposited on the surface of the first oxide layer 3, and a terminal ring implantation window is developed and etched to implant P-type ions into the N-type epitaxial layer 2 through the terminal ring implantation window.

[0072] S30: As Figure 8 As shown, the photoresist 4 is removed, and a second oxide layer 6 is grown on the surface of the first oxide layer 3 and the N-type epitaxial layer 2. The thickness of the second oxide layer 6 is 18000 Å. Since the thickness of the second oxide layer 6 is greater than that of the first oxide layer 3, the second oxide layer 6 will cover the first oxide layer 3 to form a protective layer, and form a terminal ring 5 for the P-type ion pusher implanted into the N-type epitaxial layer 2.

[0073] S40: As Figure 9 and Figure 10 As shown, photoresist 4 is deposited on the surface of the second oxide layer 6, the active region implantation window is developed and etched, the photoresist 4 is removed, and an implantation barrier oxide layer 7 is grown on the surface of the N-type epitaxial layer 2 within the active region implantation window, wherein the thickness of the barrier oxide layer 7 is 500 Å.

[0074] S50: such as Figure 11 and Figure 12 As shown, N-type ions are implanted into the N-type epitaxial layer 2 through the active region implantation window and the active region 8 is activated by push-well. The implantation barrier oxide layer 7 is removed by etching, wherein the active region is N-type.

[0075] S60: As Figure 13 and Figure 14 As shown, a gate oxide layer 9 is grown on the surface of the N-type epitaxial layer 2 corresponding to the active region 8. The thickness of the gate oxide layer 9 is 1100 Å. Polysilicon is deposited on the surface of the gate oxide layer 9 and the second oxide layer 6, and N-type ions are implanted on the surface of the polysilicon to form a gate polysilicon strip 10. The gate polysilicon strip 10 is a heavily doped N-type polysilicon.

[0076] S70: As Figure 15 As shown, photoresist 4 is deposited on the surface of the gate polycrystal 10, the gate polycrystal 10 is developed and etched to form the gate and gate interconnect regions, and the gate oxide layer 9 is etched and thinned to serve as a barrier layer for P-type body region implantation. It should be noted that since the active regions have the same type as the substrate, they will not be shown in the following figures. At the same time, the portion of the active region that overlaps with the P-type body region will be compensated by the P-type body region.

[0077] S80: such as Figure 16 As shown, the photoresist 4 is removed, and photoresist 4 is deposited on the surface of the N-type epitaxial layer 2 corresponding to the gate polysilicon strip 10, the second oxide layer 6, and the active region 8. The P-type body region implantation window is then developed and etched.

[0078] S90: such as Figure 17 As shown, P-type ions are injected into the active region through the P-type body region injection window and the P-type body region 11 is activated by push-in, and the photoresist 4 is removed.

[0079] S100: As Figure 18 As shown, photoresist 4 is deposited on the N-type epitaxial layer 2 corresponding to the gate polycrystalline strip 10, the second oxide layer 6, and the active region 8. The N-type heavily doped implantation window is developed and etched out. N-type ions are implanted into the active region through the N-type heavily doped implantation window to form the N-type heavily doped region 12.

[0080] S110: As Figure 19 and Figure 20 As shown, an insulating layer 13 is deposited on the gate polysilicon strip 10, the second oxide layer 6, and the surface of the active region. Photoresist 4 is deposited on the surface of the insulating layer 13. Etching is performed at the corresponding positions of the P-type body region to form a P-type heavily doped implantation window. P-type ions are implanted into the P-type body region through the P-type heavily doped implantation window to form a P-type heavily doped region 14. The insulating layer 13 is made of TEOS (tetraethyl orthosilicate) and has a thickness of 1500 Å.

[0081] S120: As Figure 21As shown, photoresist 4 is removed, and a dielectric isolation layer 15 is deposited on the surface of the insulating layer 13. Photoresist 4 is then deposited on the surface of the dielectric isolation layer 15, the contact holes are developed and etched, and the photoresist 4 is removed. The dielectric isolation layer 15 is made of BPSG (Borophosphosilicate Glass) with a thickness of 10000 Å.

[0082] S130: As Figure 22 and Figure 23 As shown, a metal dielectric 16 is sputtered on the surface of the dielectric isolation layer 15 and inside the contact hole. The metal dielectric 16 is aluminum with a thickness of 40000 Å. Photoresist 4 is deposited on the surface of the metal dielectric 16. The electrode lead-out area is developed and etched, and the photoresist 4 is removed.

[0083] S140: As Figure 24 As shown, the N-type substrate 1 is thinned and the back side of the N-type substrate 1 is metallized to form a drain, thus completing the fabrication of the integrated high-voltage start-up device.

[0084] Among them, the N-type ion mentioned above is the phosphorus ion, and the P-type ion is the boron ion.

[0085] Finally, the integrated high-voltage starting device is connected to the high-voltage starting peripheral circuit through wire bonding to form the high-voltage starting circuit of any of the integrated high-voltage starting devices described above.

[0086] Finally, it should be noted that the above specific embodiments are only used to illustrate the technical solution of this utility model and not to limit it. Although this utility model has been described in detail with reference to examples, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solution of this utility model without departing from the spirit and scope of the technical solution of this utility model, and all such modifications and substitutions should be covered within the scope of the claims of this utility model.

Claims

1. An integrated high-voltage starting device, characterized in that, include: JFET M3, first MOS transistor M1, and second MOS transistor M2 are connected to the VCC terminal. The gate of JFET M3 is grounded, and the gate of first MOS transistor M1 is connected to the gate of second MOS transistor M2.

2. A high-voltage starting circuit integrating a high-voltage starting device, characterized in that, include: The high-voltage starting peripheral circuit and the integrated high-voltage starting device according to claim 1, wherein the high-voltage starting peripheral circuit includes: a voltage comparator, a power transistor control module and a capacitor C1, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fourth MOSFET M4, a fifth MOSFET M5, and a sixth MOSFET M6; The source of JFET M3 is connected to one end of the second resistor R2 and one end of the third resistor R3. The other end of the second resistor R2 is connected to the drain and gate of the fourth MOSFET M4, the gate of the fifth MOSFET M5, and one end of the fourth resistor R4. The source of the fourth MOSFET M4, the source of the fifth MOSFET M5, the first input terminal of the power transistor control module, the first input terminal of the voltage comparator, and one end of the capacitor C1 are connected to the VDD terminal. The other end of the fourth resistor R4 is connected to the drain of the sixth MOSFET M6. The gate of the sixth MOSFET M6 is connected to the output terminal of the voltage comparator. The second input terminal of the voltage comparator is connected to the reference voltage REF. The gates of the first MOSFET M1 and the second MOSFET M2 are connected to the output terminal of the power transistor control module. The second input terminal of the power transistor control module is connected to the source of the second MOSFET M2 and one end of the first resistor R1. The source of the first MOSFET M1 is connected to the output terminal. The source of the sixth MOSFET M6, the other end of the capacitor C1, and the other end of the first resistor R1 are grounded.

3. The high-voltage starting circuit with integrated high-voltage starting device as described in claim 2, characterized in that, The power transistor control module includes a power transistor control logic circuit and an overcurrent detection circuit. The first input terminal of the power transistor control logic circuit is connected to the VDD terminal, and the output terminal is connected to the gate of the first MOSFET M1 and the gate of the second MOSFET M2. The second input terminal is connected to the output terminal of the overcurrent detection circuit. The input terminal of the overcurrent detection circuit is connected to the source of the second MOSFET M2 and one end of the first resistor R1.

4. The high-voltage starting circuit with integrated high-voltage starting device as described in claim 2, characterized in that, The first MOSFET M1 and the second MOSFET M2 are N-type power transistors.

5. The high-voltage starting circuit with integrated high-voltage starting device as described in claim 2, characterized in that, The fourth MOSFET M4, the fifth MOSFET M5, and the sixth MOSFET M6 are N-type switching transistors.

6. The high-voltage starting circuit of the integrated high-voltage starting device as described in claim 4 or 5, characterized in that, The substrates of the fourth MOS transistor M4, the fifth MOS transistor M5, and the sixth MOS transistor M6 are all grounded.

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