A low gate charge and low on-resistance trench gate silicon carbide VDMOS
By constructing a dual floating gate structure and an interleaved source region design in silicon carbide VDMOS devices, the problem of balancing gate charge and on-resistance under high voltage is solved, improving switching speed and withstand voltage, and reducing losses.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- GLOBAL POWER TECH CO LTD
- Filing Date
- 2025-05-08
- Publication Date
- 2026-06-05
AI Technical Summary
Existing silicon carbide VDMOS devices struggle to achieve a balance between low gate charge and low on-resistance at high voltages, affecting the device's switching speed and voltage withstand capability.
By redesigning the P-type source region and P-type well region, a dual floating gate structure is constructed to reduce the doping concentration of the P-type well region. The first P-type source region, the Schottky metal layer and the second P-type source region are alternately arranged below the source metal layer to form a charge-balanced conductive channel and shield the gate drain capacitance.
This achieves low on-resistance and low gate charge, improving the switching speed and voltage withstand capability of the device, and reducing drive loss and freewheeling loss of the body diode.
Smart Images
Figure CN224329834U_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a trench gate silicon carbide VDMOS with low gate charge and low on-resistance. Background Technology
[0002] Silicon carbide VDMOS devices, due to their wide bandgap characteristics, naturally possess the advantages of low gate charge and high switching speed compared to SiVDMOS devices. However, their wide bandgap characteristics also mean that the device can only be fully turned on at a higher voltage. Therefore, there is still room to further reduce the gate charge, which can further improve the switching speed of the device. Utility Model Content
[0003] The technical problem to be solved by this utility model is to provide a trench gate silicon carbide VDMOS with low gate charge and low on-resistance. By redesigning the P-type source region and P-type well region of the device, the doping concentration of the P-type well region is reduced while ensuring the voltage withstand characteristics of the device, thereby reducing the gate charge of the device.
[0004] This invention provides a low-gate-charge, low-on-resistance trench-gate silicon carbide VDMOS, comprising:
[0005] silicon carbide substrate;
[0006] A drift layer, the lower side of which is connected to the upper side of the silicon carbide substrate; the drift layer has a protrusion and a groove, the groove being located within the protrusion; the depth of the groove is greater than the thickness of the protrusion;
[0007] A first P-type source region, the lower side of which is connected to the upper side of the drift layer;
[0008] A Schottky metal layer, wherein the lower side of the Schottky metal layer is connected to the upper side of the drift layer, and the outer side of the Schottky metal layer is connected to the inner side of the first P-type source region;
[0009] The second P-type source region has its lower side connected to the upper side of the drift layer and its outer side connected to the inner side of the Schottky metal layer. The second P-type source region is provided with a first P-type well region, an N-type source region and a second P-type well region. The N-type source region is located between the first P-type well region and the second P-type well region. The inner side of the second P-type source region and the inner side of the second P-type well region are both connected to the outer side of the protrusion.
[0010] An insulating dielectric layer is provided at its lower part within the groove. The insulating dielectric layer is connected to the upper side of the N-type source region, the upper side of the second P-type well region, and the upper side of the protrusion. A first floating gate and a second floating gate are provided within the insulating dielectric layer, with the first floating gate located directly below the second floating gate. The insulating dielectric layer is provided with grooves.
[0011] A gate metal layer, wherein the gate metal layer is disposed within the trench;
[0012] A source metal layer, wherein the source metal layer is respectively connected to the first P-type source region, the Schottky metal layer, the second P-type source region and the first P-type well region;
[0013] And a drain metal layer, which is connected to the lower side of the silicon carbide substrate.
[0014] The advantages of this utility model are:
[0015] I. This utility model constructs a double floating gate structure. The double floating gate structure is distributed inside the device. When a positive voltage is applied to the gate of the device and it is turned on, a conductive channel with a higher electron concentration is formed on both sides of the floating gate through the charge balance effect, thereby reducing the on-resistance of the device and achieving low on-resistance characteristics.
[0016] 2. The dual floating gate structure can shield the capacitance effect from the gate metal layer to the drain metal layer, thereby reducing the gate-drain capacitance of the device, i.e., the Miller capacitance, which can effectively reduce the gate charge of the device, improve the switching speed of the device, and reduce the drive loss.
[0017] Third, by setting a first P-type well region, an N-type source region, and a second P-type well region on the second P-type source region, the diffusion rate of the space charge region in the first P-type well region and the second P-type well region can be reduced under the condition that the drain is subjected to a large voltage, thereby improving the device's withstand voltage capability.
[0018] Fourth, while ensuring the drain breakdown voltage of the device, reducing the doping concentration of the first P-type well region and the second P-type well region can reduce the amount of charge required for the gate control conductive channel, reduce the gate charge of the device, and improve the switching speed of the device.
[0019] Fifth, a structure in which the first P-type source region, the Schottky metal layer, and the second P-type source region are interleaved is constructed under the source metal layer of the device, which can reduce the freewheeling loss of the body diode. Attached Figure Description
[0020] The present invention will be further described below with reference to the accompanying drawings and embodiments.
[0021] Figure 1 This is a schematic diagram of a trench gate silicon carbide VDMOS with low gate charge and low on-resistance according to this utility model.
[0022] Figure 2 This is a cross-sectional view of the process of a trench gate silicon carbide VDMOS with low gate charge and low on-resistance according to the present invention. Figure 1 .
[0023] Figure 3 This is a cross-sectional view of the process of a trench gate silicon carbide VDMOS with low gate charge and low on-resistance according to the present invention. Figure 2 .
[0024] Figure 4 This is a cross-sectional view of the process of a trench gate silicon carbide VDMOS with low gate charge and low on-resistance according to the present invention. Figure 3 .
[0025] Figure 5 This is a cross-sectional view of the process of a trench gate silicon carbide VDMOS with low gate charge and low on-resistance according to the present invention. Figure 4 .
[0026] Figure 6 This is a cross-sectional view of the process of a trench gate silicon carbide VDMOS with low gate charge and low on-resistance according to the present invention. Figure 5 .
[0027] Figure 7 This is a cross-sectional view of the process of a trench gate silicon carbide VDMOS with low gate charge and low on-resistance according to the present invention. Figure 6 .
[0028] Figure 8 This is a cross-sectional view of the process of a trench gate silicon carbide VDMOS with low gate charge and low on-resistance according to the present invention. Figure 7 .
[0029] Figure 9 This is a cross-sectional view of the process of a trench gate silicon carbide VDMOS with low gate charge and low on-resistance according to the present invention. Figure 8 .
[0030] Figure 10 This is a cross-sectional view of the process of a trench gate silicon carbide VDMOS with low gate charge and low on-resistance according to the present invention. Figure 9 .
[0031] Figure 11 This is a cross-sectional view of the process of a trench gate silicon carbide VDMOS with low gate charge and low on-resistance according to the present invention. Figure 10 .
[0032] Figure 12 This is a cross-sectional view of the process of a trench gate silicon carbide VDMOS with low gate charge and low on-resistance according to the present invention. Figure 10 one.
[0033] Figure 13 This is a cross-sectional view of the process of a trench gate silicon carbide VDMOS with low gate charge and low on-resistance according to the present invention. Figure 10 two.
[0034] Figure 14 This is a cross-sectional view of the process of a trench gate silicon carbide VDMOS with low gate charge and low on-resistance according to the present invention. Figure 10 three.
[0035] Figure 15 This is a cross-sectional view of the process of a trench gate silicon carbide VDMOS with low gate charge and low on-resistance according to the present invention. Figure 10 Four.
[0036] Figure 16 This is a cross-sectional view of the process of a trench gate silicon carbide VDMOS with low gate charge and low on-resistance according to the present invention. Figure 10 five.
[0037] Figure 17 This is a cross-sectional view of the process of a trench gate silicon carbide VDMOS with low gate charge and low on-resistance according to the present invention. Figure 10 six.
[0038] Figure 18 This is a cross-sectional view of the process of a trench gate silicon carbide VDMOS with low gate charge and low on-resistance according to the present invention. Figure 10 seven.
[0039] Figure 19 This is a cross-sectional view of the process of a trench gate silicon carbide VDMOS with low gate charge and low on-resistance according to the present invention. Figure 10 eight. Detailed Implementation
[0040] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.
[0042] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "in contact with," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this utility model, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion.
[0043] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figures and other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as “below,” “under,” or “below” other elements or features would be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein are interpreted accordingly.
[0044] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.
[0045] like Figure 1 As shown, this application embodiment provides a low-gate-charge, low-on-resistance trench-gate silicon carbide VDMOS, comprising:
[0046] Silicon carbide substrate 1;
[0047] A drift layer 2 is provided, the lower side of which is connected to the upper side of the silicon carbide substrate 1; the drift layer 2 is provided with a protrusion 21 and a groove 22, the groove 22 being located within the protrusion 21; the depth of the groove 22 is greater than the thickness of the protrusion 21;
[0048] The first P-type source region 3, the lower side of the first P-type source region 3 is connected to the upper side of the drift layer 2;
[0049] Schottky metal layer 4, the lower side of which is connected to the upper side of the drift layer 2, and the outer side of which is connected to the inner side of the first P-type source region 3;
[0050] The second P-type source region 5 has its lower side connected to the upper side of the drift layer 2, and its outer side connected to the inner side of the Schottky metal layer 4. The second P-type source region 5 is provided with a first P-type well region 51, an N-type source region 52, and a second P-type well region 53. The N-type source region 52 is located between the first P-type well region 51 and the second P-type well region 53. The inner side of the second P-type source region 5 and the inner side of the second P-type well region 53 are both connected to the outer side of the protrusion 21.
[0051] An insulating dielectric layer 6 is disposed at its lower part within the groove 22. The insulating dielectric layer 6 is connected to the upper side of the N-type source region 52, the upper side of the second P-type well region 53, and the upper side of the protrusion 21. A first floating gate 61 and a second floating gate 62 are provided within the insulating dielectric layer 6, with the first floating gate 61 located directly below the second floating gate 62. A groove 63 is provided on the insulating dielectric layer 6.
[0052] A gate metal layer 7 is disposed within the trench 63;
[0053] Source metal layer 8, which is connected to the first P-type source region 3, the Schottky metal layer 4, the second P-type source region 5 and the first P-type well region 51 respectively;
[0054] And a drain metal layer 9, which is connected to the lower side of the silicon carbide substrate 1.
[0055] In this embodiment, preferably, the doping concentration of the first P-type source region 3 is greater than the doping concentration of the first P-type well region 51; the doping concentration of the first P-type source region 3 is equal to the doping concentration of the second P-type source region 5; and the doping concentration of the first P-type well region 51 is equal to the doping concentration of the second P-type well region 53.
[0056] In this embodiment, preferably, the doping concentration of the N-type source region 52 is greater than the doping concentration of the first P-type well region 51, and less than the doping concentration of the first P-type source region 3.
[0057] In this embodiment, preferably, the width of the first P-type well region 51 is greater than the width of the second P-type well region 53.
[0058] In this embodiment, preferably, the width of the first floating gate 61 is smaller than the width of the second floating gate 62.
[0059] In this embodiment, preferably, the thicknesses of the first P-type source region 3, the Schottky metal layer 4, and the second P-type source region 5 are all equal.
[0060] In this embodiment, preferably, the lower side of the second levitation gate 62 is lower than the upper side of the drift layer 2.
[0061] like Figures 1 to 19 As shown, the above-mentioned method for fabricating VDMOS includes the following steps:
[0062] Step 1: Deposit metal on the lower side of silicon carbide substrate 1 to form drain metal layer 9; grow epitaxially on the upper side of silicon carbide substrate 1 to form drift layer 2;
[0063] Step 2: Form a barrier layer 100 above the drift layer 2, etch the barrier layer 100 to form a via, and implant ions to form a P-type region 200.
[0064] Step 3: Remove the barrier layer 100 from Step 2, reform the barrier layer 100, etch the barrier layer 100 to form a via, and implant ions to form a P-type second region 300.
[0065] Step 4: Remove the barrier layer 100 from Step 3, reform the barrier layer 100, etch the barrier layer 100 to form a via, and implant ions to form the total well region 400.
[0066] Step 5: Remove the barrier layer 100 from step 4, reform the barrier layer 100, etch the barrier layer 100 to form a via, implant ions to form an N-type source region 52, and divide the total well region 400 into a first P-type well region 51 and a second P-type well region 53.
[0067] Step 6: Remove the barrier layer 100 from step 5, reform the barrier layer 100, etch the barrier layer 100 to form a via, and etch the P-type region 200 to the upper side of the drift layer 2 to obtain the first P-type source region 3 and the second P-type source region 5. Deposit metal to form the Schottky metal layer 4.
[0068] Step 7: Remove the barrier layer 100 from step 6, reform the barrier layer 100, etch the barrier layer 100 to form a through hole, etch the drift layer 2 to form a groove 22, and deposit to form the first insulating layer 64.
[0069] Step 8: Remove the barrier layer 100 from step 7, reform the barrier layer 100, etch the barrier layer 100 to form a through hole, etch the first insulating layer 64, deposit metal, and form the first floating gate 61.
[0070] Step 9: Remove the barrier layer 100 from step 8, reform the barrier layer 100, etch the barrier layer 100 to form a via, and deposit to form the second insulating layer 65.
[0071] Step 10: Remove the barrier layer 100 from step 9, reform the barrier layer 100, etch the barrier layer 100 to form a via, etch the second insulating layer 65, deposit metal, and form the second floating gate 62.
[0072] Step 11: Remove the barrier layer 100 from step 10, reform the barrier layer 100, etch the barrier layer 100 to form a via, and deposit to form a third insulating layer 66. The insulating dielectric layer 6 includes a first insulating layer 64, a second insulating layer 65, and a third insulating layer 66.
[0073] Step 12: Remove the barrier layer 100 from step 11, reform the barrier layer 100, etch the barrier layer 100 to form a via, deposit metal, and form the source metal layer 8.
[0074] Step 13: Remove the barrier layer 100 from step 12, reform the barrier layer 100, etch the barrier layer 100 to form a via, etch the insulating dielectric layer 6 to form a trench 63, deposit metal to form a gate metal layer 7, remove the barrier layer 100, and complete the fabrication.
[0075] In another embodiment of this invention, the doping concentration of the N-type silicon carbide substrate 1 is 2-8e18cm. -3 The doping concentration of the N-type drift layer 2 is 6-10e16cm. -3 The doping concentration of both the first P-type well region 51 and the second P-type well region 53 is 1-5e15cm. -3 The doping concentration of the first P-type source region 3 and the second P-type source region 5 is 1-5e19cm. -3 The insulating dielectric layer can be made of silicon dioxide, and the doping concentration of the N-type source region 52 is 2-8e18cm. -3 ;
[0076] The doping concentration of the N-type silicon carbide substrate 1 is to ensure a low-resistance ohmic contact with the drain metal layer 9, thereby reducing the overall on-resistance of the device. The doping concentration of the N-type drift layer 2 is a trade-off between the reverse breakdown voltage and the on-resistance of the device. The doping concentration of the first P-type source region 3 can reduce the contact resistance between the first P-type source region 3 and the source metal layer 8, thereby reducing the parasitic diode conduction loss of the device. Furthermore, the doping concentration of the second P-type source region 5 ensures that the space charge region of the second P-type source region 5 terminates at the bottom of the first P-type well region 51 and the second P-type well region 53 when the drain voltage is high, thereby reducing the doping concentration of the first P-type well region 51 and the second P-type well region 53. The doping concentration of the first P-type well region 51 and the second P-type well region 53 is to reduce the gate control charge of the device gate and improve the switching speed of the device.
[0077] The thickness of the N-type silicon carbide substrate 1 is 1 μm, and the thickness of the N-type drift layer 2 is 50-100 μm, which is adjusted within the above range according to different requirements for the withstand voltage characteristics of the device. The thickness of the insulating dielectric layer 6 at the bottom and on both sides of the first floating gate 61 is 800 nm. This is to ensure that the first floating gate 61 is not broken down due to electric field concentration. The width of the insulating dielectric layer on the left and right sides of the second floating gate 62 and the thickness of the insulating dielectric layer at the top are 200 nm. This is to ensure the gate control of the conductive channels on the left and right sides of the second floating gate 62 while ensuring the reliability of the second floating gate 62. To reduce the on-resistance of the device, when the drain is subjected to voltage, an electric field concentration occurs at the gate corner. As the voltage approaches the top gate, the electric field concentration weakens. Therefore, the thickness of the insulating dielectric on both sides of the second floating gate 62 can be thinner. The distance between the lower side of the gate metal layer 7 and the second floating gate 62 is 50nm. This is the key to the device's control of the switch and there is no electric field concentration problem. It can be fabricated at the highest performance. The width of the insulating dielectric on both sides of the gate metal layer 7 is 500nm. This is to achieve isolation from the source metal layer 8. Its width does not affect the device characteristics.
[0078] The maximum thickness of the first P-type source region 3 and the second P-type source region 5 is 600 nm. The thickness of the first P-type well region 51 and the second P-type well region 53 is 300 nm. The thickness of the N-type source region 52 is 300 nm. The thickness of the gate metal layer 7 is 250 nm. The thickness of the source metal layer 8 is 300 nm. The width of the Schottky metal layer 4 is 1 μm. The width of the N-type source region 52 is 500 nm. The width of the second P-type well region 53 is 300 nm. This is to reduce the gate charge of the device. The width of the first P-type well region is 500-800 nm. The width of the second floating gate 62 is 2 μm. The width of the first floating gate 61 is 0.8 μm. The width of the gate metal layer 7 is 3.8 μm.
[0079] While specific embodiments of the present invention have been described above, those skilled in the art should understand that the specific embodiments described are merely illustrative and not intended to limit the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should be covered within the scope of protection of the claims of the present invention.
Claims
1. A trench-gate silicon carbide VDMOS with low gate charge and low on-resistance, characterized in that: include: silicon carbide substrate; A drift layer, wherein the lower side of the drift layer is connected to the upper side of the silicon carbide substrate; The drift layer has protrusions and grooves, with the grooves located inside the protrusions; the depth of the grooves is greater than the thickness of the protrusions. A first P-type source region, the lower side of which is connected to the upper side of the drift layer; A Schottky metal layer, wherein the lower side of the Schottky metal layer is connected to the upper side of the drift layer, and the outer side of the Schottky metal layer is connected to the inner side of the first P-type source region; The second P-type source region has its lower side connected to the upper side of the drift layer and its outer side connected to the inner side of the Schottky metal layer. The second P-type source region is provided with a first P-type well region, an N-type source region and a second P-type well region. The N-type source region is located between the first P-type well region and the second P-type well region. The inner side of the second P-type source region and the inner side of the second P-type well region are both connected to the outer side of the protrusion. An insulating dielectric layer is provided at its lower part within the groove. The insulating dielectric layer is connected to the upper side of the N-type source region, the upper side of the second P-type well region, and the upper side of the protrusion. A first floating gate and a second floating gate are provided within the insulating dielectric layer, with the first floating gate located directly below the second floating gate. The insulating dielectric layer is provided with grooves. A gate metal layer, wherein the gate metal layer is disposed within the trench; A source metal layer, wherein the source metal layer is respectively connected to the first P-type source region, the Schottky metal layer, the second P-type source region and the first P-type well region; And a drain metal layer, which is connected to the lower side of the silicon carbide substrate.
2. The low gate charge, low on-resistance trench gate silicon carbide VDMOS as described in claim 1, characterized in that: The doping concentration of the first P-type source region is greater than the doping concentration of the first P-type well region; the doping concentration of the first P-type source region is equal to the doping concentration of the second P-type source region; The doping concentration of the first P-type well region is equal to the doping concentration of the second P-type well region.
3. The low gate charge, low on-resistance trench gate silicon carbide VDMOS as described in claim 1, characterized in that: The doping concentration of the N-type source region is greater than the doping concentration of the first P-type well region, but less than the doping concentration of the first P-type source region.
4. The low gate charge, low on-resistance trench gate silicon carbide VDMOS as described in claim 1, characterized in that: The width of the first P-type well region is greater than the width of the second P-type well region.
5. The low gate charge, low on-resistance trench gate silicon carbide VDMOS as described in claim 1, characterized in that: The width of the first floating gate is smaller than the width of the second floating gate.
6. The low gate charge, low on-resistance trench gate silicon carbide VDMOS as described in claim 1, characterized in that: The thicknesses of the first P-type source region, the Schottky metal layer, and the second P-type source region are all equal.
7. The low gate charge, low on-resistance trench gate silicon carbide VDMOS as described in claim 1, characterized in that: The lower side of the second levitation gate is lower than the upper side of the drift layer.