Semiconductor device
By designing groove structures and doped region layouts in SiC semiconductor devices, the manufacturing challenges and on-resistance issues caused by the reduction of cell size were solved, achieving device miniaturization and performance improvement.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- HUNAN SANAN SEMICON CO LTD
- Filing Date
- 2025-05-21
- Publication Date
- 2026-06-05
AI Technical Summary
In the miniaturization process of SiC semiconductor devices, the reduction in cell size leads to challenges in manufacturing process windows and chip design. Furthermore, the junction field-effect transistor region has a significant impact on on-resistance, making it difficult to reduce cell size to improve device performance without reducing ohmic contact area.
The design of the semiconductor device structure includes creating a groove in the repeating cell of the epitaxial layer, extending the ohmic contact layer into the groove to cover the upper surface of the second doped region, and designing the second doped region in the JFET region to protrude from the top surface of the epitaxial layer. The gate is disposed between adjacent repeating cells to cover the channel region.
Without reducing the ohmic contact area, the cell size is reduced and the impact of the JFET region on the on-resistance is decreased, thereby improving device performance and making it suitable for high-frequency switching applications.
Smart Images
Figure CN224329837U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of power electronic device technology, and in particular to a semiconductor device. Background Technology
[0002] Silicon carbide (SiC) technology has developed rapidly in recent years, with continuous product iteration and upgrades, and constantly improving device performance, demonstrating great application prospects in the field of power control. Compared with Si semiconductor devices, SiC semiconductor devices have advantages in various aspects, but they are not price-competitive. Reducing device costs by decreasing chip area has become an important research focus in the development of SiC technology. Smaller chip areas mean more devices on a wafer of the same size, without increasing the overall cost, including substrate, epitaxy, and manufacturing, thus reducing the average cost per device. Miniaturization of SiC semiconductor devices aims to reduce their cell size, such as cell pitch. However, increasingly smaller cell sizes bring new challenges to the process window for device manufacturing and chip design. Utility Model Content
[0003] In view of this, the present invention provides a semiconductor device that can reduce the cell size and reduce the influence of the junction field effect transistor (JFET) region on the on-resistance without reducing the ohmic contact area, thereby improving device performance.
[0004] Specifically, a semiconductor device provided in this embodiment of the present invention includes, for example, a substrate, an epitaxial layer, an ohmic contact layer, and a gate. The epitaxial layer is disposed on the substrate and has a plurality of repeating units. The plurality of repeating units are located on the side of the epitaxial layer away from the substrate in a first direction and are spaced apart along a second direction different from the first direction. The first direction is the direction from the substrate to the epitaxial layer. Each repeating unit includes a first doped region, a second doped region, and a third doped region and has a groove. The epitaxial layer and the second doped region have a first conductivity type. The first doped region and the third doped region have a second conductivity type different from the first conductivity type. The second doped region is located on the side of the first doped region away from the substrate in the first direction and is located on opposite sides of the groove in the second direction. The second doped region has an upper end face away from the substrate in the first direction. The portion of the epitaxial layer between two adjacent repeating units has a top surface away from the substrate. The second doped region protrudes from the top surface in the first direction so that the upper end face is higher than the top surface. The third doped region is located below the groove in the first direction and is in contact with the first doped region. The second doped region is also located on opposite sides of the third doped region in the second direction. The ohmic contact layer extends into the groove of each of the repeating cells and extends outward from the groove to the upper end face of the second doped region of the repeating cell. The gate is disposed between two adjacent repeating cells and covers the channel region of the first doped region of each of the two adjacent repeating cells.
[0005] The above embodiments of this utility model can have the following beneficial effects: Since each repeating unit of the epitaxial layer has the groove, and the ohmic contact layer extends into the groove of each repeating unit and extends outward from the groove to the upper end surface of the second doped region covering the repeating unit, the cell size, such as the cell pitch, can be reduced without reducing the ohmic contact area. Furthermore, the second doped region (e.g., as the source region of a MOSFET device) protrudes in the first direction from the top surface of the epitaxial layer located between two adjacent repeating units (e.g., the portion where the JFET region of a planar MOSFET device is formed) away from the top surface of the substrate, so that the upper end surface of the second doped region is higher than the top surface. Compared with the case where the top surface of the JFET region of a planar MOSFET device is flush with the upper end surface of the source region, the influence of the JFET region on the on-resistance can be reduced to improve device performance. Attached Figure Description
[0006] The specific embodiments of this utility model will now be described in detail with reference to the accompanying drawings.
[0007] Figure 1A This is a partial structural cross-sectional schematic diagram of a semiconductor device provided in an embodiment of the present invention.
[0008] Figure 1B for Figure 1A The diagram shows a partial cross-sectional view of the semiconductor device after the formation of the interlayer dielectric layer, the first electrode layer, and the second electrode layer.
[0009] Figure 2A-2H for Figure 1B The diagram shows a schematic representation of multiple processes in a method for fabricating a semiconductor device, wherein... Figure 2H The cross-sectional structure along section line AA in the top view shown corresponds to Figure 2G The structure after removing the ohmic contact layer.
[0010] Figure 3A This is a partial structural cross-sectional schematic diagram of another semiconductor device provided in an embodiment of the present invention.
[0011] Figure 3B for Figure 3A The diagram shows a partial cross-sectional view of the semiconductor device after the formation of the interlayer dielectric layer, the first electrode layer, and the second electrode layer.
[0012] Figures 4A-4B for Figure 3B The diagram shows a process structure of a method for fabricating a semiconductor device, wherein... Figure 4B The cross-sectional structure along section line AA in the top view shown corresponds to Figure 4A The structure after removing the ohmic contact layer. Detailed Implementation
[0013] To make the above-mentioned objectives, features and advantages of this utility model more apparent and understandable, the specific embodiments of this utility model will be described in detail below with reference to the accompanying drawings.
[0014] To enable those skilled in the art to better understand the technical solutions of this utility model, the technical solutions of this utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments of this utility model. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of this utility model.
[0015] It should be noted that the terms "first," "second," "third," etc., in the specification, claims, and accompanying drawings of this utility model are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that the embodiments of the utility model described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0016] It should also be noted that the division of multiple embodiments in this utility model is only for the convenience of description and should not constitute a special limitation. Features in various embodiments can be combined and referenced in each other without contradiction.
[0017] See Figure 1A and Figure 1B This utility model provides a semiconductor device 10, which is, for example, a planar MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device. Specifically, the semiconductor device includes, for example, a substrate 11, an epitaxial layer 12, an ohmic contact layer 14, and a gate 15. The epitaxial layer 12 is disposed on the substrate 11 and has a plurality of repeating units 13 ( Figure 1A The diagram illustrates two adjacent repeating units 13. The plurality of repeating units 13 are located on the side of the epitaxial layer 12 away from the substrate 11 in a first direction B1 and are spaced apart along a second direction B2 different from the first direction B1. The first direction B1 is the direction from the substrate 11 to the epitaxial layer 12, and the second direction B2 is, for example, perpendicular to the first direction B1.
[0018] As described above, each repeating unit 13 includes a first doped region 131, a second doped region 133, and a third doped region 135, and has a groove 13H. The epitaxial layer 12 and the second doped region 133 have a first conductivity type, such as N-type, and the first doped region 131 and the third doped region 135 have a second conductivity type, such as P-type, different from the first conductivity type. The second doped region 133 is located on the side of the first doped region 131 facing away from the substrate 11 in the first direction B1, and is located on opposite sides of the groove 13H in the second direction B2. The second doped region 133 has an upper end face 133T facing away from the substrate 11 in the first direction B1. The portion of the epitaxial layer 12 located between two adjacent repeating units 13 has a top surface 12T facing away from the substrate 11. The second doped region 133 protrudes from the top surface 12T in the first direction B1 such that the upper end face 133T is higher than the top surface 12T. The third doped region 135 is located below the groove 131H in the first direction B1 and is in contact with the first doped region 131. The second doped region 133 is also located on opposite sides of the third doped region 135 in the second direction B2.
[0019] The ohmic contact layer 14 extends into the groove 13H of each repeating unit 13 and extends outward from the groove 13H to the upper end face 133T covering the second doped region 133 of the repeating unit 13.
[0020] The gate 15 is disposed between two adjacent repeating units 13 and covers the channel region 131C of the first doped region 131 of each of the two adjacent repeating units 13.
[0021] As can be seen from the above, since each repeating unit 13 of the epitaxial layer 12 has a groove 13H, and the ohmic contact layer 14 extends into the groove 13H of each repeating unit 13 and extends outward from the groove 13H to the upper end surface 133T of the second doped region 133 covering the repeating unit 13, the cell size, such as the cell pitch, can be reduced without reducing the ohmic contact area. Furthermore, the second doped region 133 (e.g., as the source region of a MOSFET device) protrudes in the first direction B1 from the portion of the epitaxial layer 12 located between two adjacent repeating units 13 (e.g., the portion forming the JFET region of a planar MOSFET device) away from the top surface 12T of the substrate 11, so that the upper end surface 133T of the second doped region 133 is higher than the top surface 12T. Compared to the case where the top surface of the JFET region of a planar MOSFET device is flush with the upper end surface of the source region, the influence of the JFET region on the on-resistance can be reduced to improve device performance.
[0022] In some embodiments, see Figure 1A and Figure 1B For example, the substrate 11 is an N-type SiC substrate, and its doping concentration is, for example, in the range of 1E19 cm⁻¹. -3 -1E20cm -3 The epitaxial layer 12 is an N-type SiC epitaxial layer, and its doping concentration is, for example, in the range of 1E16cm. -3 -1E17cm -3 The first doped region 131 and the third doped region 135 are P-type doped regions, and the second doped region 133 is an N-type doped region. The doping concentrations of the first doped region 131, the second doped region 133, and the third doped region 135 can be found in existing mature technologies and will not be elaborated here. Furthermore, the doping concentration of the third doped region 135 is typically higher than that of the first doped region 133. The ohmic contact layer 14 includes, for example, a stacked titanium (Ti) layer and a nickel (Ni) layer, but this invention is not limited to this.
[0023] In some embodiments, see Figure 1A and Figure 1BIn each of the repeating units 13, the two facing side surfaces 133S of the second doped region 133 in the second direction B2 respectively constitute the two sidewalls of the groove 13H in the second direction B2, and the upper surface 135T of the third doped region 135 facing away from the substrate 11 constitutes the bottom wall of the groove 13H; in other words, the two side surfaces 133S of the second doped region 133 and the upper surface 135T of the third doped region 135 together define the groove 13H. Furthermore, the bottom wall of the groove 13H is higher than the lower end surface 133B of the second doped region 133 facing the substrate 11 in the first direction B1, and the ohmic contact layer 14 contacts the two sidewalls and the bottom wall respectively in the groove 13H. In this way, a better ohmic contact effect can be achieved.
[0024] In some embodiments, see Figure 1A and Figure 1B The distance h1 from the bottom wall of the groove 13H (corresponding to the upper surface 135T of the third doped region 135) along the first direction B1 to the upper end face 133 of the second doped region 133 (reference) Figure 2G The depth of the groove 13H is less than the distance h2 from the lower end face 133B of the second doped region 133 along the first direction B1 to the upper end face 133T of the second doped region 133 (reference). Figure 2G In this way, a better ohmic contact effect can be achieved.
[0025] In some embodiments, see Figure 1A and Figure 1B In each of the repeating units 13, the third doped region 135 is located on the side of the first doped region 131 facing away from the substrate 11 in the first direction B1, and the lower surface 135B of the third doped region 135 facing the substrate 11 is higher than the bottom surface 131B of the first doped region 131 facing the substrate 11 in the first direction B1. In this way, the semiconductor device 10 is more suitable for high-frequency switching applications. Furthermore, it is understood that, to accommodate other different needs, the third doped region 135 may also be designed to penetrate the first doped region 131.
[0026] In some embodiments, see Figure 1A and Figure 1BThe semiconductor device 10 is a planar MOSFET device. A junction field-effect transistor (JFET) is formed in the portion of the epitaxial layer 12 located between two adjacent repeating units 13. The top surface 12T of the epitaxial layer 12 is the top surface of the JFET facing away from the substrate 11. The JFET contacts the first doped region 131 of each of the two adjacent repeating units 13. The channel region 131C of the first doped region 131 is located between the second doped region 133 and the JFET in the second direction B2; that is, the channel region 131C is a lateral channel region. In this way, the second doped region 133 partially protrudes from the JFET, thereby reducing the impact of the JFET on the on-resistance and improving device performance.
[0027] As described above, the second doped region 133 of each of the two adjacent repeating units 13 has an intermediate step surface 133M that is flush with the top surface of the junction field-effect transistor (JFET). The intermediate step surface 133M is located in the first direction B1 between the upper end surface 133T and the lower end surface 133B of the second doped region 133 facing the substrate 11. Thus, the second doped region 133 is stepped, facilitating the provision of the area required for the gate 15. Furthermore, the gate 15 is located on the top surface of the JFET (corresponding to the top surface 12T of the epitaxial layer 12) and extends from the JFET in the second direction B2 to both sides, crossing the channel region 131 of each of the two adjacent repeating units 13 and covering a portion of the intermediate step surface 133M of the second doped region 13. The gate 15 here includes, for example, a gate oxide layer 151 and a gate electrode layer 153, and the gate electrode layer 153 is electrically insulated from the junction field-effect transistor region (JFET) of the epitaxial layer 12, the channel region 131C and the second doped region 133 through the gate oxide layer 151; the gate oxide layer 151 is, for example, a silicon dioxide layer, and the gate electrode layer 153 is, for example, a polysilicon layer.
[0028] In some embodiments, see Figure 1A and Figure 1BThe second doped region 133 includes a first portion 1331 and a second portion 1332 that are sequentially connected in the first direction B1. The first portion 1331 has the intermediate step surface 133M and the lower end surface 133B of the second doped region 133 and is located between the intermediate step surface 133M and the lower end surface 133B. The second portion 1332 protrudes from the intermediate step surface 133M in the first direction B1 and extends to the upper end surface 133T of the second doped region 133. The width W1 of the first portion 1331 in the second direction B2 is greater than the width W2 of the second portion 1332 in the second direction B2 (see reference). Figure 2G In other words, the second doped region 133 has a two-stage stepped structure in the first direction B1, which is easy to form and thus simplifies the process.
[0029] In some embodiments, see Figure 1A and Figure 1B The ohmic contact layer 14 includes two ohmic contact segments 14a and 14b spaced apart in the second direction B2 and corresponding one-to-one with the two adjacent repeating units 13. Each ohmic contact segment 14a and 14b extends into the groove 13H of the corresponding repeating unit 13 and extends outward from the groove 13H to cover the upper end face 133T of the second doped region 133 of the corresponding repeating unit 13. The distance D1 between the two ohmic contact segments 14a and 14b in the second direction B2 is equal to the distance D2 between the second portions 1332 of the second doped regions 133 of the two adjacent repeating units 13 in the second direction B2. In this way, these ohmic contact segments 14a and 14b can be used as a mask layer for self-aligned etching to form the area required by the gate 15, thereby simplifying the process.
[0030] In some embodiments, see Figure 1A and Figure 1BThe semiconductor device 10 further includes an interlayer dielectric layer 16, a first electrode layer 17, and a second electrode layer 18. The first electrode layer 17 is located on the side of the ohmic contact layer 14 and the gate 15 opposite to the substrate 11, and is electrically contacted with the ohmic contact layer 14 and electrically insulated from the gate 15 by the interlayer dielectric layer 16. The second electrode layer 18 is located on the side of the substrate 11 opposite to the epitaxial layer 12. For example, the interlayer dielectric layer 16 may be a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer. Furthermore, when the semiconductor device 10 is a MOSFET device, the first electrode layer 17 may be, for example, a source metal layer such as an aluminum layer, and the second electrode layer 18 may be, for example, a drain metal layer including a silver (Ag) layer and alternating layers of titanium and nickel layers disposed between the silver layer and the substrate 11. In this way, the semiconductor device 10 is a vertical device.
[0031] In some embodiments, see Figure 1A and Figure 1B The ohmic contact layer 14 includes a first lateral segment HS1 located within a groove 13H of each repeating unit 13, a first vertical segment VS1 and a second vertical segment VS2 respectively connected to opposite ends of the first lateral segment HS1, and a second lateral segment HS2 and a third lateral segment HS3 respectively located on opposite sides of the groove 13H in the second direction B2 and covering the upper end surface 133T of the second doped region 133 of the overlapping unit 13. The first lateral segment HS1, the second lateral segment HS2 and the third lateral segment HS3 extend along the second direction B2, the first vertical segment VS1 and the second vertical segment VS2 extend along the first direction B1, the second lateral segment HS2 connects to the end of the first vertical segment VS1 away from the first lateral segment HS1, and the third lateral segment HS3 connects to the end of the second vertical segment VS2 away from the first lateral segment HS1. In this way, each ohmic contact segment 14a, 14b is a bent five-segment structure, thereby achieving a sufficiently large ohmic contact area within a small cell pitch.
[0032] To facilitate better understanding Figure 1B The semiconductor device 10 shown below will be combined with Figure 2A-2H and Figure 1A and Figure 1B A brief description of a semiconductor device fabrication method is as follows:
[0033] (1) Provide a substrate 11 and epitaxially grow an epitaxial layer 12 on the substrate 11, such as Figure 2A As shown;
[0034] (2) P-type ion implantation is performed within the epitaxial layer 12 to form multiple spaced P-Well regions 1310 within the epitaxial layer 12, such as... Figure 2B As shown;
[0035] (3) N-type ion implantation is performed in each P-Well region 1310 to form an N-region 1330 in each P-Well region 1310, such as Figure 2C As shown;
[0036] (4) P-type ion implantation is performed within each P-Well region 1310 to form a P-Plus region 1350 within each P-Wel region 1310, such as... Figure 2D As shown;
[0037] (5) Etch each P-Plus region 1350 to form the groove 13H and the third doped region 135, such as Figure 2E As shown;
[0038] (6) Forming an ohmic contact layer 14, wherein the ohmic contact layer 14 includes, for example, spaced-apart ohmic contact segments 14a and 14b, which respectively extend into the corresponding grooves 13H and outward from the grooves 13H to cover a portion of the upper surface of the corresponding N region 1330, such as... Figure 2F As shown;
[0039] (7) Self-aligned etching is performed using the ohmic contact layer 14 as a mask layer to obtain multiple, for example, adjacent repeating units 13. Each repeating unit 13 includes, for example, a P-type first doped region 131, an N-type second doped region 133, and a P-type third doped region 135, and has a groove 13H. The second doped region 133 is stepped and includes a first part 1331 and a second part 1332 connected in sequence. Figure 2G As shown. It is worth mentioning that, Figure 2H The cross-sectional structure along section line AA in the top view shown corresponds to Figure 2G The structure after removing ohmic contact layer 14 Figure 2H The vertical dashed line in the figure represents the corner of the stepped second doped region 133.
[0040] (8) A silicon dioxide layer is formed in the self-aligned etched region as a gate oxide layer 151, and a polysilicon layer is formed as a gate electrode layer 153 to obtain the gate electrode 15, as shown below. Figure 1A As shown;
[0041] (9) An interlayer dielectric layer 16 is deposited in the self-aligned etched region, followed by the formation of a first electrode layer 17 and a second electrode layer 18, thereby producing a material as shown in the figure. Figure 1B The semiconductor device shown.
[0042] Furthermore, it is worth mentioning that the semiconductor device provided in this embodiment of the present invention is not limited to... Figure 1A and Figure 1B The planar MOSFET device shown can also be a trench MOSFET device, for example... Figure 3A and Figure 3B As shown.
[0043] Specifically, see Figure 3A and Figure 3B As a trench MOSFET device, the epitaxial layer 12 is formed with a trench 12TR recessed between two adjacent repeating units 13 along the first direction B1. The top surface 12T of the epitaxial layer 12 is the bottom wall of the trench 12TR. The bottom surface 131B of the first doped region 131 of each of the two adjacent repeating units 13, facing the substrate 11, is higher than or flush with the bottom wall of the trench 12TR (corresponding to the top surface 12T) in the first direction B1. The channel region 131C of the first doped region 131 of each of the two adjacent repeating units 13 is located between the lower end surface 133B of the second doped region 133 facing the substrate 11 and the bottom wall of the trench 12TR (corresponding to the top surface 12T) in the first direction B1. That is, the channel region 131C is a longitudinal channel region. Furthermore, the gate 15 is located within the trench 12TR and spans the channel region 131C of the first doped region 131 of each of the two adjacent repeating units 13 along the first direction B1. Here, the gate 15 includes, for example, a gate oxide layer 151 and a gate electrode layer 153, and the gate electrode layer 153 is electrically insulated from the epitaxial layer 12, the channel region 131C, and the second doped region 133 through the gate oxide layer 151; the gate oxide layer 151 is, for example, a silicon dioxide layer, and the gate electrode layer 153 is, for example, a polysilicon layer. By designing the semiconductor device of this embodiment as a trench-type MOSFET device, the influence of the junction field-effect transistor (JFET) region on the conductivity resistance can be further reduced or even eliminated, thereby improving device performance.
[0044] In some embodiments, see Figures 3A-3B and Figures 4A-4BThe ohmic contact layer 14 includes two ohmic contact segments 14a and 14b spaced apart in the second direction B2 and corresponding one-to-one with the two adjacent repeating units 13. Each ohmic contact segment 14a and 14b extends into the groove 13H of the corresponding repeating unit 13 and extends outward from the groove 13H to cover the upper end face 133T of the second doped region 133 of the corresponding repeating unit 13. The distance D1 between the two ohmic contact segments 14a and 14b in the second direction B2 is equal to the width D3 of the trench 12TR in the second direction B2 (reference). Figure 4A In this way, these ohmic contact segments 14a and 14b can be used as mask layers for self-aligned etching to form the trench 12TR, thereby simplifying the process. It is worth mentioning that... Figure 4B The cross-sectional structure along section line AA in the top view shown corresponds to Figure 4A Structure after removing ohmic contact layer 14.
[0045] The above description is merely a preferred embodiment of the present utility model and is not intended to limit the present utility model in any way. Although the present utility model has been disclosed above with reference to a preferred embodiment, it is not intended to limit the present utility model. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present utility model. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present utility model without departing from the scope of the present utility model shall still fall within the scope of the present utility model.
Claims
1. A semiconductor device, characterized in that, include: Substrate; An epitaxial layer is disposed on the substrate and has a plurality of repeating units. These repeating units are located in a first direction on the side of the epitaxial layer opposite to the substrate and are spaced apart along a second direction different from the first direction. The first direction is the direction from the substrate to the epitaxial layer. Each repeating unit includes a first doped region, a second doped region, and a third doped region and has a groove formed therein. The epitaxial layer and the second doped region have a first conductivity type, and the first doped region and the third doped region have a second conductivity type different from the first conductivity type. The second doped region is located on the side of the first doped region facing away from the substrate in the first direction and on opposite sides of the groove in the second direction. The second doped region has an upper end face facing away from the substrate in the first direction. The portion of the epitaxial layer between two adjacent repeating units has a top surface facing away from the substrate. The second doped region protrudes from the top surface in the first direction such that the upper end face is higher than the top surface. The third doped region is located below the groove in the first direction and is in contact with the first doped region, and the second doped region is located on opposite sides of the third doped region in the second direction; an ohmic contact layer extends into the groove of each repeating unit and extends outward from the groove to cover the upper end face of the second doped region of the repeating unit. as well as A gate is disposed between two adjacent repeating cells and covers the channel region of the first doped region of each of the two adjacent repeating cells.
2. The semiconductor device according to claim 1, characterized in that, The second doped region of each repeating unit has two side surfaces facing each other in the second direction that respectively form two sidewalls of the groove in the second direction. The upper surface of the third doped region away from the substrate forms the bottom wall of the groove. The bottom wall of the groove is higher than the lower end surface of the second doped region facing the substrate in the first direction. The ohmic contact layer is in contact with the two sidewalls and the bottom wall in the groove.
3. The semiconductor device according to claim 2, characterized in that, The distance from the bottom wall of the groove to the upper surface of the second doped region along the first direction is equal to the depth of the groove and less than the distance from the lower surface of the second doped region to the upper surface of the second doped region along the first direction.
4. The semiconductor device according to claim 1, characterized in that, The third doped region of each repeating unit is located on the side of the first doped region away from the substrate in the first direction, and the lower surface of the third doped region facing the substrate is higher than the bottom surface of the first doped region facing the substrate in the first direction.
5. The semiconductor device according to claim 1, characterized in that, The semiconductor device is a planar MOSFET device. The portion of the epitaxial layer located between the two adjacent repeating units forms a junction field-effect transistor region. The top surface of the epitaxial layer is the top surface of the junction field-effect transistor region facing away from the substrate. The junction field-effect transistor region is in contact with the first doped region of each of the two adjacent repeating units. The channel region of the first doped region is located between the second doped region and the junction field-effect transistor region in the second direction. The second doped region of each of the two adjacent repeating units has an intermediate step surface that is flush with the top surface of the junction field-effect transistor region. The intermediate step surface is located in the first direction between the upper end surface of the second doped region and the lower end surface of the second doped region facing the substrate. The gate is located on the top surface of the junction field-effect transistor region and extends from the junction field-effect transistor region in the second direction to both sides, crossing the channel region of each of the two adjacent repeating units and covering a portion of the intermediate step surface of the second doped region.
6. The semiconductor device according to claim 5, characterized in that, The second doped region includes a first portion and a second portion that are sequentially connected in the first direction. The first portion has the intermediate step surface and the lower end surface of the second doped region and is located between the intermediate step surface and the lower end surface. The second portion protrudes from the intermediate step surface in the first direction and extends to the upper end surface of the second doped region. The width of the first portion in the second direction is greater than the width of the second portion in the second direction.
7. The semiconductor device according to claim 6, characterized in that, The ohmic contact layer includes two ohmic contact segments spaced apart in the second direction and corresponding one-to-one with the two adjacent repeating units. Each ohmic contact segment extends into the groove of the corresponding repeating unit and extends outward from the groove to the upper end face covering the second doped region of the corresponding repeating unit. The distance between the two ohmic contact segments in the second direction is equal to the distance between the second portions of the second doped regions of the two adjacent repeating units in the second direction.
8. The semiconductor device according to claim 1, characterized in that, The semiconductor device is a trench MOSFET device. The epitaxial layer is formed with a trench recessed between two adjacent repeating units along the first direction. The top surface of the epitaxial layer is the bottom wall of the trench. The bottom surface of the first doped region of each of the two adjacent repeating units facing the substrate is higher than or flush with the bottom wall of the trench in the first direction. The channel region of the first doped region of each of the two adjacent repeating units is located between the lower end surface of the second doped region facing the substrate and the bottom wall of the trench in the first direction. The gate is located in the trench and spans the channel region of the first doped region of each of the two adjacent repeating units along the first direction.
9. The semiconductor device according to claim 8, characterized in that, The ohmic contact layer includes two ohmic contact segments spaced apart in the second direction and corresponding one-to-one with the two adjacent repeating units. Each ohmic contact segment extends into the groove of the corresponding repeating unit and extends outward from the groove to the upper end face covering the second doped region of the corresponding repeating unit. The distance between the two ohmic contact segments in the second direction is equal to the width of the groove in the second direction.
10. The semiconductor device according to any one of claims 1 to 9, characterized in that, It also includes an interlayer dielectric layer, a first electrode layer, and a second electrode layer. The first electrode layer is located on the side of the substrate opposite to the ohmic contact layer and the gate, and is in electrical contact with the ohmic contact layer and electrically insulated from the gate through the interlayer dielectric layer. The second electrode layer is located on the side of the substrate opposite to the epitaxial layer; and / or The ohmic contact layer includes a first lateral segment located within a groove in each of the repeating units, a first vertical segment and a second vertical segment respectively connected to opposite ends of the first lateral segment, and a second lateral segment and a third lateral segment respectively located on opposite sides of the groove in the second direction and covering the upper end face of the second doped region of the overlapping unit. The first lateral segment, the second lateral segment and the third lateral segment extend along the second direction, the first vertical segment and the second vertical segment extend along the first direction, the second lateral segment connects to the end of the first vertical segment away from the first lateral segment, and the third lateral segment connects to the end of the second vertical segment away from the first lateral segment.