A transient voltage suppression protection device
By adopting a vertical structure design in the transient voltage suppression protection device, and using a series NPN transistor and parallel SCR structure, the problems of high trigger voltage and dynamic impedance of existing products are solved, achieving the effects of low capacitance and low clamping voltage, thus meeting the special protection requirements of electronic products.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- SHANGHAI JUREN SEMICONDUCTOR CO LTD
- Filing Date
- 2025-08-01
- Publication Date
- 2026-06-05
AI Technical Summary
Existing transverse low-capacitance TVS products have issues with high trigger and clamping voltages and large dynamic impedance, which cannot meet the requirements of electronic products for lower clamping voltages and smaller parasitic capacitances.
The design employs a vertical structure, including two NPN transistors with floating base regions connected in series and an ultra-low trigger voltage SCR structure connected in parallel. It utilizes a high resistivity substrate as a common collector to reduce capacitance and achieve low capacitance and low dynamic impedance through the parallel connection of the ultra-low trigger voltage SCR structure.
This device achieves transient voltage suppression protection with low capacitance, low clamping voltage, and small dynamic impedance, operating at lower voltages. It meets customer protection requirements, reduces production costs, saves space, simplifies processes, achieves better performance, and meets the needs of high-performance electronic products.
Smart Images
Figure CN224329839U_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, specifically to a transient voltage suppression and protection device. Background Technology
[0002] With the widespread adoption and continuous iteration of HDMI interfaces, the signal transmission rates of laptops and security electronic products are constantly increasing. Simultaneously, the manufacturing processes of backend IC devices are becoming increasingly advanced, making electronic products less resistant to ESD (electrostatic discharge) and EOS (electrical overstress). This places higher demands on the protection capabilities of electronic products, requiring lower clamping voltages and smaller parasitic capacitances. Existing lateral low-capacitance TVS products suffer from complex manufacturing processes and relatively high trigger voltages and clamping requirements. Customers need better device performance to meet the protection needs of backend ICs.
[0003] To address the issues of high trigger and clamping voltages and large dynamic impedance in existing low-capacitance TVS devices, a low-cost, space-saving, and simple-to-manufacture vertical low-capacitance high-performance transient voltage suppression and protection device has been developed. This device can operate at lower voltages and features low clamping voltage, low dynamic impedance, and low capacitance. Summary of the Invention
[0004] Therefore, this application provides a transient voltage suppression and protection device, including: a first transistor, a second transistor, and an SCR structure;
[0005] The first transistor and the second transistor are connected in series, and the first transistor and the second transistor are connected in parallel with the SCR structure;
[0006] The first transistor includes a well region, a first implantation region, and a first epitaxial layer; the second transistor includes the first epitaxial layer, a second epitaxial layer, and a substrate.
[0007] A second epitaxial layer, a first epitaxial layer, and a well region are sequentially disposed above the substrate, and the first implantation region is disposed in the well region;
[0008] The first implantation region, the first epitaxial layer, and the substrate are of the first doping type, and the well region and the second epitaxial layer are of the second doping type;
[0009] The SCR structure includes a second implantation region, a first epitaxial layer, a second epitaxial layer, and a substrate. The second implantation region is disposed in the first epitaxial layer and is of a second doping type.
[0010] In a preferred embodiment of this application, a third injection region is provided on the side of the first injection region away from the second injection region. The third injection region is disposed in the first epitaxial layer and is of the second doping type.
[0011] In a preferred embodiment of this application, a third injection region is provided on the side of the first injection region away from the second injection region. Both the first injection region and the third injection region are located in the well region, and the third injection region is of the second doping type.
[0012] In a preferred embodiment of this application, the second injection region is disposed in the trap region.
[0013] In a preferred embodiment of this application, a fourth injection region is provided on the side of the second injection region away from the first injection region. The fourth injection region is disposed in the well region and is of the first doping type.
[0014] In a preferred embodiment of this application, the first doping type is N-type and the second doping type is P-type.
[0015] In a preferred embodiment of this application, the resistivity of the second epitaxial layer is greater than 5.
[0016] Compared with the prior art, the embodiments of this application provide a transient voltage suppression protection device. This application uses a substrate as a common collector and connects two NPN transistors with floating base regions in series. This design can halve the capacitance to obtain a smaller capacitance. At the same time, an SCR structure with an ultra-low trigger voltage is connected in parallel to make a low-capacitance transient voltage suppression protection device, which can meet the special needs of customers for protection devices in practical applications. Attached Figure Description
[0017] To more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are merely exemplary, and those skilled in the art can derive other embodiments based on the provided drawings without creative effort.
[0018] The structures, proportions, sizes, etc. illustrated in this specification are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed herein, and are not intended to limit the conditions under which the present invention can be implemented. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportions, or adjustments to the size, without affecting the effects and objectives that the present invention can produce, should still fall within the scope of the technical content disclosed in the present invention.
[0019] Figure 1 This is a schematic diagram of the structure provided in Embodiment 1 of the present invention;
[0020] Figure 2 This is a schematic diagram of the structure provided in Embodiment 2 of the present invention;
[0021] Figure 3 This is a schematic diagram of the structure provided in Embodiment 3 of the present invention;
[0022] Figure 4 This is a schematic diagram of the structure provided in Embodiment 4 of the present invention;
[0023] Figure 5 This is a schematic diagram of the structure provided in Embodiment 5 of the present invention;
[0024] Figure 6 The above are equivalent circuit diagrams for embodiments 1 to 5 of this application. Detailed Implementation
[0025] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0026] Example 1
[0027] This application provides a transient voltage suppression and protection device, including: a first transistor, a second transistor, and an SCR structure;
[0028] The first transistor and the second transistor are connected in series, and the first transistor and the second transistor are connected in parallel with the SCR structure;
[0029] The first transistor includes a well region 4, a first implantation region 5, and a first epitaxial layer 3; the second transistor includes the first epitaxial layer 3, a second epitaxial layer 2, and a substrate 1.
[0030] A second epitaxial layer 2, a first epitaxial layer 3, and a well region 4 are sequentially disposed above the substrate 1, and the first implantation region 5 is disposed in the well region 4;
[0031] The first implantation region 5, the first epitaxial layer 3 and the substrate 1 are of the first doping type, and the well region 4 and the second epitaxial layer 2 are of the second doping type;
[0032] The SCR structure includes a second implantation region 6, a first epitaxial layer 3, a second epitaxial layer 2, and a substrate 1. The second implantation region 6 is disposed in the first epitaxial layer 3, and the second implantation region 6 is a second doping type.
[0033] In this embodiment, an isolation trench 7 is provided around the first transistor, the second transistor, and the SCR structure. The isolation trench 7 extends from top to bottom through the first epitaxial layer 3 and the second epitaxial layer 2 into the substrate 1. Additionally, a metal layer 8 is provided below the substrate 1 to bring out the collector electrode.
[0034] The first transistor is composed of a well region 4, a first implantation region 5 and a first epitaxial layer 3, and the second transistor is composed of the first epitaxial layer 3, a second epitaxial layer 2 and a substrate 1. The SCR structure is composed of a second implantation region 6, a first epitaxial layer 3, a second epitaxial layer 2 and a substrate 1. If the first doping type is N-type and the second doping type is P-type, then both the first transistor and the second transistor are NPN structures, and the SCR structure is composed of a PNP structure and an NPN structure.
[0035] The resistivity of the second epitaxial layer 2 is greater than 5 ohm·cm, and the substrate is also of high resistivity.
[0036] Example 2
[0037] Based on Embodiment 1, a third injection region 9 is provided on the side of the first injection region 5 away from the second injection region 6. The third injection region 9 is disposed in the first epitaxial layer 3 and is of the second doping type.
[0038] The first transistor is composed of a well region 4, a first injection region 5 and a first epitaxial layer 3, and the second transistor is composed of the first epitaxial layer 3, the second epitaxial layer 2 and a substrate 1.
[0039] The third implantation region 9, together with the first epitaxial layer 3, the second epitaxial layer 2 and the substrate 1, forms an SCR structure, and the second implantation region 6, together with the first epitaxial layer 3, the second epitaxial layer 2 and the substrate 1, forms an SCR structure.
[0040] Example 3
[0041] The difference between Embodiment 3 and Embodiment 2 is that a third injection region 9 is provided at a distance from the first injection region 5 on the side away from the second injection region 6. Both the second injection region and the third injection region 9 are located in the well region 4, and the third injection region 9 is of the second doping type.
[0042] The first transistor is composed of a well region 4, a first injection region 5 and a first epitaxial layer 3, and the second transistor is composed of the first epitaxial layer 3, the second epitaxial layer 2 and a substrate 1.
[0043] The second implantation region 6, the well region 4, the first epitaxial layer 3, the second epitaxial layer 2, and the substrate 1 constitute an SCR structure.
[0044] The third injection region 9, the well region 4, the first epitaxial layer 3, the second epitaxial layer 2, and the substrate 1 form an SCR structure.
[0045] Example 4
[0046] The difference between Embodiment 4 and Embodiment 1 is that the second injection region 6 is disposed in the trap region 4, in this embodiment of the application.
[0047] The first transistor is composed of a well region 4, a first injection region 5 and a first epitaxial layer 3, and the second transistor is composed of the first epitaxial layer 3, the second epitaxial layer 2 and the substrate 1. The second injection region 6, the well region 4, the first epitaxial layer 3, the second epitaxial layer 2 and the substrate 1 form an SCR structure.
[0048] Example 5
[0049] Based on embodiment 4, a fourth injection region 10 is provided on the side of the second injection region 6 away from the first injection region 5. The fourth injection region 10 is disposed in the well region 4 and is of the first doping type.
[0050] The first transistor is composed of a fourth injection region 10, a well region 4, and a first epitaxial layer 3, while the second transistor is composed of the first epitaxial layer 3, a second epitaxial layer 2, and a substrate 1.
[0051] The SCR structure consists of a second implantation region 6, a well region 4, a first epitaxial layer 3, a second epitaxial layer 2, and a substrate 1.
[0052] The equivalent circuit diagrams obtained from Examples 1 to 5 above are as follows: Figure 6 As shown, if the first doping type is N-type and the second doping type is P-type, from the equivalent circuit... Figure 6 From this, we can see that both the first and second transistors are NPN transistors, and the SCR structure is composed of PNP and NPN transistors.
[0053] This application provides a transient voltage suppression protection device that solves the problems of high trigger and clamping voltages and large dynamic impedance in existing products with low lateral capacitance TVS. It produces a low-cost, area-saving, and simple-to-process vertically low-capacitance high-performance transient voltage suppression protection device that can operate at a lower voltage and has advantages such as low clamping voltage, low dynamic impedance, and low capacitance. Furthermore, this application uses a highly doped substrate and a double epitaxial layer, where the second epitaxial layer is a high-resistivity epitaxial layer (>5 ohm·cm). By using a high-resistivity substrate as a common collector and connecting two floating base regions of transistors in series, this series design halves the capacitance. Simultaneously, an ultra-low trigger voltage SCR structure is connected in parallel, utilizing the semiconductor punch-through characteristic to solve the problem of the unidirectional cutoff characteristic of high-resistivity substrate transistors preventing the device from being used independently. This application halves the device capacitance by using two vertically series NPN transistors, thus obtaining a smaller capacitance. The parallel connection of the ultra-low trigger voltage vertical SCR structure creates a low-capacitance transient voltage suppression protection device, meeting the specific protection device requirements of customers in practical applications.
[0054] Although the present invention has been described in detail above with general descriptions and specific embodiments, modifications or improvements can be made to it, which will be obvious to those skilled in the art. Therefore, all such modifications or improvements made without departing from the spirit of the present invention fall within the scope of protection claimed by the present invention.
Claims
1. A transient voltage suppression and protection device, characterized in that, include: The structure of the first transistor, the second transistor, and the SCR; The first transistor and the second transistor are connected in series, and the first transistor and the second transistor are connected in parallel with the SCR structure; The first transistor includes a well region, a first implantation region, and a first epitaxial layer; the second transistor includes the first epitaxial layer, a second epitaxial layer, and a substrate. A second epitaxial layer, a first epitaxial layer, and a well region are sequentially disposed above the substrate, and the first implantation region is disposed in the well region; The first implantation region, the first epitaxial layer, and the substrate are of the first doping type, and the well region and the second epitaxial layer are of the second doping type; The SCR structure includes a second implantation region, a first epitaxial layer, a second epitaxial layer, and a substrate. The second implantation region is disposed in the first epitaxial layer and is of a second doping type.
2. The transient voltage suppression and protection device as described in claim 1, characterized in that, A third injection region is provided on the side of the first injection region away from the second injection region. The third injection region is disposed in the first epitaxial layer and is of the second doping type.
3. The transient voltage suppression and protection device as described in claim 1, characterized in that, A third injection region is provided on the side of the first injection region away from the second injection region. Both the first injection region and the third injection region are located in the well region. The third injection region is of the second doping type.
4. A transient voltage suppression and protection device as described in claim 1, characterized in that, The second injection region is located in the well region.
5. A transient voltage suppression and protection device as described in claim 4, characterized in that, A fourth injection region is provided on the side of the second injection region away from the first injection region. The fourth injection region is located in the well region and is of the first doping type.
6. A transient voltage suppression and protection device as described in any one of claims 1 to 5, characterized in that, The first doping type is N-type, and the second doping type is P-type.
7. A transient voltage suppression and protection device as described in claim 6, characterized in that, The resistivity of the second epitaxial layer is greater than 5.