A three-dimensional interconnect structure based on wafer bump and gradient CTE transition
By forming a trapezoidal cavity through laser etching on a rigid board and combining it with copper pillar bumps and gold-plated bumps through thermo-press bonding, the problems of insufficient interconnect density, long signal transmission path, impedance mismatch and thermal stress failure in traditional packaging are solved, thus achieving optimization of high-density wiring and high-frequency signal transmission.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- 广西华芯振邦半导体有限公司
- Filing Date
- 2025-07-24
- Publication Date
- 2026-06-05
AI Technical Summary
Traditional packaging suffers from insufficient interconnect density between rigid and flexible boards, long signal transmission paths, impedance mismatch, thermal stress failure, and high-frequency loss, especially in multi-chip systems and high-frequency millimeter-wave bands.
Employing a three-dimensional interconnect structure based on wafer bumps and gradient CTE transition, a trapezoidal cavity is formed by laser etching on a rigid board. The chip is flip-chip bonded to a copper bump array on a flexible board and embedded into the cavity by folding the flexible board. The copper pillar bumps and gold-plated bumps are thermo-pressed together to adapt to thermal expansion differences, and the venting hole design avoids stress concentration.
It achieves synergistic optimization of high-density wiring, improved thermomechanical reliability and high-frequency signal transmission in semiconductor packaging, solves the problems of insufficient interconnect density and thermal stress failure in traditional packaging, and reduces high-frequency loss.
Smart Images
Figure CN224329900U_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor packaging technology, specifically a three-dimensional interconnect structure based on wafer bumps and gradient CTE transition. Background Technology
[0002] In traditional packaging, flexible boards and rigid boards are often connected by planar lamination or connectors, resulting in long signal transmission paths and impedance mismatch.
[0003] Insufficient interconnect density: Traditional wire bonding or planar mounting cannot meet the interconnect requirements of multi-chip systems (such as HBM+GPU);
[0004] Thermal stress failure: Mismatch between the rigid board and the chip CTE leads to solder joint cracking (such as the UBM layer falling off in a Flip-Chip package).
[0005] High-frequency loss: impedance abrupt change at the connection between rigid and flexible boards (e.g., return loss > 10dB in the 5G millimeter wave band). Utility Model Content
[0006] The purpose of this invention is to provide a three-dimensional interconnect structure based on wafer bumps and gradient CTE transition. The cavity structure is laser-etched on a rigid board, and the chip is flip-chip bonded to the copper bump array on a flexible board. After the flexible board is folded, the chip is embedded in the cavity. This invention is suitable for scenarios such as chiplet heterogeneous integration, 2.5D / 3D packaging, and high-frequency millimeter-wave devices. It solves the problems of high-density wiring, thermomechanical reliability, and high-frequency signal transmission coordination optimization in semiconductor packaging, thereby addressing the aforementioned background issues.
[0007] To achieve the above objectives, this utility model provides the following technical solution:
[0008] A three-dimensional interconnect structure based on wafer bumps and gradient CTE transition includes a rigid board and a chip. The rigid board is formed into a trapezoidal cavity by a laser etching process, and the bottom of the cavity is etched to form an exhaust hole that penetrates the rigid board.
[0009] A flexible plate is disposed below the chip, and a copper pillar bump is formed on the top of the flexible plate by electroplating. The chip is connected to the flexible plate through the copper pillar bump.
[0010] The top of the trapezoidal cavity forms a copper pad array through an electroplating process, and the bottom of the flexible plate forms gold-plated bumps at the position corresponding to the copper pad array through an electroplating process. The gold-plated bumps and the copper pad array are connected by thermo-press bonding.
[0011] As a further technical solution of this utility model, the side of the trapezoidal cavity is a trapezoidal groove structure, and the depth of the trapezoidal cavity is 150-300μm. The two sides of the trapezoidal cavity adopt an asymmetrical structure, with a long side and a short side respectively. The inclination angle of the long side wall is 60° and the inclination angle of the short side wall is 70°, which can adapt to the thermal expansion difference in different directions. The bottom corner of the trapezoidal cavity is rounded with a radius of 20-50μm to avoid stress concentration.
[0012] As a further technical solution of this utility model, the exhaust hole is a through hole with a diameter of 30-50μm, and the exhaust holes are distributed at the four corners of the bottom surface of the trapezoidal cavity, 100-150μm away from the edge, which can avoid stress concentration. At the same time, the exhaust hole is used to discharge air when the flexible board 5 is bonded. The gas is discharged directly vertically, avoiding lateral diffusion in the multilayer board and avoiding air bubble residue.
[0013] As a further technical solution of this utility model, the chip is bonded to the copper pillar bumps of the flexible board by tin-silver solder, and conductive adhesive is filled between the chip and the flexible board to improve thermal fatigue life and maintain high-frequency impedance consistency.
[0014] As a further technical solution of this utility model, the flexible plate is folded from the surface of the rigid plate toward the trapezoidal cavity, and the two ends of the flexible plate are folded back and embedded into the interior of the trapezoidal cavity; after the combination between the chip and the flexible plate is embedded into the trapezoidal cavity, the surface of the chip is flush with the top of the rigid plate.
[0015] Compared with the prior art, the beneficial effects of this utility model are:
[0016] This invention involves laser etching a cavity structure on a rigid board, flip-chip bonding it to a copper bump array on a flexible board, and embedding the chip into the cavity after the flexible board is folded. It is suitable for scenarios such as chiplet heterogeneous integration, 2.5D / 3D packaging, and high-frequency millimeter-wave devices, and solves the problems of high-density wiring, thermomechanical reliability, and high-frequency signal transmission co-optimization in semiconductor packaging. Attached Figure Description
[0017] Figure 1 This is a schematic diagram of the overall structure of this utility model.
[0018] Figure 2 This is a schematic diagram of the trapezoidal cavity and exhaust hole forming in this utility model.
[0019] Figure 3 This is a schematic diagram of the connection between the chip and the flexible board in this utility model.
[0020] Figure 4 This is a schematic diagram of the flexible plate after bending in this utility model.
[0021] Figure 5 This is a schematic diagram of the connection between the flexible plate and the rigid plate in this utility model.
[0022] In the diagram: 1-rigid board, 2-trapezoidal cavity, 3-vent hole, 4-chip, 5-flexible board, 6-copper pillar bump, 7-copper pad array, 8-gold-plated bump. Detailed Implementation
[0023] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.
[0024] Please see Figure 1 In this embodiment of the present invention, a three-dimensional interconnect structure based on wafer bumps and gradient CTE transition includes a rigid board 1 and a chip 4. The rigid board 1 is formed into a trapezoidal cavity 2 by a laser etching process, and the bottom of the cavity 2 is etched to form an exhaust hole 3 that penetrates the rigid board 1.
[0025] A flexible plate 5 is disposed below the chip 4, and a copper pillar protrusion 6 is formed on the top of the flexible plate 5 by electroplating. The chip 4 is connected to the flexible plate 5 through the copper pillar protrusion 6.
[0026] The top of the trapezoidal cavity 2 is formed with a copper pad array 7 through an electroplating process. The bottom of the flexible plate 5, corresponding to the position of the copper pad array 7, is formed with gold-plated bumps 8 through an electroplating process. The gold-plated bumps 8 and the copper pad array 7 are connected by thermo-press bonding.
[0027] In this example, the side of the trapezoidal cavity 2 is a trapezoidal groove structure, and the depth of the trapezoidal cavity 2 is 150-300μm. The two sides of the trapezoidal cavity 2 adopt an asymmetrical structure, with one long side and one short side respectively. The inclination angle of the long side wall is 60° and the inclination angle of the short side wall is 70°, which can adapt to the difference in thermal expansion in different directions. The bottom corner of the trapezoidal cavity 2 is rounded with a radius of 20-50μm to avoid stress concentration.
[0028] In this example, the vent hole 3 is a through hole with a diameter of 30-50μm, and the vent hole 3 is distributed at the four corners of the bottom surface of the trapezoidal cavity 2 at a distance of 100-150μm from the edge, which can avoid stress concentration. At the same time, the vent hole 3 is used to discharge air when the flexible board 5 is bonded. The gas is discharged directly vertically, avoiding lateral diffusion in the multilayer board and avoiding air bubble residue.
[0029] In this example, the chip 4 is bonded to the copper pillar bumps 6 of the flexible board 5 by tin-silver solder, and conductive adhesive is filled between the chip 4 and the flexible board 5 to improve thermal fatigue life and maintain high-frequency impedance consistency.
[0030] In this example, the flexible plate 5 is folded from the surface of the rigid plate 1 toward the trapezoidal cavity 2, and the two ends of the flexible plate 5 are folded back and embedded into the interior of the trapezoidal cavity 2; after the combination between the chip 4 and the flexible plate 5 is embedded into the trapezoidal cavity 2, the surface of the chip 4 is flush with the top of the rigid plate 1.
[0031] In this example, the process of forming the trapezoidal cavity 2 and the vent 3 includes the following steps:
[0032] Step 1: Surface pretreatment of rigid plate. First, plasma cleaning is performed on the surface of rigid plate 1 to remove organic contaminants, thereby improving the laser absorption rate. Then, an ultraviolet absorption layer is spin-coated to enhance the laser energy coupling efficiency.
[0033] Step 2: Laser roughing (forming a trapezoidal contour). A laser with a power of 8W (energy density 3.2J / cm²), a repetition frequency of 100kHz, and a scanning speed of 500mm / s is used for processing in a spiral progressive path (diffusion from the cavity center outwards). When processing at an angle, the laser incident angle is changed by dynamic focusing modulation: 60° incident angle on the long side (achieved by lifting the Z-axis by 0.29μm / scan line), and 70° incident angle on the short side (achieved by lifting the Z-axis by 0.21μm / scan line).
[0034] Step 3: Fine finishing and sidewall polishing. After the above steps are completed, the laser power is reduced to 5W (energy density 2.0J / cm²), the tracing speed is increased to 800mm / s, and a ring spot pattern (outer diameter 25μm, inner diameter 15μm) is used for processing to reduce the roughness of the sidewall.
[0035] Step 4: Roughness and fillet verification. Roughness and fillet are measured by white light interferometer and SEM respectively. The side wall roughness Ra < 1μm and the bottom fillet R = 30±5μm are required.
[0036] Step 5: Exhaust hole machining. Using coaxial vision positioning technology, drill 40μm diameter through holes at the four corners of the cavity, penetrating the hard plate 1.
[0037] Step 6: Slag removal treatment, ultrasonic cleaning with DI water + 0.1% TMAH (DI water + 0.1% TMAH, 40kHz, 5min), and then removal of carbides by plasma etching (CF4 / O2, 50W, 1min).
[0038] Furthermore, the bending process of the flexible plate 5 includes the following methods:
[0039] First bend (vertical downward bend)
[0040] Objective: To bend the flexible plate downwards from the surface of the rigid plate and initially embed it into the trapezoidal cavity 2;
[0041] 1. Use a precision clamp to hold the flexible plate 5, and first bend it 90° with a radius of 0.8mm to pre-form it;
[0042] 2. The flexible plate 5 is bent downwards at 90° from the starting point of the 60° inclined wall at the edge of the cavity to complete the initial embedding into the trapezoidal cavity;
[0043] Second bend (horizontal inward bend)
[0044] Objective: To bend the flexible plate 5 horizontally inward so that the chip 4 is fully embedded in the cavity, forming a "U" shaped structure;
[0045] 1. Align chip 4 with trapezoidal cavity 2 using a vacuum nozzle;
[0046] 2. The flexible board 5 is bent inward by 180° horizontally, so that the chip 4 is completely embedded in the trapezoidal cavity 2, forming a "U" shaped structure, with a specific length reserved at the edge for reliable bonding with the rigid board 1.
[0047] In this example, the forming process of the copper pillar bump 6 mainly includes the following steps:
[0048] Substrate pretreatment: Organic matter and oxides on the surface of flexible board 5 are removed by plasma cleaning; and Ti or Cu is sputtered on the surface as a seed layer for electroplating to form UBM of copper pillar bumps;
[0049] Thick photoresist pattern preparation: After coating with thick photoresist, the area to be prepared as copper pillars is exposed through pre-baking, exposure, development, and post-baking.
[0050] Copper pillar electroplating: Copper is electroplated in the patterned area of UBM that is not covered by photoresist to form a copper pillar of the required height;
[0051] Photoresist removal: Photoresist is removed using chemical solvents or plasma cleaning;
[0052] Seed layer removal: Use an appropriate etching solution to remove excess metal seed layer, ensuring that the already formed copper pillars and solder layer are not damaged.
[0053] In this example, the forming process of the gold-plated bump 8 is basically the same as that of the copper pillar bump 6, and the gold-plated bump 8 is electroplated using a chemical gold plating process.
[0054] It will be apparent to those skilled in the art that this invention is not limited to the details of the exemplary embodiments described above, and that it can be implemented in other specific forms without departing from the spirit or essential characteristics of this invention. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this invention is defined by the appended claims rather than the foregoing description. Thus, it is intended that all variations falling within the meaning and scope of equivalents of the claims be included within this invention. No reference numerals in the claims should be construed as limiting the scope of the claims.
[0055] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.
Claims
1. A three-dimensional interconnect structure based on wafer bumps and gradient CTE transition, characterized in that: Includes a rigid board (1) and a chip (4). The rigid board (1) forms a trapezoidal cavity (2) through a laser etching process, and the bottom of the cavity (2) is etched to form an exhaust hole (3) that penetrates the rigid board (1). A flexible plate (5) is provided below the chip (4), and a copper pillar protrusion (6) is formed on the top of the flexible plate (5) by electroplating. The chip (4) is connected to the flexible plate (5) through the copper pillar protrusion (6). The top of the trapezoidal cavity (2) is formed with a copper pad array (7) through an electroplating process. The bottom of the flexible plate (5) is formed with gold-plated bumps (8) at the position corresponding to the copper pad array (7) through an electroplating process. The gold-plated bumps (8) and the copper pad array (7) are connected by thermo-press bonding.
2. The three-dimensional interconnect structure based on wafer bumps and gradient CTE transition according to claim 1, characterized in that: The trapezoidal cavity (2) has a trapezoidal groove structure on its side and a depth of 150-300μm. The trapezoidal cavity (2) has an asymmetrical structure on both sides, with a long side and a short side respectively. The inclination angle of the long side wall is 60° and the inclination angle of the short side wall is 70°. The corner of the bottom of the trapezoidal cavity (2) is rounded with a radius of 20-50μm.
3. The three-dimensional interconnect structure based on wafer bumps and gradient CTE transition according to claim 1, characterized in that: The exhaust hole (3) is a through hole with a diameter of 30-50μm, and the exhaust hole (3) is distributed at the four corners of the bottom surface of the trapezoidal cavity (2) at a distance of 100-150μm from the edge.
4. The three-dimensional interconnect structure based on wafer bumps and gradient CTE transition according to claim 1, characterized in that: The chip (4) is bonded to the copper pillar bumps (6) of the flexible board (5) by tin-silver solder, and conductive adhesive is filled between the chip (4) and the flexible board (5).
5. A three-dimensional interconnect structure based on wafer bumps and gradient CTE transition according to claim 1, characterized in that: The flexible plate (5) is folded from the surface of the rigid plate (1) toward the trapezoidal cavity (2), and the two ends of the flexible plate (5) are folded back and embedded into the interior of the trapezoidal cavity (2); after the combination between the chip (4) and the flexible plate (5) is embedded into the trapezoidal cavity (2), the surface of the chip (4) is flush with the top of the rigid plate (1).