A screen testing device integrating multiple signal interfaces

Abstract

The utility model discloses a screen testing arrangement of integrated multi -signal interface, and the device is constituted by four parts of main control board, signal board, adapter plate and display control board. The utility model discloses through the innovative modular integration architecture, breaks through the technical bottleneck of traditional test equipment bulky, poor signal compatibility. Each module realizes high -speed data interaction through QSPI interface (main control board -signal board), MCU / GPIO interface (main control board -display control board). The utility model discloses through the all -integrated signal board design and power optimization architecture, compared with traditional equipment volume reduction 60%, signal compatibility improves 90%, can satisfy smart mobile phone, vehicle -mounted display etc. Multi -scene liquid crystal module high -precision test demand.

Description

Technical Field

[0001] This utility model relates to the field of screen testing technology, and in particular to a screen testing device integrating multiple signal interfaces. Background Technology

[0002] As a core component of modern display devices, the performance of LCD modules directly affects the quality of end products. With the development of new display technologies such as OLED and Mini-LED, LCD module interface types have evolved from a single LVDS to multiple protocols such as MIPI-CPHY / DPHY, eDP, RGB, and QSPI, placing higher demands on testing equipment. However, existing testing equipment has significant technical shortcomings:

[0003] Functional limitations: Traditional equipment only supports testing of a single or a few signal types, which cannot meet the requirements of simultaneous output and combined testing of multiple signals, and is difficult to adapt to the complex function verification of new LCD modules.

[0004] Bulk size: The power supply module and signal processing module are scattered, resulting in the device size generally exceeding 400mm×300mm×150mm, which occupies too much space in small-scale production workshops and increases the cost of use.

[0005] Insufficient compatibility: Insufficient support for new signal standards such as MIPI-CPHY v1.1 and DP 1.4, requiring frequent replacement of expansion cards, which not only reduces testing efficiency but also increases hardware maintenance costs.

[0006] Therefore, existing technologies have shortcomings and need to be improved. Utility Model Content

[0007] The technical problem to be solved by this utility model is to provide a screen testing device that integrates multiple signal interfaces, achieving high integration, small size and compatibility with multiple signal protocols, so as to meet the diverse testing needs of modern LCD modules.

[0008] The technical solution of this utility model is as follows: a screen testing device integrating multiple signal interfaces is provided, including: a main control board, a signal board, an adapter board and a display control board.

[0009] The main control board includes: a main control MCU chip, an external TF card interface, an RJ45 interface, a UART interface, two RS232 interfaces, two USB interfaces, a QSPI interface, a GPIO interface, and a power control module. The main control MCU chip is connected to the power control module via UART, outputting 7 adjustable positive voltage power supplies, 2 negative voltage power supplies, 1 LEDA power supply, 12 LEDK power supplies, and 9 feedback signal circuits to the adapter board. The main control MCU chip is connected to the signal board via the QSPI interface (speed ≥ 50MHz), and to the display control board via the MCU interface and GPIO interface. The main control MCU chip is model MIMXRT1052CVL5B, and the power control module is model HC32F460.

[0010] The signal board includes: a first FPGA (preferably XCKU3P-2FFVA676I), a second FPGA (preferably LIFCL-40-8BG400C), MIPI-CPHY / DPHY, LVDS, eDP, RGB, MCU, QSPI, and SPI signal interfaces; the first FPGA is connected to a 4-channel LVDS repeater and a 2-channel DP linear driver, and outputs signals through the LVDS repeater (preferably THC63LVD1027) and the DP linear driver (preferably SN65DP141); the second FPGA is connected to a 2-channel RGB interface, an MCU interface, and a QSPI / SPI configuration interface, and outputs signals to the adapter board through a bridge chip (preferably SSD2832) and a level conversion chip (preferably SN74LVC16T245);

[0011] The display control board integrates a 3.5-inch TFT display screen and four mechanical buttons, and connects to the main control MCU chip through MCU interface and GPIO interface to realize human-computer interaction;

[0012] The adapter board connects to the screen under test via an 80-PIN FPC connector, a 120-PIN B2B connector, and a DP socket, supporting customized signal adaptation.

[0013] The signal board, through a cascaded architecture of the first and second FPGAs, supports protocols such as MIPI-CPHY v1.1 (single channel rate ≤ 3.42Gbps), LVDS (single channel rate ≤ 1.0Gbps), eDP 1.4 (single channel rate ≤ 8.1Gbps), and RGB888 (frame rate ≤ 60Hz), and can synchronously output at least 5 different types of signals.

[0014] The main control board's power control module integrates 9 power outputs, 9 16-bit ADC voltage / current acquisitions, 9 power protection / discharge circuits, 2 MTP / VCOM operational amplifier topologies, and 12 LEDK operational amplifier current limiting circuits. It works in conjunction with a third FPGA (preferably GW2A-LV18QN88) and a high-speed ADC / DAC via an SPI interface to achieve precise power control and real-time monitoring.

[0015] The adapter board adopts a modular and replaceable design, integrating an 80PIN-FPC connector (for MIPI signals), a 120PIN-B2B connector (for LVDS / RGB / QSPI signals), and a DP socket, supporting quick switching to adapt to LCD modules of different sizes and interface types within 5 minutes.

[0016] The display control board is connected to the main control board through a real-time data interaction protocol, enabling real-time display of test voltage, current, and signal waveforms, and allowing the test process to be triggered and signal modes to be switched via buttons.

[0017] The main control board connects to the signal board via QSPI headers to achieve high-speed data interaction; the main control board connects to the display control board via a 40-pin ribbon cable to transmit control signals and test data.

[0018] The signal board connects to the adapter board's 80-PIN FPC connector (transmitting MIPI signals) via an FPC cable, and to the 120-PIN B2B connector (transmitting LVDS / RGB / QSPI signals) via a board-to-board connector.

[0019] The adapter board connects to the flexible circuit board (FPC) of the screen under test via a connector to achieve physical connection and signal transmission.

[0020] The main control MCU chip achieves remote feedback compensation through a 9-channel operational amplifier topology circuit. In conjunction with the power control module (using the HC32F460 chip), the power ripple is controlled to ≤50mV, ensuring power supply stability and accuracy.

[0021] By adopting the above solution, this utility model provides a screen testing device integrating multiple signal interfaces, which has the following technical effects:

[0022] Highly integrated design: Power supply, signal processing, and human-machine interaction modules are integrated into a space of 200mm×150mm×50mm, reducing the size of traditional equipment by 60%; an FPGA + bridge chip + repeater hierarchical architecture is used to replace discrete expansion boards, reducing 3-5 boards and lowering equipment complexity and failure rate.

[0023] Multi-protocol compatibility: A single device supports 8 signal types, including MIPI-CPHY / DPHY, LVDS, eDP, RGB, MCU, QSPI, SPI, and DP, covering 12 mainstream industry interface standards (including MIPI-CPHY v1.1 and MIPI-DPHY v1.1 defined by the MIPI Alliance, eDP 1.4 and DP 1.4 of the VESA standard, and the LVDS interface specification defined by JEDEC, etc.).

[0024] Precise and reliable control: The power module employs 9 independent sampling channels of 16-bit ADCs (accuracy up to 0.024%) and dynamic adjustment of the DAC (resolution 0.1%), with voltage output accuracy ≤ ±1%; signal transmission adopts impedance matching design (LVDS impedance 100Ω, MIPI impedance 50Ω), with a bit error rate ≤ 10%. -6 This ensures the accuracy and stability of the test data.

[0025] Easy and efficient operation: The display control board provides a graphical user interface and visual guidance for the testing process, reducing operator training costs; the adapter board adopts blind-plug connectors and a foolproof design to avoid misoperation and improve testing efficiency and safety. Attached Figure Description

[0026] Figure 1 This is a functional block diagram of one embodiment of the present utility model;

[0027] Figure 2 is the circuit topology diagram of the main control board power module;

[0028] Figure 3 shows the FPGA cascade architecture of the signal board;

[0029] Figure 4 The circuit schematic for the LEDK power supply;

[0030] Figure 5 The circuit schematic for the LEDA power supply;

[0031] Figure 6 The circuit schematic for the feedback signal circuit;

[0032] Figure 7 Circuit diagram for a negative voltage power supply;

[0033] Figure 8 The circuit diagram is for a positive voltage power supply. Detailed Implementation

[0034] The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0035] Please see Figures 1-8 This embodiment provides a screen testing device integrating multiple signal interfaces, including: a main control board 51, a signal board 52, an adapter board 53, and a display control board 54.

[0036] The main control board 51 includes: a main control MCU chip 10, an external TF card interface, an RJ45 interface 11, a UART interface 12, two RS232 interfaces 13, two USB interfaces 14, a QSPI interface 15, a GPIO interface, and a power control module 18. The main control MCU chip 10 is connected to the power control module 18 via UART, outputting 7 adjustable positive voltage power supplies 81, 2 negative voltage power supplies 82, 1 LEDA power supply 83, 12 LEDK power supplies 84, and 9 feedback signal circuits 85 to the adapter board 53. The main control MCU chip 10 is connected to the signal board 52 via the QSPI interface 15 (speed ≥ 50MHz), and the main control MCU chip 10 is connected to the display control board 54 via the MCU interface and the GPIO interface. The main control MCU chip 10 uses the MIMXRT1052CVL5B chip, and the power control module 18 uses the HC32F460 chip. The external TF card interface is used to install a TF card.

[0037] The signal board 52 includes: a first FPGA 19 (preferably XCKU3P-2FFVA676I), a second FPGA 20 (preferably LIFCL-40-8BG400C), and MIPI-CPHY / DPHY, LVDS, eDP, RGB, MCU, QSPI, and SPI signal interfaces; the first FPGA 19 is connected to a 4-channel LVDS repeater 21 and a 2-channel DP linear driver 22, and outputs signals through the LVDS repeater 21 (preferably THC63LVD1027) and the DP linear driver 22 (preferably SN65DP141); the second FPGA 20 is connected to a 2-channel RGB interface and a QSPI / SPI configuration interface, and outputs signals to the adapter board 53 through a bridge chip 23 (preferably SSD2832) and a level conversion chip 24 (preferably SN74LVC16T245);

[0038] The display control board 54 integrates a 3.5-inch TFT display screen and four mechanical buttons, and is connected to the main control MCU chip 10 through the MCU interface and GPIO interface to realize human-computer interaction;

[0039] The adapter board 53 is connected to the screen under test 28 via an 80-PIN FPC connector 25, a 120-PIN B2B connector 26, and a DP socket 27, supporting customized signal adaptation.

[0040] The signal board 52, through a cascaded architecture of the first FPGA 19 and the second FPGA 20, supports protocols such as MIPI-CPHY v1.1 (single channel rate ≤ 3.42Gbps), LVDS (single channel rate ≤ 1.0Gbps), eDP 1.4 (single channel rate ≤ 8.1Gbps), and RGB 888 (frame rate ≤ 60Hz), and can synchronously output at least 5 different types of signals.

[0041] The power control module 18 of the main control board 51 integrates 9 power outputs, 9 16-bit ADC voltage / current acquisitions, 9 power protection / discharge circuits, 2 MTP / VCOM operational amplifier topologies, and 12 LEDK operational amplifier current limiting circuits. It works in conjunction with the third FPGA 29 (preferably GW2A-LV18QN88) and high-speed ADC / DAC through the SPI interface to achieve precise power control and real-time monitoring.

[0042] The adapter board 53 adopts a modular and replaceable design, integrating an 80PIN-FPC connector 25 (for MIPI signals), a 120PIN-B2B connector 26 (for LVDS / RGB / QSPI signals), and a DP socket 27, supporting rapid switching to adapt to LCD modules of different sizes and interface types within 5 minutes.

[0043] The display control board 54 is connected to the main control board 51 through a real-time data interaction protocol, enabling real-time display of test voltage, current, and signal waveforms, and triggering the test process and switching signal modes via buttons.

[0044] The main control board 51 is connected to the signal board 52 via QSPI headers to achieve high-speed data interaction; the main control board 51 is connected to the display control board 54 via a 40-pin ribbon cable to transmit control signals and test data.

[0045] The signal board 52 is connected to the 80-pin FPC connector 25 of the adapter board 53 via an FPC cable (for transmitting MIPI signals), and is connected to the 120-pin B2B connector 25 via a board-to-board connector (for transmitting LVDS / RGB / QSPI signals).

[0046] The adapter board 53 connects to the flexible circuit board (FPC) of the screen under test via a connector to achieve physical connection and signal transmission.

[0047] The main control MCU chip 10 implements remote feedback compensation through a 9-channel operational amplifier topology circuit. Together with the power control module 18 (using the HC32F460 chip), it controls the power ripple to ≤50mV, ensuring power supply stability and accuracy.

[0048] The testing process is as follows:

[0049] Step 1: Mode Selection and Program Loading: The operator selects the test mode (such as "MIPI-DPHY Single Channel Test") via the buttons on the display control board 54. The main control board 51 reads the corresponding test program from the TF card and completes the system initialization.

[0050] Step 2: Power and signal output: The main control board 51 triggers the first FPGA 19 of the signal board 52 to generate an LVDS test pattern (such as a checkerboard) through the QSPI instruction, and at the same time controls the power module to output a 5V positive voltage to the module logic circuit to provide stable power supply for testing.

[0051] Step 3: Signal conversion and transmission: The second FPGA 20 of the signal board 52 outputs 24-bit color depth image data through the RGB interface, which is converted into MIPI-CPHY signal by the bridge chip (SSD2832) and transmitted to the screen under test 28 through the adapter board 53 to realize multi-signal collaborative testing.

[0052] Step 4: Data Feedback and Anomaly Handling: The display control board 54 receives the brightness and chromaticity data fed back by the module in real time and displays it in the form of a waveform graph; if an anomaly is detected (such as uneven brightness), the main control board 51 immediately cuts off the power and triggers an audible and visual alarm to ensure test safety.

[0053] Maintenance and upgrade

[0054] The power module supports online firmware upgrades (ISP), updating the MCU2 program via the USB interface to optimize the power control algorithm and expand its functions.

[0055] The FPGA program for the signal board can be remotely downloaded via the RJ45 interface, supporting in-system programming for testing and upgrading, facilitating rapid adaptation to new signal protocols.

[0056] In summary, this utility model provides a screen testing device integrating multiple signal interfaces, which has the following technical effects:

[0057] Highly integrated design: Power supply, signal processing, and human-machine interaction modules are integrated into a space of 200mm×150mm×50mm, reducing the size of traditional equipment by 60%; an FPGA + bridge chip + repeater hierarchical architecture is used to replace discrete expansion boards, reducing 3-5 boards and lowering equipment complexity and failure rate.

[0058] Multi-protocol compatibility: A single device supports 8 signal types, including MIPI-CPHY / DPHY, LVDS, eDP, RGB, MCU, QSPI, SPI, and DP, covering 12 mainstream industry interface standards (including MIPI-CPHY v1.1 and MIPI-DPHY v1.1 defined by the MIPI Alliance, eDP 1.4 and DP 1.4 of the VESA standard, and the LVDS interface specification defined by JEDEC, etc.).

[0059] Precise and reliable control: The power module employs 9 independent sampling channels of 16-bit ADCs (accuracy up to 0.024%) and dynamic adjustment of the DAC (resolution 0.1%), with voltage output accuracy ≤ ±1%; signal transmission adopts impedance matching design (LVDS impedance 100Ω, MIPI impedance 50Ω), with a bit error rate ≤ 10%. -6 This ensures the accuracy and stability of the test data.

[0060] Easy and efficient operation: The display control board provides a graphical user interface and visual guidance for the testing process, reducing operator training costs; the adapter board adopts blind-plug connectors and a foolproof design to avoid misoperation and improve testing efficiency and safety.

[0061] The above are merely preferred embodiments of the present utility model and are not intended to limit the present utility model. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present utility model should be included within the protection scope of the present utility model.

Claims

1. A screen testing device integrating multiple signal interfaces, characterized in that, include: Main control board, signal board, adapter board and display control board, including: The main control board includes: a main control MCU chip, an external TF card interface, an RJ45 interface, a UART interface, an RS232 interface, a USB interface, a QSPI interface, and a GPIO interface, and a power control module; the main control MCU chip is connected to the power control module via UART, outputting adjustable positive voltage power, negative voltage power, LEDA power, LEDK power, and feedback signal circuits to the adapter board; the main control MCU chip is connected to the signal board via the QSPI interface, and the main control MCU chip is connected to the display control board via the MCU interface and the GPIO interface; The signal board includes: a first FPGA, a second FPGA, MIPI-CPHY / DPHY, LVDS, eDP, RGB, MCU, QSPI, and SPI signal interfaces; the first FPGA is connected to an LVDS repeater and a DP 1.4 transmitter, and outputs signals through the LVDS repeater and DP linear driver; the second FPGA is connected to an RGB interface and a QSPI / SPI configuration interface, and outputs signals to the adapter board through a bridge chip and a level conversion chip; The display control board integrates a TFT display screen and mechanical buttons, and connects to the main control MCU chip through MCU interface and GPIO interface to realize human-computer interaction; The adapter board is connected to the screen under test via an FPC connector, a B2B connector, and a DP socket.

2. The screen testing device integrating multiple signal interfaces according to claim 1, characterized in that, The signal board, through a cascaded architecture of the first and second FPGAs, supports MIPI-CPHY v1.1, LVDS, eDP 1.4, and RGB 888 protocols, and can synchronously output at least 5 different types of signals.

3. The screen testing device integrating multiple signal interfaces according to claim 1, characterized in that, The main control board's power control module integrates power output, 16-bit ADC voltage / current acquisition, power protection / discharge circuit, MTP / VCOM operational amplifier topology circuit, and LEDK operational amplifier current limiting circuit. It works in conjunction with a third FPGA and high-speed ADC / DAC through the SPI interface to achieve precise power control and real-time monitoring.

4. The screen testing device integrating multiple signal interfaces according to claim 1, characterized in that, The adapter board adopts a modular and replaceable design, integrating FPC connectors, B2B connectors and DP sockets, and supports quick switching to adapt to LCD modules of different sizes and interface types within 5 minutes.

5. The screen testing device integrating multiple signal interfaces according to claim 1, characterized in that, The display control board is connected to the main control board through a real-time data interaction protocol, enabling real-time display of test voltage, current, and signal waveforms, and allowing the test process to be triggered and signal modes to be switched via buttons.

6. The screen testing device integrating multiple signal interfaces according to claim 1, characterized in that, The main control board connects to the signal board via QSPI headers to achieve high-speed data interaction; the main control board connects to the display control board via ribbon cables to transmit control signals and test data.

7. The screen testing device integrating multiple signal interfaces according to claim 1, characterized in that, The signal board is connected to the FPC connector of the adapter board via an FPC cable, and to the B2B connector via a board-to-board connector.

8. The screen testing device integrating multiple signal interfaces according to claim 1, characterized in that, The adapter board connects to the flexible circuit board of the screen under test via a connector, achieving physical connection and signal transmission.

9. The screen testing device integrating multiple signal interfaces according to claim 1, characterized in that, The main control MCU chip achieves remote feedback compensation through operational amplifier topology circuit, and together with the power control module, controls the power ripple to ≤50mV, ensuring power supply stability and accuracy.

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