Display panel and display device
By using a cross-spaced spacer design and a reasonable arrangement of main and secondary spacers, the problems of transmittance and cell thickness unevenness of LCD panels under high resolution and low power consumption were solved, achieving a display effect with high transmittance and low power consumption.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- BOE TECHNOLOGY GROUP CO LTD
- Filing Date
- 2025-06-06
- Publication Date
- 2026-06-09
Smart Images
Figure CN224341758U_ABST
Abstract
Description
Technical Field
[0001] This disclosure belongs to the field of display technology, specifically relating to a display panel and a display device. Background Technology
[0002] With the rapid development of display technology, the types of display panels are becoming increasingly diverse, such as Organic Light-Emitting Diode (OLED) display panels, MicroLED, and Liquid Crystal Display (LCD) panels. For medium to large-sized display devices, newer display panels such as OLED and MicroLED have not been applied due to their high cost and low yield. Instead, LCD remains the mainstream display panel, dominating the market for medium to large-sized displays in TVs, automotive, and industrial control applications.
[0003] A liquid crystal display panel consists of a liquid crystal cell formed by assembling two upper and lower substrates, and liquid crystal molecules located between the liquid crystal cells. When assembling the two upper and lower substrates, a post spacer (PS) is required between the two substrates to maintain the cell thickness of the liquid crystal cell. Utility Model Content
[0004] The present invention aims to solve at least one of the technical problems existing in the prior art, and to provide a display panel and display device.
[0005] This disclosure provides a display panel including a first substrate and a second substrate disposed opposite to each other, with a liquid crystal layer and a spacer disposed between the first substrate and the second substrate; the first substrate includes a first substrate base, and a plurality of gate lines and a plurality of data lines disposed on the first substrate base; the gate lines extend along a first direction, and the data lines extend along a second direction; wherein...
[0006] The spacer includes a first spacer portion extending along the second direction and a second spacer portion extending along the first direction; the first spacer portion is disposed on the side of the first substrate near the second substrate; the second spacer portion is disposed on the side of the second substrate near the first substrate, and the orthographic projections of the first spacer portion and the second spacer portion on the first substrate are intersecting.
[0007] The second substrate includes a second substrate, and a black matrix layer and a color resist layer disposed on the second substrate.
[0008] The black matrix layer includes a plurality of first black matrices extending along the first direction and a plurality of second black matrices extending along the second direction; the first black matrices and the second black matrices are intersected to define a plurality of pixel openings; the color resist layer includes a plurality of color resists; one of the color resists is disposed in a pixel opening, and the orthographic projection of the color resist on the second substrate covers the orthographic projection of the pixel opening on the second substrate.
[0009] The first spacer portion includes a first surface and a second surface disposed opposite to each other along the thickness direction of the first substrate, and the first surface is disposed on the first substrate; the orthographic projection of the first surface on the first substrate is located on the orthographic projection of the second black matrix on the first substrate.
[0010] Each of the second spacers includes a third surface and a fourth surface disposed opposite to each other along the thickness direction of the first substrate, and the third surface is disposed on the second substrate; the orthographic projection of the third surface on the first substrate is located on the orthographic projection of the first black matrix on the first substrate.
[0011] The color resist includes a red resist, a green resist, and a blue resist; the second spacer overlaps with the orthographic projections of the red and blue resists on the first substrate, but does not overlap with the orthographic projection of the green resist on the first substrate.
[0012] Wherein, for the second spacer portion, there are overlapping red and blue color resists with its orthographic projection on the first substrate, wherein the minimum distance between the outer contour of the orthographic projection of the second spacer portion on the first substrate and the outer contour of the orthographic projection of the blue color resist on the first substrate is a, and the minimum distance between the outer contour of the orthographic projection of the second spacer portion on the first substrate and the outer contour of the orthographic projection of the red color resist on the first substrate is b, and a=b.
[0013] The first substrate further includes a common electrode line and a pixel unit disposed at the intersection of the gate line and the data line.
[0014] The pixel unit includes a thin-film transistor disposed on the first substrate, a common electrode and a pixel electrode disposed on the side of the thin-film transistor facing away from the first substrate;
[0015] The common electrode line is connected to the common electrode and is located between the common electrode and the layer containing the pixel electrode.
[0016] Two common electrode lines extending along the first direction are provided between the two rows of pixel units arranged side by side along the second direction, and the orthographic projection of the two common electrode lines on the first substrate is covered by the orthographic projection of the first black matrix on the first substrate.
[0017] The second spacer portion has a first side and a second side disposed opposite to each other along the second direction when projected onto the first substrate; the common electrode line has a third side and a fourth side disposed opposite to each other along the second direction when projected onto the first substrate.
[0018] For the two common electrode lines and the spacer located between the two rows of pixel units, one of the two common electrode lines is a first common electrode line and the other is a second common electrode line; the first side of the second spacer portion of the spacer falls on the third side of the first common electrode line, and the second side of the second spacer portion of the spacer falls on the fourth side of the second common electrode line.
[0019] The first substrate further includes a pixel unit disposed at the intersection of the gate line and the data line;
[0020] The pixel unit includes a thin-film transistor disposed on the first substrate, a common electrode and a pixel electrode disposed on the side of the thin-film transistor facing away from the first substrate; the gate of the thin-film transistor and the corresponding gate line are connected as an integral structure.
[0021] At least a portion of the spacer overlaps with the orthographic projection of the thin-film transistor onto the first substrate.
[0022] The gate of the thin-film transistor includes a fifth side and a sixth side disposed opposite to each other along the first direction; for the spacer and the thin-film transistor having overlapping orthographic projections on the first substrate, the orthographic projection of the first spacer portion of the spacer on the first substrate does not overlap with the orthographic projection of the fifth side on the first substrate, and covers the orthographic projection of the sixth side on the first substrate; the fourth surface of the second spacer portion of the spacer overlaps with the orthographic projection portion of the gate on the first substrate.
[0023] The first substrate further includes a pixel unit disposed at the intersection of the gate line and the data line;
[0024] The pixel unit includes a thin-film transistor disposed on the first substrate, a common electrode and a pixel electrode disposed on the side of the thin-film transistor facing away from the first substrate;
[0025] At least a portion of the spacer overlaps with the orthographic projection of the thin-film transistor onto the first substrate.
[0026] For the orthographic projection of the spacer and the thin-film transistor on the first substrate, the orthographic projection of the fourth surface of the second spacer portion of the spacer on the first substrate covers the orthographic projection of the drain of the thin-film transistor on the first substrate.
[0027] Wherein, at least a portion of the spacer overlaps with the orthographic projection of the data line on the first substrate;
[0028] For the spacers and the data line that overlap in their orthogonal projections on the first substrate, the centers of the orthogonal projections of the first spacer portion and the second spacer portion of the spacers on the first substrate are both penetrated by the orthogonal projection of the data line on the first substrate.
[0029] The first substrate further includes a pixel unit disposed at the intersection of the gate line and the data line;
[0030] The pixel unit includes a thin-film transistor disposed on the first substrate, a common electrode and a pixel electrode disposed on the side of the thin-film transistor facing away from the first substrate; the drain of the thin-film transistor is connected to the pixel electrode through a via penetrating the interlayer insulating layer.
[0031] At least a portion of the spacer overlaps with the orthographic projection of the thin-film transistor onto the first substrate.
[0032] For the orthographic projection of the spacer and the thin film transistor on the first substrate, there is an overlapping spacer and a fourth surface of the second spacer portion of the spacer on the first substrate, and an orthographic projection of the via connecting the drain of the thin film transistor to the pixel electrode on the first substrate.
[0033] The spacer includes a main spacer and a secondary spacer; the first spacer portion and the second spacer portion of the main spacer abut against each other; and the first spacer portion and the second spacer portion of the secondary spacer have a certain distance between them.
[0034] The first spacer portion includes a first surface and a second surface disposed opposite to each other along the thickness direction of the first substrate, and the first surface is disposed on the first substrate; each of the second spacers includes a third surface and a fourth surface disposed opposite to each other along the thickness direction of the first substrate.
[0035] The width of the second surface of the primary spacer along the first direction is smaller than the width of the second surface of the secondary spacer along the first direction.
[0036] The length of the fourth surface of the primary septum along the second direction is less than the length of the fourth surface of the secondary septum along the second direction.
[0037] The display panel is divided into a display area and a peripheral area; the display substrate also includes a frame adhesive located in the peripheral area and disposed between the first substrate and the second substrate, the frame adhesive surrounding the liquid crystal layer.
[0038] The peripheral area also includes redundant color resist and redundant black matrix located on the side of the frame adhesive near the display area, as well as redundant spacers disposed on the side of the redundant color resist and redundant black matrix near the display area.
[0039] This disclosure also provides a display device, which includes any of the display panels described above, and a backlight that provides a light source for the display panel. Attached Figure Description
[0040] Figure 1 This is a top view of a display panel.
[0041] Figure 2 This is a cross-sectional view of an exemplary display panel.
[0042] Figure 3 This is a cross-sectional view of the display panel according to an embodiment of the present disclosure.
[0043] Figure 4 This is a top view of the spacer of the display panel in this embodiment.
[0044] Figure 5 This is a top view of the peripheral area of the display panel in this embodiment.
[0045] Figure 6 This is a top view of the array substrate in the display panel of an embodiment of this disclosure.
[0046] Figure 7 This is a partial top view of the array substrate side of the display panel in an embodiment of the present disclosure.
[0047] Figure 8 for Figure 7 The cross-sectional view of A-A' shown.
[0048] Figure 9 for Figure 7 The cross-sectional view of B-B' shown.
[0049] Figure 10This is a partial top view of the color filter substrate side of the display panel in an embodiment of this disclosure.
[0050] Figure 11 This is a top view of the black matrix layer in an embodiment of this disclosure.
[0051] Figure 12 for Figure 10 The cross-sectional view of C-C' shown.
[0052] Figure 13 This is a top view of the secondary spacer according to an embodiment of the present disclosure.
[0053] Figure 14 This is a top view of the main spacer in an embodiment of this disclosure.
[0054] Figure 15 This is a top view of the main spacer and the secondary spacer according to an embodiment of the present disclosure.
[0055] Figure 16 This is a schematic diagram showing the relative positions of the spacer and the array substrate according to an embodiment of the present disclosure.
[0056] Figure 17 This is a schematic diagram showing the relative positions of the second septum portion and the color resist in an embodiment of this disclosure.
[0057] Figure 18 This is a schematic diagram showing the relative positions of the spacer and the gate in an embodiment of this disclosure.
[0058] Figure 19 This is a schematic diagram showing the relative positions of the spacer, data line, and thin-film transistor drain in an embodiment of this disclosure.
[0059] Figure 20 This is a schematic diagram showing the relative positions of the spacer and the via connecting the drain of the thin-film transistor and the pixel electrode in an embodiment of this disclosure.
[0060] Figure 21 This is a schematic diagram showing the relative positions of the septum and the common electrode line in an embodiment of this disclosure.
[0061] Figure 22 This is a schematic diagram showing the relative positions of the second spacer portion and the first black matrix in an embodiment of this disclosure.
[0062] Figure 23 This is a schematic diagram showing the relative positions of the first spacer portion and the second black matrix in an embodiment of this disclosure. Detailed Implementation
[0063] To enable those skilled in the art to better understand the technical solution of this utility model, the present utility model will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0064] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.
[0065] Structurally, a liquid crystal display (LCD) screen mainly consists of a backlight, a liquid crystal panel, and driving circuitry. The liquid crystal panel includes a color filter (CF) substrate and a TFT substrate mounted opposite each other, as well as liquid crystal molecules positioned between the CF and TFT substrates. Depending on their function, LCD panels can be divided into an active area (AA) and a peripheral area, such as... Figure 1 As shown. The display area includes a pixel array composed of several pixel units 100. Each pixel unit 100 consists of three sub-pixels (or dots) of red, green, and blue, represented by R, G, and B respectively. A sealant is formed around the display area. The main function of this sealant is to seal the liquid crystal within the liquid crystal cell formed by the CF substrate and the TFT substrate, and to bond the color filter substrate and the array substrate together.
[0066] Cross-sectional view of the display panel as follows Figure 2As shown, the display panel includes a color filter substrate and an array substrate disposed opposite each other. The array substrate may include a first substrate and a driving circuit structure disposed on the first substrate. The color filter substrate may include a second substrate 21 (e.g., glass), a black matrix (BM) layer 22, a color resist layer 23, and an overcoat (OC) layer 24. The black matrix layer 22 blocks stray light from the liquid crystal layer, preventing color mixing between subpixels and preventing ambient light from illuminating the TFT channel. The color resist layer 23 absorbs a portion of the spectrum of natural light, allowing only the matching monochromatic spectrum to pass through, forming the primary colors in color mixing. The overcoat layer 24 is a plane formed on the side of the BM layer 22 and the color resist layer 23 facing away from the second substrate 21. This facilitates the orientation of liquid crystal molecules while isolating heavy metal impurities in the color resist layer 23 from contacting and contaminating the liquid crystal molecules.
[0067] The volume of liquid crystal molecules is easily affected by ambient temperature; they expand when the temperature rises and contract when the temperature falls. This can easily lead to variations in the cell thickness formed by the CF substrate and TFT substrate, resulting in uneven cell thickness. Uneven cell thickness can cause uneven brightness and darkness in the display panel, affecting the display effect. To give the display panel a certain degree of resistance to temperature changes and maintain uniform cell thickness, or in other words, to have a wide liquid crystal redundancy, related technologies typically employ the placement of post spacers (PS) in the display area.
[0068] The spacer in display area AA, such as Figure 2 As shown, there are generally two types: one is the main spacer 51 (Main PS), which maintains the thickness of the liquid crystal cell under normal conditions, and the other is the sub-spacer 52 (Sub PS), which only provides support when subjected to external pressure. Depending on actual product requirements, the main spacer 51 and sub-spacer 52 are arranged in an orderly manner in the display area AA according to a certain layout rule and distribution density. The main spacer 51 has a certain elasticity and can be compressed to a certain extent when subjected to external pressure. Alternatively, the sub-spacer 52 may include multiple sub-spacers 52 of different heights to ensure that the liquid crystal cell has sufficient liquid crystal redundancy. In summary, the function of setting the main spacer 51 and sub-spacer 52 in the display area AA in related technologies is: 1. To ensure that the display panel has a certain resistance to temperature changes; 2. When the shape of the main spacer 51 and the liquid crystal dispensing volume fluctuate, the step difference between the main spacer 51 and sub-spacer 52 allows the display panel to have a wider liquid crystal redundancy, thus making mass production feasible. In addition, the bezel adhesive 4 of the peripheral area BA contains filler 41, such as silicon sphere particles or plastic sphere particles, which can also play a role in supporting and maintaining the thickness of the liquid crystal cell around the display area AA.
[0069] With the development of display technology and the growing awareness of low-carbon and environmental protection, the demand for high-resolution (PPI) and low-power display products is increasing. However, as resolution increases, subpixels become smaller, but due to manufacturing limitations, the spacer design cannot be infinitely reduced, resulting in a decreasing pixel aperture ratio. Therefore, providing a novel display panel design to improve pixel aperture ratio, enhance panel transmittance, and reduce backlight power consumption is a crucial technical challenge that urgently needs to be addressed.
[0070] In response to the above problems, Figure 3 This is a cross-sectional view of the display panel according to an embodiment of the present disclosure; as shown Figure 3 As shown, this disclosure provides a display substrate comprising a first substrate and a second substrate disposed opposite to each other, and a liquid crystal layer 3 and a spacer disposed between the first substrate and the second substrate. Figure 3 As shown, in this example, the septum includes a main septum 51 and a secondary septum 52.
[0071] Figure 4 This is a top view of the spacer of the display panel in this embodiment; as shown Figure 3 and 4 As shown, the spacer in this embodiment includes a first spacer portion 501 and a second spacer portion 502 disposed opposite to each other. The first spacer portion 501 is disposed on the side of the first substrate near the liquid crystal layer 3, and the second spacer portion 502 is disposed on the side of the second substrate near the liquid crystal layer 3. The projections of the first spacer portion 501 and the second spacer portion 502 onto the first substrate 11 are intersecting. The first spacer portion 501 extends along the column direction Y, and the second spacer portion 502 extends along the row direction X. In other words, the orthogonal projection of the spacer on the first substrate 11 in this embodiment forms a cross-shaped structure. This structure can maximize the pixel aperture ratio, thereby increasing the transmittance of the display panel, reducing backlight power consumption, and improving the pressure resistance of the display panel.
[0072] In this embodiment of the disclosure, the first substrate is an array substrate and the second substrate is a color filter substrate.
[0073] Figure 6 This is a top view of the array substrate in the display panel according to an embodiment of the present disclosure; Figure 7 This is a partial top view of the array substrate side of the display panel according to an embodiment of the present disclosure; Figure 8 for Figure 7 The cross-sectional view of A-A' shown below; Figure 9 for Figure 7 The cross-sectional view of B-B' shown; as Figure 6-9As shown, exemplarily, the array substrate of this embodiment may include a first substrate 11, a plurality of gate lines 12 extending in a first direction, a plurality of data lines 13 extending in a second direction, and sub-pixels 10 disposed at the intersection of the gate lines 12 and the data lines 13. Each sub-pixel 10 includes a thin-film transistor 14, a common electrode 15, and a pixel electrode 16 sequentially disposed on the first substrate 11. In this embodiment, taking the thin-film transistor 14 as a bottom-gate thin-film transistor as an example, a first passivation layer 17 and a planarization layer 18 are disposed between the source and drain layers of the thin-film transistor 14 and the layer where the common electrode 15 is located, and a second passivation layer 19 is disposed between the layer where the common electrode 15 is located and the layer where the pixel electrode 16 is located. The drain of the thin-film transistor 14 is connected to the pixel electrode 16 through a via penetrating the first passivation layer 17, the planarization layer 18, and the second passivation layer 19.
[0074] Figure 10 This is a partial top view of the color filter substrate side of the display panel in an embodiment of this disclosure; Figure 11 This is a top view of the black matrix layer 22 in an embodiment of this disclosure; Figure 12 for Figure 10 The cross-sectional view of C-C' shown; as Figure 10-12 As shown, exemplarily, the color filter substrate may include a second substrate 21, on which a black matrix layer 22, a color resist layer, and a protective layer 24 are disposed. The black matrix layer 22 includes multiple first black matrices 221 extending along a first direction and multiple second black matrices 222 extending along a second direction. The first black matrices 221 and second black matrices 222 intersect to define multiple pixel openings. The color resist layer includes a color resist 23. For example, in this embodiment, a subpixel includes a red subpixel R, a green subpixel G, and a blue subpixel B, and the corresponding color resist 23 in the color resist layer includes a red resist, a green resist, and a blue resist. One color resist 23 covers one pixel opening.
[0075] It should be noted that in this embodiment, one of the first direction and the second direction is the row direction X, and the other is the column direction Y. This embodiment uses the row direction X as the first direction and the column direction Y as the second direction as an example. "Extending along the row direction X" means that the length of the main portion of the orthogonal projection of the component on the first substrate 11 extends along the row direction X; similarly, "extending along the column direction Y" means that the length of the main portion of the orthogonal projection of the component on the first substrate 11 extends along the column direction Y. Here, the "main portion" of a component refers to the longest portion of the component's projection on the first substrate 11.
[0076] In some examples, refer to Figure 1 , 3The display panel is divided into a display area AA and a peripheral area BA surrounding the display area AA. A bezel adhesive 4 surrounding the liquid crystal layer 3 is provided in the peripheral area BA. The color resist layer of the color filter substrate in the display panel also includes redundant color resist 25 located in the peripheral area BA. The black matrix layer 22 also includes a redundant black matrix located in the peripheral area BA. The redundant color resist 25 is disposed in the redundant pixel openings defined by the redundant black matrix. In this embodiment, the peripheral area BA is also provided with redundant spacers 53, which are disposed on the side of the bezel adhesive 4 near the display area AA. The redundant spacers 53 in this embodiment also include a first spacer portion 501 disposed on the first substrate and a second spacer portion 502 disposed on the second substrate. By providing redundant spacers 53 in the peripheral area BA, the peripheral area BA of the display panel can be supported, thereby avoiding display defects caused by step differences around the display area AA.
[0077] In some examples, the spacers in the display area AA of the display panel include a main spacer 51 and a secondary spacer 52. The first spacer portion 501 and the second spacer portion 502 of the main spacer 51 abut against each other; there is a certain gap between the first spacer portion 501 and the second spacer portion 502 of the secondary spacer 52.
[0078] Furthermore, the first spacer portion 501 includes a first surface and a second surface disposed opposite to each other along the thickness direction of the first substrate 11, and the first surface of the first spacer portion 501 is disposed on the side of the array substrate near the liquid crystal layer 3. The second spacer portion 502 includes a third surface and a fourth surface disposed opposite to each other along the thickness direction of the first substrate 11, and the third surface is disposed on the side of the color filter substrate near the liquid crystal layer 3.
[0079] For large-size touch panels, there is an L0 dark-state light leakage issue. The dark-state light leakage level is less than Level 0.5, and the contact density of the main spacer 51 is approximately 120um. 2 / mm 2 Considering that the surface pressure level of the display panel is greater than 350N, the contact density of the secondary spacer 52 is approximately 12000um. 2 / mm 2 Considering that the mura level of the septum is greater than 250N, the shift margin of the septum design in this embodiment of the disclosure is as large as possible. When the septum of this embodiment of the disclosure is prepared using an NSK exposure machine, the size of the septum is at least about 12μm in order to ensure the uniformity of the septum.
[0080] In some examples, Figure 13 This is a top view of the secondary spacer 52 according to an embodiment of the present disclosure; as shown Figure 13As shown, since there is a certain gap between the first spacer portion 501 and the second spacer portion 502 of the sub-spacer 52, in order to prevent the first spacer portion 501 from sliding relative to the second spacer portion 502 when the display panel is subjected to external force, which would cause the first spacer portion 501 to scratch the color resist 23 and result in bright spots or other defects, in this embodiment of the disclosure, the width of the fourth surface of the second spacer portion 502 disposed on the color filter substrate along the column direction Y is designed to be wider than the width of the second surface of the first spacer portion 501 disposed on the array substrate along the column direction Y. For example, the width of the fourth surface of the second spacer portion 502 along the column direction Y is 18 μm, and the width of the second surface of the first spacer portion 501 along the column direction Y is 12 μm. In this way, the sliding of the first spacer portion 501 relative to the second spacer portion 502, which would cause the first spacer portion 501 to scratch the color resist 23, can be effectively prevented.
[0081] Further, continue to refer to Figure 13 The dimensions of the first spacer portion 501 and the second spacer portion 502 of the sub-spacer 52 are reasonably designed to ensure the pixel aperture ratio of the display panel. In one example, the vertical offset margin of the first spacer portion 501 and the second spacer portion 502 of the sub-spacer 52 is 22μm, and the horizontal offset margin is 28μm. The dimensions of the second surface of the first spacer portion 501 are 12×26μm (length in the row direction X × length in the column direction Y), and the dimensions of the fourth surface of the second spacer portion 502 are 44×18μm (length in the row direction X × length in the column direction Y). It should be noted that the vertical offset margin of the first spacer portion 501 and the second spacer portion 502 is half the total length of the second surface in the column direction Y and the fourth surface in the column direction Y; the horizontal offset margin of the first spacer portion 501 and the second spacer portion 502 is half the total length of the second surface in the row direction X and the fourth surface in the row direction X.
[0082] Furthermore, to ensure that the difference in the impact of the main spacer 51 and the secondary spacer 52 on the pixel opening is as small as possible, preferably less than 8% (280 PPI), the vertical offset margin and the horizontal offset margin of the main spacer 51 are both 28 μm. Figure 14 This is a top view of the main spacer 51 according to an embodiment of this disclosure; as shown Figure 14 As shown, the second surface of the first spacer portion 501 of the main spacer 51 has a size of 12 × 44 μm (length in the row direction X × length in the column direction Y), and the fourth surface of the second spacer portion 502 has a size of 44 × 12 μm (length in the row direction X × length in the column direction Y).
[0083] It should be noted that in this example, the length of the first spacer of the main spacer 51 along the column direction Y is greater than the length of the first spacer of the secondary spacer 52 along the column direction Y, and the length of the second spacer of the main spacer 51 along the column direction Y is less than the length of the second spacer of the secondary spacer 52 along the column direction Y. However, the dimensions of the main spacer 51 and the secondary spacer 52 are not necessarily set in this way. The dimensions of the main spacer 51 and the secondary spacer 52 depend on the contact density of the main spacer 51 and the secondary spacer 52 in the display panel.
[0084] In some examples, the arrangement density of the main spacer 51 is less than that of the secondary spacer 52. For example, the arrangement period of the main spacer 51 is 1 / 432, and the arrangement period of the secondary spacer 52 is 1 / 6. That is, one main spacer 51 is set in 432 pixel units, and one secondary spacer 52 is set in 6 pixel units.
[0085] Furthermore, Figure 15 This is a top view of the main spacer 51 and the secondary spacer 52 according to an embodiment of this disclosure; as shown Figure 15 As shown, for two adjacent columns of secondary spacers 52 arranged along the row direction X, the secondary spacers 52 are staggered; for two adjacent columns of primary spacers 51 arranged along the row direction X, the primary spacers 51 are staggered. At least some of the pixel units containing the primary spacers 51 do not have secondary spacers 52 in two adjacent pixel units arranged along the row direction X, thus reserving space in this way ( Figure 15 (The position of the × in the middle) so that the main septum 51 and the secondary septum 52 can be distinguished when the septum inspection equipment is used for subsequent testing.
[0086] In some examples, Figure 16 This is a schematic diagram showing the relative positions of the spacers and the array substrate according to an embodiment of this disclosure; as shown... Figure 16 As shown in the embodiments of this disclosure, both the main spacer 51 and the secondary spacer 52 are preferably positioned at locations corresponding to the red subpixel R and the blue subpixel B, and do not overlap with the location of the green subpixel G. That is, the second spacer portion 502 overlaps with the orthographic projections of the red and blue color resists on the first substrate 11, but does not overlap with the orthographic projection of the green color resist on the first substrate 11. This arrangement is because the light from the green subpixel G is significantly affected by interference from spacers or other factors. In this embodiment, only the spacer spanning both the red subpixel R and the blue subpixel B is used as an example. Of course, the spacer may also be located only at the location of either the red subpixel R or the blue subpixel B.
[0087] Furthermore, Figure 17 This is a schematic diagram showing the relative positions of the second spacer portion 502 and the color resist 23 according to an embodiment of this disclosure; as shown Figure 17As shown, for the second spacer portion 502 in the spacer material, there are overlapping red and blue color resists with its orthographic projection on the first substrate 11. The minimum distance between the outer contour of the second spacer portion 502's orthographic projection on the first substrate 11 and the outer contour of the blue color resist's orthographic projection on the first substrate 11 is 'a', and the minimum distance between the outer contour of the second spacer portion 502's orthographic projection on the first substrate 11 and the outer contour of the red color resist's orthographic projection on the first substrate 11 is 'b', where a = b. In this embodiment, a = b = 3.26 μm is used as an example.
[0088] In some examples, Figure 18 This is a schematic diagram showing the relative positions of the spacer and the gate in an embodiment of this disclosure; as shown Figure 18 As shown, the gates of thin-film transistors 14 located in the same row of sub-pixels are connected to the same gate line 12, and each gate and the gate line 12 connected thereto are integrally formed structures. The gate of the thin-film transistor 14 includes a fifth side and a sixth side disposed opposite to each other along the row direction X. In the embodiments of this disclosure, at least a portion of the spacer overlaps with the orthographic projection of the thin-film transistor 14 on the first substrate 11. For the spacer and the thin-film transistor 14 whose orthographic projections on the first substrate 11 overlap, the orthographic projection of the first spacer portion 501 of the spacer on the first substrate 11 does not overlap with the orthographic projection of the fifth side on the first substrate 11, and covers the orthographic projection of the sixth side on the first substrate 11; the fourth surface of the second spacer portion 502 of the spacer partially overlaps with the orthographic projection of the gate on the first substrate 11.
[0089] Further, continue to refer to Figure 18 The length of the fourth surface of the second spacer portion 502 and the orthogonal projection of the gate onto the first substrate 11 in the column direction Y is c. The distance between the first surface of the first spacer portion and the orthogonal projection of the fifth side onto the first substrate 11 in the row direction X is d. The distance between the first surface of the first spacer portion and the orthogonal projection of the sixth side onto the first substrate 11 in the row direction X is e. Wherein, c = 10.25 μm, d = 0.5 μm, and e = 8 μm.
[0090] In some examples, Figure 19 This is a schematic diagram showing the relative positions of the spacer, data line 13, and the drain of thin-film transistor 14 according to an embodiment of this disclosure; as shown Figure 19As shown, in this embodiment of the present disclosure, at least a portion of the spacers overlap with the orthographic projection of the data line 13 onto the first substrate 11. For the spacers and data line 13 whose orthographic projections overlap on the first substrate 11, the centers of the first spacer portion 501 and the second spacer portion 502 of the spacers on the orthographic projection of the data line 13 on the first substrate 11 are both penetrated by the orthographic projection of the data line 13 on the first substrate 11. This arrangement makes the support of the spacers more stable.
[0091] Further, continue to refer to Figure 19 The minimum distances between the orthographic projections of the two opposite sides of the first surface of the first spacer portion 501 on the first substrate 11 and the orthographic projections of the data lines 13 on the first substrate 11 are f and g, respectively. In one example, f = g = 8.5 μm. The minimum distances between the minimum projections of the two opposite sides of the fourth surface of the second spacer portion 502 on the first substrate 11 and the minimum distances between the minimum projections of the data lines 13 on the first substrate 11 and the minimum distances of the data lines 13 on the first substrate 11 are h and i, respectively. In one example, h = i = 6.26 μm.
[0092] Further, continue to refer to Figure 19 The orthographic projection of the second spacer portion 502 on the first substrate 11 covers the orthographic projection of the drain of the thin-film transistor 14 on the first substrate 11. Specifically, the orthographic projection of one second spacer portion 502 on the first substrate 11 covers the orthographic projection of the drain of the thin-film transistor 14 in the red sub-pixel R and the green sub-pixel G on the first substrate 11. That is, the thickness of the spacer portion 502 at the corresponding position on the array substrate is basically consistent, thereby ensuring stable support.
[0093] Furthermore, Figure 20 This is a schematic diagram showing the relative positions of the spacer and the via connecting the drain of the thin-film transistor 14 and the pixel electrode 16 according to an embodiment of this disclosure; as shown Figure 20 As shown, the drain of the thin-film transistor 14 is connected to the pixel electrode 16 through a via penetrating the first passivation layer 17, the planarization layer 18, and the second passivation layer 19. The orthographic projection of a second spacer portion 502 on the first substrate 11 covers the orthographic projection of two vias in the red sub-pixel R and the blue sub-pixel B on the first substrate 11, thereby avoiding the height difference caused by the second spacer portion 502 covering the via on one side, which would affect the support stability.
[0094] Furthermore, continue to refer to Figure 20The via for connecting the drain of the thin-film transistor 14 and the pixel electrode 16 includes a first sub-via penetrating through the first passivation layer 17 and the planarization layer 18, and a second sub-via penetrating through the second passivation layer 19. The second spacer portion 502 includes orthographic projections of its side edges disposed opposite each other along the row direction X onto the first substrate 11, with minimum distances j and k between these sides and the orthographic projections of the first sub-via onto the first substrate 11, respectively. The second spacer portion 502 also includes orthographic projections of its side edges disposed opposite each other along the column direction Y onto the first substrate 11, with minimum distances l and m between these sides and the orthographic projections of the first sub-via onto the first substrate 11, respectively. In one example, j = 1.25 μm, k = 24 μm, l = 3.25 μm, and m = 6.25 μm.
[0095] In some examples, Figure 21 This is a schematic diagram showing the relative positions of the spacer and the common electrode line 110 in an embodiment of this disclosure; as shown Figure 21 As shown, the display panel not only includes the above-described structure, but also includes a common electrode line 110 located between the common electrode 15 and the pixel electrode 16 layer of the array substrate. The common electrode 15 in the pixel unit located in the same row is connected to the same common electrode line 110. Two common electrode lines 110 are provided between two rows of pixel units arranged side by side along the column direction Y, and the orthographic projection of the two common electrode lines 110 on the first substrate 11 is covered by the orthographic projection of the first black matrix 221 on the first substrate 11.
[0096] Further, continue to refer to Figure 21 The second spacer portion 502 has a first side and a second side disposed opposite to each other along the column direction Y when projected onto the first substrate 11; the common electrode line 110 has a third side and a fourth side disposed opposite to each other along the column direction Y when projected onto the first substrate 11; for the two common electrode lines 110 and the spacer located between the two rows of pixel units, one of the two common electrode lines 110 is called the first common electrode line and the other is called the second common electrode line; the first side of the second spacer portion 502 of the spacer falls on the third side of the first common electrode line, and the second side of the second spacer portion 502 of the spacer falls on the fourth side of the second common electrode line 110.
[0097] Further, continue to refer to Figure 21 The distance between the fourth side of the first common electrode line 110 and the side of the first surface closest to it in the column direction Y, and the distance between the third side of the second common electrode line 110 and the side of the first surface closest to it in the column direction Y, and the distance between the projections on the first substrate 11, is o. In one example, n=o.
[0098] In this example, one spacer corresponds to two common electrode lines 110, thereby ensuring that the height of the first spacer portion 501 is uniform and that the spacer is stably supported. The common electrode line 110 is located at the position of the black matrix, ensuring that the opening ratio is maximized without affecting the opening ratio.
[0099] In some examples, Figure 22 This is a schematic diagram showing the relative positions of the second spacer portion 502 and the first black matrix 221 in an embodiment of this disclosure; as shown Figure 22 As shown, to ensure that the second spacer portion 502 is covered by the first black matrix 221, the distance between the fourth surface of the second spacer portion 502 and the first black matrix 221 is p, and the distance between the third surface of the second spacer portion 502 and the first black matrix 221 is q. The first black matrix 221 includes a first portion that overlaps with the second spacer portion 502 on the first substrate 11, and a second portion that does not overlap with the second spacer portion 502 on the first substrate 11. The length of the second portion in the column direction Y is r, and the length of the first portion in the column direction Y is s. In one example, p = 6 μm, q = 1 μm, r = 28.5 μm, and s = 30 μm. This example method has the least impact on the aperture ratio of the display panel.
[0100] In some examples, Figure 23 This is a schematic diagram showing the relative positions of the first spacer portion 501 and the second black matrix 222 in an embodiment of this disclosure; as shown Figure 23 As shown, to ensure that the first spacer portion 501 is covered by the second black matrix 222, the distance between the second surface of the first spacer portion 501 and the second black matrix 222 is t, and the distance between the first surface and the second black matrix 222 is u. The second black matrix 222 includes a third portion that overlaps with the first spacer portion 501 on the first substrate 11, and a fourth portion that does not overlap with the first spacer portion 501 on the first substrate 11. The length of the fourth portion in the column direction Y is v, and the length of the third portion in the column direction Y is w. In one example, t = 6 μm, u = 1 μm, v = 5.5 μm, and w = 24 μm. This example method has the least impact on the aperture ratio of the display panel.
[0101] This disclosure also provides a display device, which includes any of the above-described display panels and a backlight that provides a light source for the display panel.
[0102] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of this utility model, and the utility model is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of this utility model, and these modifications and improvements are also considered to be within the protection scope of this utility model.
Claims
1. A display panel comprising a first substrate and a second substrate disposed opposite to each other, wherein a liquid crystal layer and a spacer are disposed between the first substrate and the second substrate; the first substrate includes a first substrate substrate, and a plurality of gate lines and a plurality of data lines disposed on the first substrate substrate; the gate lines extend along a first direction, and the data lines extend along a second direction; wherein, The spacer includes a first spacer portion extending along the second direction and a second spacer portion extending along the first direction; the first spacer portion is disposed on the side of the first substrate near the second substrate; the second spacer portion is disposed on the side of the second substrate near the first substrate, and the orthographic projections of the first spacer portion and the second spacer portion on the first substrate are intersecting.
2. The display panel according to claim 1, wherein, The second substrate includes a second substrate, and a black matrix layer and a color resist layer disposed on the second substrate; The black matrix layer includes a plurality of first black matrices extending along the first direction and a plurality of second black matrices extending along the second direction; the first black matrices and the second black matrices are intersected to define a plurality of pixel openings; the color resist layer includes a plurality of color resists; one of the color resists is disposed in a pixel opening, and the orthographic projection of the color resist on the second substrate covers the orthographic projection of the pixel opening on the second substrate.
3. The display panel according to claim 2, wherein, The first spacer portion includes a first surface and a second surface disposed opposite to each other along the thickness direction of the first substrate, and the first surface is disposed on the first substrate; the orthographic projection of the first surface on the first substrate is located on the orthographic projection of the second black matrix on the first substrate. Each of the second spacers includes a third surface and a fourth surface disposed opposite to each other along the thickness direction of the first substrate, and the third surface is disposed on the second substrate; the orthographic projection of the third surface on the first substrate is located on the orthographic projection of the first black matrix on the first substrate.
4. The display panel according to claim 2, wherein, The color resist includes a red resist, a green resist, and a blue resist; the second spacer overlaps with the orthographic projections of the red resist and the blue resist on the first substrate, but does not overlap with the orthographic projection of the green resist on the first substrate.
5. The display panel according to claim 4, wherein, For the second spacer portion, there are overlapping red and blue color resists with its orthographic projection on the first substrate, wherein the minimum distance between the outer contour of the orthographic projection of the second spacer portion on the first substrate and the outer contour of the orthographic projection of the blue color resist on the first substrate is a, and the minimum distance between the outer contour of the orthographic projection of the second spacer portion on the first substrate and the outer contour of the orthographic projection of the red color resist on the first substrate is b, and a=b.
6. The display panel according to claim 2, wherein, The first substrate further includes a common electrode line; and a pixel unit disposed at the intersection of the gate line and the data line; The pixel unit includes a thin-film transistor disposed on the first substrate, a common electrode and a pixel electrode disposed on the side of the thin-film transistor facing away from the first substrate; The common electrode line is connected to the common electrode and is located between the common electrode and the layer containing the pixel electrode. Two common electrode lines extending along the first direction are provided between the two rows of pixel units arranged side by side along the second direction, and the orthographic projection of the two common electrode lines on the first substrate is covered by the orthographic projection of the first black matrix on the first substrate.
7. The display panel according to claim 6, wherein, The second spacer portion has a first side and a second side disposed opposite to each other along the second direction in its orthogonal projection onto the first substrate; the common electrode line has a third side and a fourth side disposed opposite to each other along the second direction in its orthogonal projection onto the first substrate. For the two common electrode lines and the spacer located between the two rows of pixel units, one of the two common electrode lines is a first common electrode line and the other is a second common electrode line; the first side of the second spacer portion of the spacer falls on the third side of the first common electrode line, and the second side of the second spacer portion of the spacer falls on the fourth side of the second common electrode line.
8. The display panel according to claim 1, wherein, The first substrate further includes a pixel unit disposed at the intersection of the gate line and the data line; The pixel unit includes a thin-film transistor disposed on the first substrate, a common electrode and a pixel electrode disposed on the side of the thin-film transistor facing away from the first substrate; the gate of the thin-film transistor and the corresponding gate line are connected as an integral structure. At least a portion of the spacer overlaps with the orthographic projection of the thin-film transistor onto the first substrate. The gate of the thin-film transistor includes a fifth side and a sixth side disposed opposite to each other along the first direction; For the spacer and the thin film transistor whose orthogonal projections on the first substrate overlap, the orthogonal projection of the first spacer portion of the spacer on the first substrate does not overlap with the orthogonal projection of the fifth side on the first substrate, and covers the orthogonal projection of the sixth side on the first substrate. The fourth surface of the second spacer portion of the spacer overlaps with the orthogonal projection portion of the gate on the first substrate.
9. The display panel according to claim 1, wherein, The first substrate further includes a pixel unit disposed at the intersection of the gate line and the data line; The pixel unit includes a thin-film transistor disposed on the first substrate, a common electrode and a pixel electrode disposed on the side of the thin-film transistor facing away from the first substrate; At least a portion of the spacer overlaps with the orthographic projection of the thin-film transistor onto the first substrate. For the orthographic projection of the spacer and the thin-film transistor on the first substrate, the orthographic projection of the fourth surface of the second spacer portion of the spacer on the first substrate covers the orthographic projection of the drain of the thin-film transistor on the first substrate.
10. The display panel according to claim 1, wherein, At least a portion of the spacer overlaps with the orthographic projection of the data line onto the first substrate. For the spacers and the data line that overlap in their orthogonal projections on the first substrate, the centers of the orthogonal projections of the first spacer portion and the second spacer portion of the spacers on the first substrate are both penetrated by the orthogonal projection of the data line on the first substrate.
11. The display panel according to claim 1, wherein, The first substrate further includes a pixel unit disposed at the intersection of the gate line and the data line; The pixel unit includes a thin-film transistor disposed on the first substrate, a common electrode and a pixel electrode disposed on the side of the thin-film transistor facing away from the first substrate; the drain of the thin-film transistor is connected to the pixel electrode through a via penetrating the interlayer insulating layer. At least a portion of the spacer overlaps with the orthographic projection of the thin-film transistor onto the first substrate. For the orthographic projection of the spacer and the thin film transistor on the first substrate, there is an overlapping spacer and a fourth surface of the second spacer portion of the spacer on the first substrate, and an orthographic projection of the via connecting the drain of the thin film transistor to the pixel electrode on the first substrate.
12. The display panel according to any one of claims 1-11, wherein, The septum includes a main septum and a secondary septum; the first septum portion and the second septum portion of the main septum abut against each other; and the first septum portion and the second septum portion of the secondary septum have a certain distance between them.
13. The display panel according to claim 12, wherein, The second spacer portion includes a third surface and a fourth surface disposed opposite to each other along the thickness direction of the first substrate. The width of the second surface of the primary spacer along the first direction is smaller than the width of the second surface of the secondary spacer along the first direction. The length of the fourth surface of the primary septum along the second direction is less than the length of the fourth surface of the secondary septum along the second direction.
14. The display panel according to any one of claims 1-11, wherein, The display panel is divided into a display area and a peripheral area; the display panel also includes a frame adhesive located in the peripheral area and disposed between the first substrate and the second substrate, the frame adhesive surrounding the liquid crystal layer.
15. The display panel according to claim 14, wherein, The peripheral area also includes redundant color resist and redundant black matrix located on the side of the frame adhesive near the display area, as well as redundant spacers disposed on the side of the redundant color resist and redundant black matrix near the display area.
16. A display device, characterized in that, It includes a display panel according to any one of claims 1-15, and a backlight for providing a light source for the display panel.