Gate driving circuit, display panel
By introducing first and second switching circuits into the gate drive circuit, and controlling the switching circuits to turn on and off via the control signal line, the problem of low aging process efficiency in the prior art is solved, achieving rapid aging process and reduced leakage current, and supporting narrow bezel design.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- BOE TECHNOLOGY GROUP CO LTD
- Filing Date
- 2025-07-01
- Publication Date
- 2026-06-09
Smart Images
Figure CN224342024U_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of display technology, and in particular to a gate driving circuit and a display panel. Background Technology
[0002] Before the display panel leaves the factory, the transistors in the gate drive circuit need to undergo aging treatment to reduce the leakage current of the transistors. However, the gate drive circuit has multiple shift register units cascaded and driven step by step, which makes the aging treatment of the gate drive circuit relatively slow.
[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Utility Model Content
[0004] This disclosure first provides a gate driving circuit, wherein the gate driving circuit includes:
[0005] Multiple shift register units are cascaded together, with the signal output terminal of the upper-level shift register unit connected to the signal input terminal of the lower-level shift register unit;
[0006] Multiple first switching circuits are provided, and the first switching circuits are correspondingly configured with the shift register unit. The signal output terminal of the shift register unit is connected to the signal input terminal of the next-level shift register unit through its corresponding first switching circuit. The first switching circuit is used to respond to a control signal to connect the signal output terminal of its corresponding shift register unit and the signal input terminal of the next-level shift register unit.
[0007] The start signal line is connected to the signal input terminal of the first-stage shift register unit;
[0008] Multiple second switching circuits are provided, and the second switching circuits are correspondingly arranged with shift register units other than the first-stage shift register unit. The second switching circuit is connected between the start signal line and the signal input terminal of the corresponding shift register unit. The second switching circuit is used to respond to a control signal to connect the start signal line and the signal input terminal of the shift register unit.
[0009] In one exemplary embodiment of this disclosure, the second switching circuit includes one or more switching transistors;
[0010] The second switching circuit corresponding to the secondary shift register unit is connected to the start signal line;
[0011] In the shift register unit located below the secondary shift register unit, the second switching circuit corresponding to the lower shift register unit is indirectly connected to the start signal line through at least some of the switching transistors in the second switching circuit corresponding to the upper shift register unit.
[0012] In one exemplary embodiment of this disclosure, a plurality of second switching circuits are directly connected to the start signal line.
[0013] In an exemplary embodiment of this disclosure, a plurality of first switching circuits are connected to control signal lines. The first switching circuits are used to respond to signals from the control signal lines to connect the signal output terminal of their corresponding shift register unit and the signal input terminal of the next-level shift register unit.
[0014] Multiple second switching circuits are connected to the control signal line, and the second switching circuits are used to respond to the signal of the control signal line to connect the start signal line and the signal input terminal of the shift register unit;
[0015] The conduction level of the first switching circuit and the conduction level of the second switching circuit are logically opposite.
[0016] In one exemplary embodiment of this disclosure, the first switching circuit includes:
[0017] The first transistor has its first terminal connected to the signal output terminal of its corresponding shift register unit, its second terminal connected to the signal input terminal of the next-level shift register unit, and its gate connected to the control signal line.
[0018] The second switching circuit includes:
[0019] The second transistor has its gate connected to the control signal line;
[0020] The third transistor has its first terminal connected to the second terminal of the second transistor in the same second switching circuit, and its second terminal connected to the signal input terminal of its corresponding shift register unit. Its gate is connected to the control signal line.
[0021] In this case, the first terminal of the second transistor corresponding to the secondary shift register unit is connected to the start signal line;
[0022] In the shift register unit located below the secondary shift register unit, the first terminal of the second transistor corresponding to the lower shift register unit is connected to the second terminal of the second transistor corresponding to the upper shift register unit;
[0023] The first transistor is an N-type transistor, and the second and third transistors are P-type transistors.
[0024] In one exemplary embodiment of this disclosure, the first switching circuit includes:
[0025] The first transistor has its first terminal connected to the signal output terminal of its corresponding shift register unit, its second terminal connected to the signal input terminal of the next-level shift register unit, and its gate connected to the control signal line.
[0026] The second switching circuit includes:
[0027] The second transistor has a first terminal connected to the start signal line, a second terminal connected to the signal input terminal of its corresponding shift register unit, and a gate connected to the control signal line.
[0028] The first transistor is an N-type transistor, and the second transistor is a P-type transistor.
[0029] In one exemplary embodiment of this disclosure, the first switching circuit includes:
[0030] The first transistor has its first terminal connected to the signal output terminal of its corresponding shift register unit, its second terminal connected to the signal input terminal of the next-level shift register unit, and its gate connected to the control signal line.
[0031] The second switching circuit includes:
[0032] The second transistor has its gate connected to the control signal line and its second terminal connected to the signal input terminal of its corresponding shift register unit.
[0033] In this case, the first terminal of the second transistor corresponding to the secondary shift register unit is connected to the start signal line;
[0034] In the shift register unit located below the secondary shift register unit, the first terminal of the second transistor corresponding to the lower shift register unit is connected to the second terminal of the second transistor corresponding to the upper shift register unit;
[0035] The first transistor is an N-type transistor, and the second transistor is a P-type transistor.
[0036] In one exemplary embodiment of this disclosure, the shift register unit includes:
[0037] A first input circuit is connected to a signal input terminal, a first node, and a clock signal terminal. The first input circuit is used to respond to the signal of the clock signal terminal to transmit the signal of the signal input terminal to the first node.
[0038] The second input circuit is connected to the first power supply terminal, the second node, the third node, the fourth node, and the clock signal terminal. The second input circuit is used to respond to the signal of the second node to transmit the signal of the first power supply terminal to the third node, and to respond to the signal of the clock signal terminal to transmit the signal of the third node to the fourth node.
[0039] A pull-up circuit is connected to the signal input terminal, the second power supply terminal, the second node, and the third node. The pull-up circuit is used to respond to the signal at the signal input terminal to transmit the signal at the second power supply terminal to the second node and the third node.
[0040] A coupling circuit connects the clock signal terminal and the second node, and the coupling circuit is used to couple the voltage change of the clock signal terminal to the second node;
[0041] An isolation circuit is provided to connect the first node, the fifth node, and the first power supply terminal. The isolation circuit is used to respond to the signal from the first power supply terminal to connect the first node and the fifth node.
[0042] A first output circuit is connected to the fifth node, a signal output terminal, and a first power supply terminal. The first output circuit is used to respond to the signal of the fifth node to transmit the signal of the first power supply terminal to the signal output terminal.
[0043] The second output circuit is connected to the fourth node, the signal output terminal, and the second power supply terminal. The second output circuit is used to respond to the signal of the fourth node to transmit the signal of the second power supply terminal to the signal output terminal.
[0044] In one exemplary embodiment of this disclosure, the first input circuit includes:
[0045] The fourth transistor has its first terminal connected to the signal input terminal, its second terminal connected to the first node, and its gate connected to the clock signal terminal.
[0046] The second input circuit includes:
[0047] The fifth transistor has its first terminal connected to the first power supply terminal, its second terminal connected to the third node, and its gate connected to the second node.
[0048] The sixth transistor has its first terminal connected to the third node, its second terminal connected to the fourth node, and its gate connected to the clock signal terminal.
[0049] The pull-up circuit includes:
[0050] The seventh transistor has its first terminal connected to the second power supply terminal, its second terminal connected to the second node, and its gate connected to the signal input terminal.
[0051] The eighth transistor has its first terminal connected to the second power supply terminal, its second terminal connected to the third node, and its gate connected to the signal input terminal.
[0052] The coupling circuit includes:
[0053] The first capacitor is connected between the clock signal terminal and the second node;
[0054] The isolation circuit includes:
[0055] The ninth transistor has its first terminal connected to the first node, its second terminal connected to the fifth node, and its gate connected to the first power supply terminal.
[0056] The first output circuit includes:
[0057] The tenth transistor has its first terminal connected to the first power supply terminal, its second terminal connected to the signal output terminal, and its gate connected to the fifth node.
[0058] The second capacitor is connected between the fifth node and the signal output terminal;
[0059] The second output circuit includes:
[0060] The eleventh transistor has its first terminal connected to the second power supply terminal, its second terminal connected to the signal output terminal, and its gate connected to the fourth node.
[0061] The third capacitor is connected between the fourth node and the second power supply terminal.
[0062] This disclosure also provides a gate driving circuit driving method, wherein the driving method is used to drive the above-mentioned gate driving circuit, and the driving method includes:
[0063] In the first mode, the first switching circuit is turned on and the second switching circuit is turned off, and the shift signal is output step by step using cascaded shift register units;
[0064] In the second mode, the first switching circuit is turned off, the second switching circuit is turned on, and aging processing signals are input to each shift register unit respectively.
[0065] This disclosure also provides a display panel, wherein the display panel includes the gate driving circuit described above.
[0066] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description
[0067] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.
[0068] Figure 1 This is a schematic diagram of the structure of a display panel in related technologies;
[0069] Figure 2 This is a transfer characteristic curve of a transistor;
[0070] Figure 3 This is a schematic diagram of an exemplary embodiment of the gate drive circuit of this disclosure;
[0071] Figure 4 This is a schematic diagram of another exemplary embodiment of the gate drive circuit of this disclosure;
[0072] Figure 5 This is a schematic diagram of another exemplary embodiment of the gate drive circuit of this disclosure;
[0073] Figure 6 This is a schematic diagram of the structure of an exemplary embodiment of the display panel disclosed herein;
[0074] Figure 7 This is a schematic diagram of the structure of an exemplary embodiment of the display panel disclosed herein;
[0075] Figure 8 This is a schematic diagram of the shift register unit in an exemplary embodiment of the gate drive circuit of this disclosure;
[0076] Figure 9 This is a schematic diagram of the structure of an exemplary embodiment of the gate drive circuit of this disclosure;
[0077] Figure 10 for Figure 9 The timing diagram of each node in a driving method of the gate driving circuit shown is shown. Detailed Implementation
[0078] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore their detailed description will be omitted.
[0079] The terms “a,” “one,” and “the” are used to indicate the existence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended meaning of inclusion and that there may be other elements / components / etc. in addition to the listed elements / components / etc.
[0080] In the description of this disclosure, unless otherwise expressly specified and limited, the terms “first” and “second” are used for descriptive purposes only and should not be construed as indicating or implying relative importance; the term “multiple” refers to two or more; and the term “and / or” includes any and all combinations of one or more associated listed items. In particular, references to “the / described” object or “a” object are also intended to indicate one of a possible plurality of such objects.
[0081] Unless otherwise specified or stated, the terms "connection," "fixed," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, an integral connection, an electrical connection, or a signal connection; "connection" can be a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.
[0082] Furthermore, it should be understood that the directional terms such as "upper," "lower," "inner," and "outer" described in the exemplary embodiments of this disclosure are used to describe the angles shown in the accompanying drawings and should not be construed as limiting the exemplary embodiments of this disclosure. It should also be understood that, in the context of an element or feature being connected to one or more "upper," "lower," "inner," or "outer" elements, it can be directly connected to one or more "upper," "lower," "inner," or "outer" elements, or indirectly connected to one or more "upper," "lower," "inner," or "outer" elements through intermediate elements.
[0083] like Figure 1 The diagram shows a schematic of a display panel in the related art. This display panel includes a pixel driving circuit Pix and a gate driving circuit Cg. The gate driving circuit Cg includes multiple cascaded shift register units GOA. The signal input terminal of the first-level shift register unit is connected to the start signal line STV, and the signal output terminal of the upper-level shift register unit is connected to the signal input terminal of the lower-level shift register unit. The shift register units GOA in the gate driving circuit Cg provide gate driving signals to the pixel driving circuit Pix step by step to drive the pixel driving circuit to scan line by line.
[0084] like Figure 2The figure shows the transfer characteristic curves of a transistor, with the horizontal axis representing the gate-source voltage difference and the vertical axis representing the output current. Lin1 is the transfer characteristic curve before aging treatment, and Lin2 is the transfer characteristic curve after aging treatment. According to... Figure 2 It is evident that the transfer characteristic curve of the transistor exhibits a tail-end phenomenon before aging treatment, and the transistor has a relatively large turn-off leakage current. This tail-end phenomenon is particularly pronounced in the transfer characteristic curve of the low-temperature polysilicon transistor. Therefore, the transistors in the gate drive circuit Cg need to undergo aging treatment before the display panel leaves the factory to reduce the turn-off leakage current. During the aging treatment of the gate drive circuit, an effective level needs to be input to the signal input terminal of the shift register unit, and an aging treatment signal needs to be input to the shift register unit simultaneously. However, if… Figure 1 As shown, the shift register units in the gate drive circuit are cascaded, and the signal input terminals of each shift register unit are input with valid levels step by step. Therefore, the aging efficiency of this gate drive circuit is very low.
[0085] Based on this, this exemplary embodiment provides a gate driving circuit, such as... Figure 3 The diagram shown is a schematic representation of an exemplary embodiment of the gate drive circuit of this disclosure. The gate drive circuit includes multiple shift register units GOA, multiple first switching circuits CN1, a start signal line STV, and multiple second switching circuits CN2. Multiple shift register units (GOAs) are cascaded, with the signal output terminal OUT of the upper-level shift register unit GOA connected to the signal input terminal IN of the lower-level shift register unit GOA. A first switching circuit CN1 is correspondingly configured with shift register units GOA, and the signal output terminal OUT of the shift register unit GOA is connected to the signal input terminal IN of the next-level shift register unit GOA through its corresponding first switching circuit CN1. The first switching circuit CN1 is used to respond to a control signal to connect the signal output terminal OUT of its corresponding shift register unit GOA and the signal input terminal IN of the lower-level shift register unit GOA. A start signal line STV is connected to the signal input terminal IN of the first-level shift register unit GOA. A second switching circuit CN2 is correspondingly configured with shift register units GOA other than the first-level shift register unit GOA, and the second switching circuit CN2 is connected between the start signal line STV and the signal input terminal of its corresponding shift register unit GOA. The second switching circuit is used to respond to a control signal to connect the start signal line STV and the signal input terminal IN of the shift register unit GOA.
[0086] In this exemplary embodiment, in the first mode, the first switch circuit CN1 can be turned on and the second switch circuit CN2 can be turned off, and the shift signal can be output step by step using the cascaded shift register units GOA. The gate driving circuit can drive the pixel driving circuit to scan line by line in the first mode. In the second mode, the first switch circuit CN1 can be turned off and the second switch circuit CN2 can be turned on. The start signal line STV can input an effective level to the input terminal of each shift register unit GOA respectively. The gate driving circuit can realize rapid aging process in the second mode.
[0087] In this exemplary embodiment, the second switching circuit can be directly connected to the start signal line STV or indirectly connected to the start signal line STV. For example, as... Figure 3 As shown, the second switching circuit CN2 includes one or more switching transistors; the second switching circuit CN2 corresponding to the secondary shift register unit GOA can be directly connected to the start signal line STV; in the shift register unit GOA located below the secondary shift register unit GOA, the second switching circuit CN2 corresponding to the lower shift register unit GOA is indirectly connected to the start signal line STV through at least some of the switching transistors in the second switching circuit CN2 corresponding to the upper shift register unit GOA. The secondary shift register unit GOA is the shift register unit directly connected to the first-level shift register unit.
[0088] In this exemplary embodiment, as Figure 3 As shown, the first switching circuit CN1 may include: a first transistor T1, the first terminal of the first transistor T1 is connected to the signal output terminal of its corresponding shift register unit GOA, the second terminal is connected to the signal input terminal of the next-level shift register unit GOA, and the gate is connected to the control signal line DW.
[0089] In this exemplary embodiment, as Figure 3 As shown, the second switching circuit CN2 includes a second transistor T2 and a third transistor T3. The gate of the second transistor T2 is connected to a control signal line. The first terminal of the third transistor T3 is connected to the second terminal of the second transistor T2 in the same second switching circuit CN2. The second terminal is connected to the signal input terminal IN of its corresponding shift register unit GOA, and its gate is connected to the control signal line DW. The first terminal of the second transistor T2 corresponding to the secondary shift register unit GOA is connected to the start signal line STV. In the shift register unit GOA located below the secondary shift register unit GOA, the first terminal of the second transistor T2 corresponding to the lower-level shift register unit GOA is connected to the second terminal of the second transistor T2 corresponding to the upper-level shift register unit GOA.
[0090] In this exemplary embodiment, as Figure 3As shown, the first transistor T1 can be an N-type transistor, while the second transistor T2 and the third transistor T3 can be P-type transistors. When the control signal line DW outputs a high-level signal, the first transistor T1 is turned on, and the second transistor T2 and the third transistor T3 are turned off. When the control signal line DW outputs a low-level signal, the first transistor T1 is turned off, and the second transistor T2 and the third transistor T3 are turned on. This gate drive circuit can control the first transistor T1, the second transistor T2, and the third transistor T3 through a single control signal line DW.
[0091] In this exemplary embodiment, as Figure 3 As shown, the second switching circuit CN2 includes two second transistors T2 and a third transistor T3 connected in series. When the second switching circuit CN2 is turned off, this configuration can reduce the leakage current between the start signal line STV and the shift register unit. It should be understood that in other exemplary embodiments, such as Figure 4 The diagram shown is a schematic representation of another exemplary embodiment of the gate drive circuit of this disclosure. The second switching circuit CN2 may also exclude the third transistor T3, and the second terminal of the second transistor T2 is directly connected to the signal input terminal of its corresponding shift register unit.
[0092] like Figure 5 The diagram shown is a schematic representation of another exemplary embodiment of the gate drive circuit of this disclosure. In this circuit, multiple second switching circuits CN2 can be directly connected to the start signal line STV. The start signal line STV can extend along the cascading direction of the shift register units.
[0093] In this exemplary embodiment, as Figure 5 As shown, the first switching circuit CN1 may include: a first transistor T1, the first terminal of the first transistor T1 is connected to the signal output terminal OUT of its corresponding shift register unit GOA, the second terminal is connected to the signal input terminal IN of the next-level shift register unit GOA, and the gate is connected to the control signal line DW.
[0094] In this exemplary embodiment, as Figure 5 As shown, the second switching circuit CN2 includes a second transistor T2. The first terminal of the second transistor T2 is connected to the start signal line STV, the second terminal is connected to the signal input terminal IN of its corresponding shift register unit GOA, and the gate is connected to the control signal line DW. The first transistor T1 is an N-type transistor, and the second transistor T2 is a P-type transistor.
[0095] In this exemplary embodiment, as Figure 5 As shown, the second switching circuit CN2 includes a switching transistor. It should be understood that in other exemplary embodiments, the second switching circuit CN2 may also include multiple switching transistors connected in series.
[0096] Compared to Figure 3 The gate drive circuit shown is Figure 5 In the gate drive circuit shown, the second switch circuit CN2 is directly connected to the start signal line STV, which avoids the problem that the voltage at the input terminal IN of the lower-level shift register unit is lower than the voltage at the input terminal IN of the upper-level shift register unit due to the resistance of the second switch circuit CN2 itself.
[0097] Compared to Figure 5 The gate drive circuit shown is Figure 3 The start signal line STV in the gate drive circuit shown does not need to extend along the cascading direction of the shift register unit, which facilitates the layout design of the gate drive circuit and the implementation of a narrow bezel design for the display panel.
[0098] In this exemplary embodiment, as Figures 3-5 As shown, the second transistor T2 and the third transistor T3 can be low-temperature polysilicon transistors, and the first transistor T1 can be a metal-oxide-semiconductor transistor. Metal-oxide-semiconductor transistors have a smaller turn-off leakage current, thus avoiding large leakage current between shift register cells in the second mode.
[0099] In this exemplary embodiment, as Figures 3-5 As shown, multiple first switching circuits CN1 are connected to the control signal line DW. Each first switching circuit CN1 responds to the signal from the control signal line DW to connect its corresponding shift register unit GOA's signal output terminal OUT and the next-level shift register unit GOA's signal input terminal IN. Multiple second switching circuits CN2 are also connected to the control signal line DW. Each second switching circuit CN2 responds to the signal from the control signal line DW to connect the start signal line STV and the shift register unit GOA's signal input terminal IN. The conduction levels of the first switching circuits CN1 and CN2 are logically opposite. This gate drive circuit can control both the first switching circuits CN1 and CN2 through a single control signal line DW.
[0100] It should be noted that cascaded upper-level shift register units and lower-level shift register units can be placed adjacently or not. For example, ... Figures 3-5 As shown, the nth-level shift register unit and the (n+1)th-level shift register unit are cascaded, meaning that the cascaded upper-level shift register units and lower-level shift register units are arranged adjacently, where n is a positive integer greater than or equal to 1. It should be understood that in other exemplary embodiments, the nth-level shift register unit may also be cascaded with the (n+m)th-level shift register unit, meaning that the cascaded upper-level shift register units and lower-level shift register units are not arranged adjacently, where n and m are positive integers greater than or equal to 1.
[0101] like Figure 6 The diagram shown is a structural schematic of an exemplary embodiment of the display panel disclosed herein. The display panel includes a pixel driving circuit (Pix) and... Figure 3 The gate driving circuit Cg is shown. The display panel may include two gate driving circuits Cg, each connected to both ends of a gate line. The gate driving circuits Cg provide gate driving signals to the pixel driving circuit Pix through the gate line. The gate line may extend along the row direction, and the two gate driving circuits may be located in the border areas on both sides of the display area in the row direction. It should be understood that in other exemplary embodiments, the display panel may also have only one gate driving circuit.
[0102] like Figure 7 The diagram shown is a structural schematic of an exemplary embodiment of the display panel disclosed herein. The display panel includes a pixel driving circuit (Pix) and... Figure 5 The gate driving circuit Cg is shown. The display panel may include two gate driving circuits Cg, each connected to both ends of a gate line. The gate driving circuits Cg provide gate driving signals to the pixel driving circuit Pix through the gate line. The gate line may extend along the row direction, and the two gate driving circuits may be located in the border areas on both sides of the display area in the row direction. It should be understood that in other exemplary embodiments, the display panel may also have only one gate driving circuit.
[0103] like Figure 8The diagram shown is a schematic representation of the shift register unit in an exemplary embodiment of the gate drive circuit of this disclosure. The shift register unit includes: a first input circuit 11, a second input circuit 12, a pull-up circuit 2, a coupling circuit 3, an isolation circuit 4, a first output circuit 51, and a second output circuit 52. The first input circuit 11 is connected to the signal input terminal IN, the first node N1, and the clock signal terminal CK. The first input circuit is used to respond to the signal at the clock signal terminal CK to transmit the signal at the signal input terminal IN to the first node N1. The second input circuit 12 is connected to the first power supply terminal VGL, the second node N2, the third node N3, the fourth node N4, and the clock signal terminal CK. The second input circuit is used to respond to the signal at the second node N2 to transmit the signal at the first power supply terminal VGL to the third node N3, and to respond to the signal at the clock signal terminal CK to transmit the signal at the third node N3 to the fourth node N4. The pull-up circuit 2 is connected to the signal input terminal IN, the second power supply terminal VGH, the second node N2, and the third node N3. The pull-up circuit 2 is used to respond to the signal at the signal input terminal IN to transmit the signal at the second power supply terminal VGH to the second node N2 and the third node N3. Point N3; Coupling circuit 3 connects clock signal terminal CK and second node N2, and is used to couple the voltage change of clock signal terminal CK to second node N2; Isolation circuit 4 connects first node N1, fifth node N5, and first power supply terminal VGL, and is used to respond to the signal of first power supply terminal VGL to connect first node N1 and fifth node N5; First output circuit 51 connects fifth node N5, signal output terminal OUT, and first power supply terminal VGL, and is used to respond to the signal of fifth node N5 to transmit the signal of first power supply terminal VGL to signal output terminal OUT; Second output circuit 52 connects fourth node N4, signal output terminal OUT, and second power supply terminal VGH, and is used to respond to the signal of fourth node N4 to transmit the signal of second power supply terminal VGH to signal output terminal OUT.
[0104] In this exemplary embodiment, as Figure 8As shown, the first input circuit 11 includes a fourth transistor T4, whose first terminal is connected to the signal input terminal IN, second terminal is connected to the first node N1, and gate is connected to the clock signal terminal CK. The second input circuit includes a fifth transistor T5 and a sixth transistor T6. The first terminal of the fifth transistor T5 is connected to the first power supply terminal VGL, second terminal is connected to the third node N3, and gate is connected to the second node N2; the first terminal of the sixth transistor T6 is connected to the third node N3, second terminal is connected to the fourth node N4, and gate is connected to the clock signal terminal CK. The pull-up circuit 2 includes a seventh transistor T7 and an eighth transistor T8. The first terminal of the seventh transistor T7 is connected to the second power supply terminal VGH, second terminal is connected to the second node N2, and gate is connected to the signal input terminal IN; the first terminal of the eighth transistor T8 is connected to the second power supply terminal VGH, second terminal is connected to the third node N3, and gate is connected to the signal input terminal IN. The coupling circuit includes a first capacitor C1, which is connected between the clock signal terminal CK and the second node N2. The isolation circuit 4 includes a ninth transistor T9, whose first terminal is connected to the first node N1, its second terminal is connected to the fifth node N5, and its gate is connected to the first power supply terminal VGL. The first output circuit 51 includes a tenth transistor T10 and a second capacitor C2. The first terminal of the tenth transistor T10 is connected to the first power supply terminal VGL, its second terminal is connected to the signal output terminal OUT, and its gate is connected to the fifth node N5. The second capacitor C2 is connected between the fifth node N5 and the signal output terminal OUT. The second output circuit 52 includes an eleventh transistor T11 and a third capacitor C3. The first terminal of the eleventh transistor T11 is connected to the second power supply terminal VGH, its second terminal is connected to the signal output terminal OUT, and its gate is connected to the fourth node N4. The third capacitor C3 is connected between the fourth node N4 and the second power supply terminal VGH.
[0105] In this exemplary embodiment, as Figure 8 As shown, transistors four through eleven are P-type transistors, the first power supply terminal VGL is a low-level power supply signal terminal, and the second power supply terminal VGH is a high-level power supply signal terminal.
[0106] In this exemplary embodiment, as Figure 8 As shown, transistors four through eleven can be low-temperature polycrystalline silicon transistors.
[0107] This shift register unit can be applied to Figures 3-5 In the gate drive circuit shown.
[0108] like Figure 9 The diagram shown is a schematic representation of an exemplary embodiment of the gate driving circuit of this disclosure. The gate driving circuit may include multiple... Figure 8The shift register unit GOA shown is configured with multiple shift register units GOA cascaded together. The signal output terminal OUT of the previous shift register unit GOA is connected to the signal input terminal IN of the adjacent next-level shift register unit GOA. The gate drive circuit may further include a first clock signal line CK1 and a second clock signal line CK2. The first clock signal line CK1 is connected to the clock signal terminal CK in the odd-numbered shift register units, and the second clock signal line CK2 is connected to the clock signal terminal CK in the even-numbered shift register units.
[0109] like Figure 10 As shown, Figure 9 The timing diagrams of each node in a driving method of the gate driving circuit shown are as follows: STV is the timing diagram of the signal on the start signal line, CK1 is the timing diagram of the signal on the first clock signal line, CK2 is the timing diagram of the signal on the second clock signal line, and OUT is the timing diagram of the signal on the output terminal of the first-stage shift register unit.
[0110] The driving method of this shift register unit may include a first stage t1, a second stage t2, a third stage t3, a fourth stage t4, a fifth stage t5, a sixth stage t6, a seventh stage t7, and an eighth stage t8.
[0111] When the first switching circuit CN1 is turned on and the second switching circuit CN2 is turned off, this exemplary embodiment will be described using the driving method of the first-stage shift register unit as an example:
[0112] In the first stage t1, the signal input terminal IN is at a high level, the clock signal terminal CK is at a high level, the fourth node N4 maintains the high level of the previous stage, the eleventh transistor T11 is turned off, the fifth node N5 maintains the low level of the previous stage, the tenth transistor T10 is turned on, and the first power supply terminal VGL inputs a low-level signal to the signal output terminal OUT.
[0113] In the second stage t2, the signal input terminal IN is at a high level, the clock signal terminal CK is at a low level, the fourth transistor T4 is turned on, the signal input terminal IN inputs a high-level signal to the fifth node N5, and the tenth transistor T10 is turned off; under the coupling effect of the first capacitor C1, the second node N2 is pulled low, the fifth transistor T5 is turned on, the first power supply terminal VGL inputs a low-level signal to the fourth node N4, the eleventh transistor T11 is turned on, and the second power supply terminal VGH inputs a high-level signal to the signal output terminal OUT.
[0114] In the third stage t3, the signal input terminal IN is at a high level, the clock signal terminal CK is at a high level, the fifth node N5 maintains a high level signal, the tenth transistor T10 is turned off, the fourth node N4 maintains a low level signal, the eleventh transistor T11 is turned on, and the second power supply terminal VGH inputs a high level signal to the signal output terminal OUT.
[0115] In the fourth stage t4, the signal input terminal IN is at a high level, the clock signal terminal CK is at a low level, the fourth transistor T4 is turned on, the signal input terminal IN inputs a high-level signal to the fifth node N5, and the tenth transistor T10 is turned off; under the coupling effect of the first capacitor C1, the second node N2 is pulled low, the fifth transistor T5 is turned on, the first power supply terminal VGL inputs a low-level signal to the fourth node N4, the eleventh transistor T11 is turned on, and the second power supply terminal VGH inputs a high-level signal to the signal output terminal OUT.
[0116] In the fifth stage t5, the signal input terminal IN is at a high level, the clock signal terminal CK is at a high level, the fifth node N5 maintains a high level signal, the tenth transistor T10 is turned off, the fourth node N4 maintains a low level signal, the eleventh transistor T11 is turned on, and the second power supply terminal VGH inputs a high level signal to the signal output terminal OUT.
[0117] In the sixth stage t6, the signal input terminal IN is at a high level, the clock signal terminal CK is at a low level, the fourth transistor T4 is turned on, the signal input terminal IN inputs a high-level signal to the fifth node N5, and the tenth transistor T10 is turned off; under the coupling effect of the first capacitor C1, the second node N2 is pulled low, the fifth transistor T5 is turned on, the first power supply terminal VGL inputs a low-level signal to the fourth node N4, the eleventh transistor T11 is turned on, and the second power supply terminal VGH inputs a high-level signal to the signal output terminal OUT.
[0118] In the seventh stage t7, the signal input terminal IN is at a low level, the clock signal terminal CK is at a high level, the fifth node N5 maintains a high level signal, the tenth transistor T10 is turned off, the fourth node N4 maintains a low level signal, the eleventh transistor T11 is turned on, and the second power supply terminal VGH inputs a high level signal to the signal output terminal OUT.
[0119] In stage 8 t8, the signal input terminal IN and the clock signal terminal CK are at low level. The signal input terminal IN inputs a low-level signal to the fifth node N5, the tenth transistor T10 is turned on, and the first power supply terminal VGL inputs a low-level signal to the signal output terminal OUT. The sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned on, the second power supply terminal VGH inputs a high-level signal to the second node N2, the third node N3, and the fourth node N4, and the eleventh transistor T11 is turned off.
[0120] This shift register unit can shift and output the signal at the input terminal IN through the output terminal OUT.
[0121] When the first switching circuit CN1 is turned off and the second switching circuit CN2 is turned on, aging processing signals can be provided to each signal terminal in the shift register unit to achieve rapid aging of the shift register unit. The aging processing signal can be a DC voltage signal. This signal can ensure that the gate-source voltage difference of the target transistor is greater than or equal to a first threshold voltage, and that the drain-source voltage difference of the target transistor is less than or equal to a second threshold voltage, thus achieving rapid aging of the target transistor. The first threshold voltage can be 25V, and the second threshold voltage can be -18V. For example, when aging the seventh transistor T7, an 8V DC voltage signal can be provided to the clock signal terminal CK, a 12V DC voltage signal can be input to the signal input terminal IN, and a -18V DC voltage signal can be input to the first power supply terminal VGL and the second power supply terminal VGH.
[0122] In this exemplary embodiment, the DC voltage signals input to each signal terminal in the shift register unit constitute the aging processing signals. Different transistors can be aged using different aging processing signals, and different transistors can be aged one by one. Furthermore, in other exemplary embodiments, different transistors can also be aged using the same set of aging processing signals, and multiple transistors can be aged simultaneously. For example, the seventh transistor T7 and the eighth transistor T8 can be aged simultaneously. Correspondingly, the signal input terminal IN can receive 12V, the second power supply terminal VGH can receive 8V, the clock signal terminal CK can receive -18V, and the first power supply terminal VGL can receive -18V.
[0123] This exemplary embodiment also provides a display panel, which may include the gate driving circuit described above. This display panel can be applied to display devices such as mobile phones, tablets, televisions, and automotive displays.
[0124] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.
[0125] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is defined only by the appended claims.
Claims
1. A gate driving circuit, wherein, The gate driving circuit includes: Multiple shift register units are cascaded together, with the signal output terminal of the upper-level shift register unit connected to the signal input terminal of the lower-level shift register unit; Multiple first switching circuits are provided, and the first switching circuits are correspondingly configured with the shift register unit. The signal output terminal of the shift register unit is connected to the signal input terminal of the next-level shift register unit through its corresponding first switching circuit. The first switching circuit is used to respond to a control signal to connect the signal output terminal of its corresponding shift register unit and the signal input terminal of the next-level shift register unit. The start signal line is connected to the signal input terminal of the first-stage shift register unit; Multiple second switching circuits are provided, and the second switching circuits are correspondingly arranged with shift register units other than the first-stage shift register unit. The second switching circuit is connected between the start signal line and the signal input terminal of the corresponding shift register unit. The second switching circuit is used to respond to a control signal to connect the start signal line and the signal input terminal of the shift register unit.
2. The gate driving circuit according to claim 1, wherein, The second switching circuit includes one or more switching transistors; The second switching circuit corresponding to the secondary shift register unit is connected to the start signal line; In the shift register unit located below the secondary shift register unit, the second switching circuit corresponding to the lower shift register unit is indirectly connected to the start signal line through at least some of the switching transistors in the second switching circuit corresponding to the upper shift register unit.
3. The gate driving circuit according to claim 1, wherein, Multiple second switching circuits are directly connected to the start signal line.
4. The gate driving circuit according to any one of claims 1-3, wherein, Multiple first switching circuits are connected to control signal lines. The first switching circuit is used to respond to the signal of the control signal line to connect the signal output terminal of its corresponding shift register unit and the signal input terminal of the next-level shift register unit. Multiple second switching circuits are connected to the control signal line, and the second switching circuits are used to respond to the signal of the control signal line to connect the start signal line and the signal input terminal of the shift register unit; The conduction level of the first switching circuit and the conduction level of the second switching circuit are logically opposite.
5. The gate driving circuit according to claim 2, wherein, The first switching circuit includes: The first transistor has its first terminal connected to the signal output terminal of its corresponding shift register unit, its second terminal connected to the signal input terminal of the next-level shift register unit, and its gate connected to the control signal line. The second switching circuit includes: The second transistor has its gate connected to the control signal line; The third transistor has its first terminal connected to the second terminal of the second transistor in the same second switching circuit, and its second terminal connected to the signal input terminal of its corresponding shift register unit. Its gate is connected to the control signal line. In this case, the first terminal of the second transistor corresponding to the secondary shift register unit is connected to the start signal line; In the shift register unit located below the secondary shift register unit, the first terminal of the second transistor corresponding to the lower shift register unit is connected to the second terminal of the second transistor corresponding to the upper shift register unit; The first transistor is an N-type transistor, and the second and third transistors are P-type transistors.
6. The gate driving circuit according to claim 2, wherein, The first switching circuit includes: The first transistor has its first terminal connected to the signal output terminal of its corresponding shift register unit, its second terminal connected to the signal input terminal of the next-level shift register unit, and its gate connected to the control signal line. The second switching circuit includes: The second transistor has its gate connected to the control signal line and its second terminal connected to the signal input terminal of its corresponding shift register unit. In this case, the first terminal of the second transistor corresponding to the secondary shift register unit is connected to the start signal line; In the shift register unit located below the secondary shift register unit, the first terminal of the second transistor corresponding to the lower shift register unit is connected to the second terminal of the second transistor corresponding to the upper shift register unit; The first transistor is an N-type transistor, and the second transistor is a P-type transistor.
7. The gate driving circuit according to claim 3, wherein, The first switching circuit includes: The first transistor has its first terminal connected to the signal output terminal of its corresponding shift register unit, its second terminal connected to the signal input terminal of the next-level shift register unit, and its gate connected to the control signal line. The second switching circuit includes: The second transistor has a first terminal connected to the start signal line, a second terminal connected to the signal input terminal of its corresponding shift register unit, and a gate connected to the control signal line. The first transistor is an N-type transistor, and the second transistor is a P-type transistor.
8. The gate driving circuit according to claim 1, wherein, The shift register unit includes: A first input circuit is connected to a signal input terminal, a first node, and a clock signal terminal. The first input circuit is used to respond to the signal of the clock signal terminal to transmit the signal of the signal input terminal to the first node. The second input circuit is connected to the first power supply terminal, the second node, the third node, the fourth node, and the clock signal terminal. The second input circuit is used to respond to the signal of the second node to transmit the signal of the first power supply terminal to the third node, and to respond to the signal of the clock signal terminal to transmit the signal of the third node to the fourth node. A pull-up circuit is connected to the signal input terminal, the second power supply terminal, the second node, and the third node. The pull-up circuit is used to respond to the signal at the signal input terminal to transmit the signal at the second power supply terminal to the second node and the third node. A coupling circuit connects the clock signal terminal and the second node, and the coupling circuit is used to couple the voltage change of the clock signal terminal to the second node; An isolation circuit is provided to connect the first node, the fifth node, and the first power supply terminal. The isolation circuit is used to respond to the signal from the first power supply terminal to connect the first node and the fifth node. A first output circuit is connected to the fifth node, a signal output terminal, and a first power supply terminal. The first output circuit is used to respond to the signal of the fifth node to transmit the signal of the first power supply terminal to the signal output terminal. The second output circuit is connected to the fourth node, the signal output terminal, and the second power supply terminal. The second output circuit is used to respond to the signal of the fourth node to transmit the signal of the second power supply terminal to the signal output terminal.
9. The gate driving circuit according to claim 8, wherein, The first input circuit includes: The fourth transistor has its first terminal connected to the signal input terminal, its second terminal connected to the first node, and its gate connected to the clock signal terminal. The second input circuit includes: The fifth transistor has its first terminal connected to the first power supply terminal, its second terminal connected to the third node, and its gate connected to the second node. The sixth transistor has its first terminal connected to the third node, its second terminal connected to the fourth node, and its gate connected to the clock signal terminal. The pull-up circuit includes: The seventh transistor has its first terminal connected to the second power supply terminal, its second terminal connected to the second node, and its gate connected to the signal input terminal. The eighth transistor has its first terminal connected to the second power supply terminal, its second terminal connected to the third node, and its gate connected to the signal input terminal. The coupling circuit includes: The first capacitor is connected between the clock signal terminal and the second node; The isolation circuit includes: The ninth transistor has its first terminal connected to the first node, its second terminal connected to the fifth node, and its gate connected to the first power supply terminal. The first output circuit includes: The tenth transistor has its first terminal connected to the first power supply terminal, its second terminal connected to the signal output terminal, and its gate connected to the fifth node. The second capacitor is connected between the fifth node and the signal output terminal; The second output circuit includes: The eleventh transistor has its first terminal connected to the second power supply terminal, its second terminal connected to the signal output terminal, and its gate connected to the fourth node. The third capacitor is connected between the fourth node and the second power supply terminal.
10. A display panel, wherein, The display panel includes the gate driving circuit according to any one of claims 1-9.