VCSEL array chip packaging structure and heat dissipation device thereof

Abstract

This utility model relates to a VCSEL array chip packaging structure and its heat dissipation device, belonging to the field of chip packaging technology. It includes a heat sink substrate and chip components. A plating assembly is provided on the heat sink substrate, and the plating assembly has a mounting area for chip component soldering. Multiple chip components are linearly distributed with gaps between them and connected in series. Each chip component includes multiple chips, which are spaced apart and arranged parallel to each other, thereby reducing the power requirements of the chips and avoiding excessive current and heat generation. This utility model provides a VCSEL array chip packaging structure and its heat dissipation device, which improves space utilization and flexibility through optimized chip component layout. The plating assembly significantly enhances heat dissipation performance and protects the heat sink substrate from oxidation. The modular design of the heat dissipation assembly further improves the heat dissipation effect. The parallel and series connection of the chip components reduces power requirements and power consumption.

Description

Technical Field

[0001] This utility model relates to a VCSEL array chip packaging structure and its heat dissipation device, belonging to the field of chip packaging technology. Background Technology

[0002] Chips, as a general term for semiconductor components, need to form a chip package structure together with a substrate with a conductive structure after manufacturing to realize circuit functions. Chip packaging is the bridge connecting the internal and external circuits of a chip. By connecting the chip contacts to the pins of the package shell with wires, and then establishing connections with other devices through printed circuit board wires, it plays a key role in fields such as CPUs and LSI integrated circuits. Its development trend is towards increased pin count, reduced spacing, reduced weight, improved reliability, and greater ease of use.

[0003] In existing technologies, laser heat sinks typically only accommodate one laser chip due to process limitations. Material limitations on chip heat dissipation restrict chip space layout; the conductive connection method of the chip is limited by the heat sink design; and as the power of the laser chip increases, the chip cost rises sharply, and the difficulty of heat dissipation increases exponentially, leading to new challenges in packaging costs and technology. Specifically, existing technologies have the following shortcomings: First, the number of chips that can be assembled in the heat sink is limited, and the space layout is inflexible, making it impossible to flexibly adjust the number and layout of chips according to actual needs, thus limiting the application scenarios of the chip packaging structure; Second, the performance of heat dissipation materials is limited, resulting in low heat dissipation efficiency, which cannot dissipate the heat generated by the chip in a timely manner, leading to an increase in the chip's operating temperature and affecting the chip's stability and reliability; Third, heat dissipation is difficult and costs surge at high power levels. As the power of laser chips increases, existing heat dissipation technologies cannot meet the heat dissipation requirements, necessitating more complex and expensive heat dissipation solutions, increasing packaging costs and technical difficulty. Utility Model Content

[0004] This invention provides a VCSEL array chip packaging structure and its heat dissipation device to solve the problems of low space utilization, long heat dissipation path and difficulty in cost control in the prior art.

[0005] This utility model provides a VCSEL array chip packaging structure and its heat dissipation device, which includes a heat sink substrate and a chip assembly. The heat sink substrate is provided with a plating assembly that matches the chip assembly, and the plating assembly is provided with a mounting area for soldering the chip assembly.

[0006] The chip assembly comprises multiple chips, which are linearly distributed with gaps between them and connected in series. Each chip assembly includes multiple chips, which are spaced apart and arranged in parallel to each other, thereby reducing the power requirements of the chips and avoiding excessive current and heat generation.

[0007] Preferably, the plating assembly includes a copper plating layer, a nickel plating layer, and a gold plating layer, which are disposed on the heat sink substrate from bottom to top.

[0008] Preferably, the mounting area is located on a gold plating layer, and the chip is soldered using gold-tin solder.

[0009] Preferably, the heat sink substrate has a heat dissipation groove matching the chip assembly at the end away from the chip assembly.

[0010] Preferably, a heat dissipation device includes a heat dissipation component located on a chip package structure.

[0011] Preferably, the heat dissipation component is located on the heat sink substrate, and the heat dissipation component includes a cover plate and a heat dissipation module. The cover plate is in contact with the chip by having an insulating layer and dissipates heat through the heat dissipation module.

[0012] Preferably, the insulating layer covers multiple chip components on the heat sink substrate, and the heat sink substrate is provided with a limiting groove that matches the insulating layer. The insulating layer is fixedly connected to the heat sink substrate by snapping into the limiting groove.

[0013] Preferably, a heat-conducting layer is provided between the insulating layer and the cover plate, the heat-conducting layer is provided with heat-conducting protrusions for increasing the contact area, the top of the insulating layer is provided with a second heat dissipation groove that matches the heat-conducting protrusions, and the heat-conducting protrusions are engaged with the second heat dissipation groove.

[0014] Preferably, the heat dissipation module is designed as multiple segments and located on the top of the cover plate, and the multiple heat dissipation modules are linearly distributed on the cover plate with gaps between them.

[0015] Preferably, the heat dissipation module includes multiple heat dissipation fins, which are parallel to each other and have gaps between them, and the heat dissipation fins are perpendicular to the heat sink substrate.

[0016] The beneficial effects of this utility model are:

[0017] This invention provides a VCSEL array chip packaging structure and its heat dissipation device. By arranging multiple chip components on a heat sink substrate, with each component containing multiple parallel chips spaced apart, it achieves flexible chip layout, avoiding the limitation of traditional heat sinks that can only assemble a single chip. This improves space utilization and allows the packaging structure to adapt to more diverse application scenarios. Multiple chips in each chip component are connected in series, while multiple chip components are connected in parallel, reducing power requirements and indirectly reducing Joule heating on a single path. This avoids heat concentration caused by excessive current, improving chip efficiency and stability. A copper plating layer, a nickel plating layer, and a gold plating layer are sequentially arranged on the heat sink substrate. The high thermal conductivity of copper, the oxidation resistance of nickel, and the good electrical conductivity of gold collectively enhance the heat dissipation capacity and electrical connection reliability of the heat sink substrate. The copper plating layer rapidly conducts the heat generated by the chip, the nickel plating layer prevents oxidation of the copper plating layer, and the gold plating layer... To ensure long-term reliability and low resistance of the solder interface, a heat sink substrate has a heat dissipation groove at the bottom, increasing the heat dissipation area. Simultaneously, the heat dissipation assembly includes a cover plate and a heat dissipation module. The cover plate contacts the chip through an insulating layer and dissipates heat through the heat dissipation module, enhancing air convection and improving heat dissipation efficiency. The insulating layer not only covers the chip to prevent external circuit interference but also tightly engages with the limiting groove on the heat sink substrate through limiting protrusions and rings, ensuring sealing and structural stability. This effectively prevents external factors from affecting the chip assembly and improves the reliability of the entire packaging structure. A thermally conductive layer is located between the insulating layer and the cover plate, with thermally conductive protrusions at the bottom. These protrusions engage with a second heat dissipation groove on the insulating layer, increasing the contact area and improving heat dissipation. Multiple heat dissipation fins in the heat dissipation module are parallel to each other with gaps, increasing the contact area with air. Their arrangement perpendicular to the heat sink substrate generates stronger turbulence, improving air convection heat transfer efficiency. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the overall structure of a VCSEL array chip packaging structure and its heat dissipation device according to the present invention.

[0019] Figure 2 This is a front view schematic diagram of a VCSEL array chip packaging structure and its heat dissipation device according to the present invention.

[0020] Figure 3 This is another structural schematic diagram of a VCSEL array chip packaging structure and its heat dissipation device according to the present invention.

[0021] Figure 4 This is an exploded view of the VCSEL array chip packaging structure and its heat dissipation device according to the present invention.

[0022] Figure 5This is another exploded view of the VCSEL array chip packaging structure and its heat dissipation device according to the present invention.

[0023] Figure 6 This is an exploded view of another angle of the VCSEL array chip packaging structure and its heat dissipation device according to this utility model.

[0024] Figure 7 This is a schematic diagram of the plating component structure of a VCSEL array chip packaging structure and its heat dissipation device according to the present invention.

[0025] Figure 8 This is a schematic diagram of the heat sink substrate of a VCSEL array chip packaging structure and its heat dissipation device according to the present invention.

[0026] Figure 9 This is a schematic diagram of the insulating layer structure of a VCSEL array chip packaging structure and its heat dissipation device according to the present invention.

[0027] In the figure: 1. Heat sink substrate, 11. Plating assembly, 111. Copper plating, 112. Nickel plating, 113. Gold plating, 12. First heat dissipation groove, 13. Limiting groove, 2. Chip assembly, 21. Chip, 22. Thermal conductive layer, 221. Thermal conductive protrusion, 3. Heat dissipation assembly, 31. Cover plate, 311. Insulating layer, 3111. Limiting protrusion, 3112. Limiting ring, 3113. Second heat dissipation groove, 32. Heat dissipation module, 321. Heat dissipation fins. Detailed Implementation

[0028] The preferred embodiments of this utility model will now be described in detail with reference to the accompanying drawings.

[0029] This invention provides a VCSEL array chip packaging structure and its heat dissipation device, which includes a heat sink substrate 1, a chip assembly 2, and a heat dissipation component 3 located on the heat sink substrate 1 to dissipate heat from the chip assembly 2. The heat sink substrate 1 is provided with a plating component 11 that matches the chip assembly 2. The plating component 11 includes a copper plating layer 111, a nickel plating layer 112, and a gold plating layer 113, wherein the copper plating layer 111, nickel plating layer 112, and gold plating layer 113 are arranged sequentially from bottom to top on the heat sink substrate 1. The plating component 11 improves the heat dissipation capacity of the heat sink substrate 1, and the copper plating layer 111 enhances the heat dissipation capacity of the heat sink substrate 1. A layer of nickel is plated on layer 111 to effectively prevent the heat sink substrate 1 from oxidizing when heated. The gold plating layer 113 has a mounting area that matches the chip assembly 2. The chip assembly 2 is located inside the mounting area and is soldered to the gold plating layer 113 by gold solder. There are multiple chip assemblies 2, and the multiple gold solders are connected in parallel with each other. There are gaps between the multiple chip assemblies 2. The chip assembly 2 includes multiple chips 21. The multiple chips 21 are connected in series on the gold plating layer 113. The multiple chips 21 are parallel to each other and there are gaps, which facilitates heat dissipation between the multiple chips 21.

[0030] The bottom end of the heat sink substrate 1, away from the chip assembly 2, is provided with a first heat dissipation groove 12 that matches the chip assembly 2.

[0031] The heat dissipation assembly 3 is located on the heat sink substrate 1. The heat dissipation assembly 3 includes a cover plate 31 and a heat dissipation module 32. The cover plate 31 is fixed on the heat sink substrate 1 and covers multiple chip assemblies 2. The cover plate 31 is provided with an insulating layer 311 that is connected to the multiple chips 21. The insulating layer 311 is in contact with the chips 21, covering the multiple chips 21 and being fixedly connected to the heat sink substrate 1. The heat sink substrate 1 is provided with an annularly arranged limiting groove 13. The limiting groove 13 has a trapezoidal cross-section. The bottom of the insulating layer 311 is provided with a limiting protrusion 3111 that matches the cross-section of the limiting groove 13. The limiting protrusion 3111 is engaged inside the limiting groove 13. The outer wall of the limiting protrusion 3111 is provided with Multiple limiting rings 3112 are fixedly connected to the limiting protrusions 3111. The limiting rings 3112 are in contact with the inner walls on both sides of the limiting groove 13 and are made of elastic material to further ensure the seal. The cover plate 31 and the insulating layer 311 are connected by a heat-conducting layer 22. The top of the heat-conducting layer 22 is in contact with the cover plate 31. The bottom of the heat-conducting layer 22 is provided with a serpentine heat-conducting protrusion 221. The heat-conducting protrusion 221 is fixedly connected to the heat-conducting layer 22. The insulating layer 311 is provided with a second heat dissipation groove 3113 that matches the heat-conducting protrusion 221. The two plating components 11 are snapped onto the second heat dissipation groove 3113 to increase the contact area between the heat-conducting layer 22 and the insulating layer 311.

[0032] The heat dissipation module 32 is located on the outer surface of the cover plate 31 and the insulating layer 311 to dissipate heat. Multiple heat dissipation modules 32 are provided on the cover plate 31. The multiple heat dissipation modules 32 are linearly distributed on the cover plate 31 and there are gaps between the multiple heat dissipation modules 32. The heat dissipation module 32 includes multiple heat dissipation fins 321. The multiple heat dissipation fins 321 are parallel to each other and there are gaps between them, which can increase the contact area with air and enhance the heat dissipation effect. The multiple heat dissipation fins 321 are perpendicular to each other with the heat sink substrate 1.

[0033] In use, a copper plating layer 111 is provided on the heat sink substrate 1 to improve its heat dissipation capacity and cooperate with the first heat dissipation groove 12 to dissipate heat from the chip 21. A nickel plating layer 112 is provided on the copper plating layer 111 to prevent the copper plating layer 111 from oxidizing when heated. A gold plating layer 113 is provided on the nickel plating layer 112. The gold plating layer 113 has good conductivity, reducing contact resistance, and has good resistance to discoloration, ensuring the long-term reliability and low resistance of the solder interface. Four sets of chip assemblies 2 are provided on the heat sink substrate 1. The chip assemblies 2 are soldered to the mounting area on the gold plating layer 113 with gold-tin solder. The four sets of chip assemblies 2 are connected in parallel with each other. Each set of chip assemblies 2 includes four chips 21. The four chips 21 are connected in series with each other. Through the four-series and four-parallel arrangement, the power requirements are reduced, and the Joule heat on a single path is indirectly reduced. The chips 21 are also dispersed, improving the heat dissipation effect of the chips 21 and avoiding high heat concentration in a very small area. To achieve the goal of dispersing heat load and reducing power demand, the insulating layer 311 contacts the chip 21 during use. The bottom of the insulating layer 311 is secured in the limiting groove 13 by the limiting protrusion 3111 to cover the chip assembly 2, ensuring that the chip 21 is not interfered with by external circuits and increasing safety. The limiting protrusion 3111 further ensures the sealing between itself and the limiting groove 13 through the limiting ring 3112. The heat dissipation module 32 dissipates heat from the chip 21. The heat-conducting layer 22 is secured to the insulating layer 311 by the heat-conducting protrusion 221. The heat-conducting layer 22 is serpentine in shape, which can increase the contact area between the heat-conducting layer 22 and the insulating layer 311, thereby ensuring good heat dissipation effect. Multiple heat dissipation modules 32 are arranged in segments on the cover plate 31, which can increase the contact area between multiple heat dissipation fins 321 and the air, and generate stronger turbulence, improve the convective heat transfer efficiency, and avoid the problems of traditional heat dissipation fins being straight, having limited surface area, and having low contact efficiency with air.

[0034] Compared with existing technologies, a plating assembly 11 is provided on the heat sink substrate 1, with a copper plating layer 111 located at the bottom. Copper has excellent thermal conductivity. By providing a copper plating layer 111 on the heat sink substrate 1, the heat dissipation capacity of the heat sink substrate 1 can be significantly improved, the heat generated by the chip 21 can be conducted away more quickly, the operating temperature of the chip 21 can be reduced, and the stability and reliability of the chip 21 can be improved. A nickel plating layer 112 is plated on the copper plating layer 111. Nickel has excellent anti-oxidation properties and can effectively prevent the copper plating layer 111 from oxidizing when heated. During the operation of the chip 21, heat is generated. Without the protection of the nickel plating layer 112, the copper plating layer 111 is easily oxidized by reacting with oxygen in the air at high temperatures, resulting in a decrease in thermal conductivity and affecting the heat dissipation effect. A gold plating layer 113 is provided on the nickel plating layer 112. Gold has excellent electrical conductivity, which can reduce contact resistance and has good resistance to discoloration. When the chip assembly 2 is soldered to the gold plating layer 113, the gold plating layer 113 can ensure the long-term reliability and low resistance of the soldering interface, further improve the heat dissipation efficiency, and at the same time ensure a good electrical connection between the chip assembly 2 and the heat sink substrate 1. The heat sink substrate 1 is provided with four sets of chip assemblies 2. The chip assemblies 2 are soldered to the mounting area on the gold plating layer 113 by gold solder. The four sets of chip assemblies 2 are connected in parallel with each other. Each set of chip assembly 2 includes four chips 21. The four chips 21 are connected in series with each other, which reduces the power requirements and indirectly reduces the Joule heat on a single path. It can distribute the current more reasonably, reduce the heat generated by excessive current, improve the working efficiency and stability of the chip, and disperse the chip 21 to avoid the high concentration of heat in a very small area. The gaps between multiple chips 21 facilitate heat dissipation, effectively dispersing the heat load, reducing the chip's operating temperature, and extending the chip's lifespan. The bottom of the insulating layer 311 is engaged with the heat sink substrate 1 by a limiting protrusion 3111 within a limiting groove 13 to seal the chip assembly 2. A limiting ring 3112 is provided on the limiting protrusion 3111; the limiting ring 3112 is deformed under pressure to further ensure the sealing effect, effectively preventing external factors from affecting the chip assembly 2 and improving the reliability of the entire packaging structure. A thermally conductive layer 22 is provided between the insulating layer 311 and the cover plate 31. The bottom of the thermally conductive layer 22... The part is provided with heat-conducting protrusions 221, which cooperate with the second heat dissipation groove 3113 to increase the contact area with the insulating layer 311, and then dissipate through the heat dissipation module 32, thereby improving the heat dissipation effect. The heat dissipation module 32 is located on the outer surface of the cover plate 31 and dissipates heat with the insulating layer 311. The cover plate 31 is provided with multiple heat dissipation modules 32, which are linearly distributed on the cover plate 31 and have gaps between them. The heat dissipation module 32 includes multiple heat dissipation fins 321, which are parallel to each other and have gaps, which can increase the contact area with air and enhance the heat dissipation effect.The fact that multiple heat dissipation fins 321 are perpendicular to each other with the heat sink substrate 1 can generate stronger turbulence and improve the convective heat transfer efficiency.

[0035] The present invention and its embodiments have been described above. This description is not restrictive, and the accompanying drawings are only one embodiment of the present invention; the actual structure is not limited thereto. In conclusion, if those skilled in the art are inspired by this description and design similar structures and embodiments without departing from the inventive spirit of the present invention, such designs should fall within the protection scope of the present invention.

Claims

1. A VCSEL array chip packaging structure, characterized in that: It includes a heat sink substrate and a chip assembly. The heat sink substrate is provided with a plating assembly that matches the chip assembly, and the plating assembly is provided with a mounting area for soldering the chip assembly. The chip assembly comprises multiple chips, which are linearly distributed with gaps between them and connected in series. Each chip assembly includes multiple chips, which are spaced apart and arranged in parallel to each other, thereby reducing the power requirements of the chips and avoiding excessive current and heat generation.

2. The VCSEL array chip packaging structure according to claim 1, characterized in that: The plating assembly includes a copper plating layer, a nickel plating layer, and a gold plating layer, which are arranged from bottom to top on the heat sink substrate.

3. The VCSEL array chip packaging structure according to claim 2, characterized in that: The mounting area is located on a gold plating layer, and the chip is soldered using gold-tin solder.

4. The VCSEL array chip packaging structure according to claim 1, characterized in that: The heat sink substrate has a heat dissipation groove at the end away from the chip assembly that matches the chip assembly.

5. A heat dissipation device, characterized in that, It includes a heat dissipation component, which is located on the chip packaging structure as described in any one of claims 1 to 4.

6. A heat dissipation device according to claim 5, characterized in that: The heat dissipation component is located on the heat sink substrate. The heat dissipation component includes a cover plate and a heat dissipation module. The cover plate is in contact with the chip through an insulating layer and dissipates heat through the heat dissipation module.

7. A heat dissipation device according to claim 6, characterized in that: The insulating layer covers multiple chip components on the heat sink substrate. The heat sink substrate is provided with a limiting groove that matches the insulating layer. The insulating layer is fixedly connected to the heat sink substrate by snapping into the limiting groove.

8. A heat dissipation device according to claim 7, characterized in that: A heat-conducting layer is provided between the insulating layer and the cover plate. The heat-conducting layer has heat-conducting protrusions for increasing the contact area. The top of the insulating layer has a second heat dissipation groove that matches the heat-conducting protrusions. The heat-conducting protrusions are engaged with the second heat dissipation groove.

9. A heat dissipation device according to claim 6, characterized in that: The heat dissipation module is designed in multiple segments and located on the top of the cover plate. The multiple heat dissipation modules are linearly distributed on the cover plate with gaps between them.

10. A heat dissipation device according to claim 9, characterized in that: The heat dissipation module includes multiple heat dissipation fins, which are parallel to each other and have gaps between them. The heat dissipation fins are perpendicular to the heat sink substrate.

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