Chip package structure and electronic device

Abstract

This application provides a chip packaging structure and an electronic device. The chip packaging structure includes a data processing chip, a memory chip, and an auxiliary chip. The memory chip is electrically connected to the data processing chip. The auxiliary chip includes a capacitor, which is electrically connected to the data processing chip. The electronic device includes the chip packaging structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a chip packaging structure and electronic device. Background Technology

[0002] Chips are a core component of electronic devices. With the development of technologies such as communication, artificial intelligence, and virtual reality, chips need to integrate more functional modules to meet the needs of complex application scenarios.

[0003] The proposed solutions integrate the data processing module and the storage module into a single chip, resulting in a larger chip size and reduced chip performance and yield. Utility Model Content

[0004] This application provides a chip packaging structure and an electronic device.

[0005] A first aspect of this application provides a chip packaging structure, the chip packaging structure comprising:

[0006] Data processing chip;

[0007] A storage chip, electrically connected to the data processing chip;

[0008] An auxiliary chip is provided with a capacitor, which is electrically connected to the data processing chip.

[0009] In some embodiments, the data processing chip, the storage chip, and the auxiliary chip are stacked.

[0010] In some embodiments, the storage chip is located between the data processing chip and the auxiliary chip, and the data storage chip is bonded to both the processing chip and the auxiliary chip.

[0011] In some embodiments, the chip package structure further includes a plurality of conductive structures located on the side of the auxiliary chip away from the memory chip; each of the conductive structures is electrically connected to the data processing chip, and at least one of the conductive structures is electrically connected to the capacitor.

[0012] In some embodiments, the capacitor is a deep trench capacitor.

[0013] In some embodiments, the data processing chip includes a processor; the auxiliary chip is provided with at least one capacitor bank, the capacitor bank including a plurality of spaced deep trench capacitors; each processor and one of the capacitor banks are opposite to each other in the stacking direction of the processing chip and the memory chip, and the processor is electrically connected to the capacitors of the opposite capacitor bank.

[0014] In some embodiments, the active surface of the data processing chip faces the memory chip, and the active surface of the memory chip faces the data processing chip; the chip package structure further includes a first redistribution structure located between the data processing chip and the memory chip; the first redistribution structure includes a first redistribution layer, a plurality of first metal pillars located on the side of the first redistribution layer facing the memory chip, and a second redistribution layer located between the first metal pillars and the memory chip; the first redistribution layer includes a plurality of first traces, the second redistribution layer includes a plurality of second traces, each first trace is connected to the active surface of the data processing chip and the first metal pillar, and each second trace is connected to the first metal pillar; some of the second traces are connected to the active surface of the memory chip.

[0015] In some embodiments, the chip packaging structure further includes a first conductive post penetrating the memory chip, a second conductive post penetrating the auxiliary chip, and a second rewiring structure located between the auxiliary chip and the memory chip; the second rewiring structure includes a third rewiring layer, a plurality of second metal posts located on the side of the third rewiring layer facing the auxiliary chip, and a fourth rewiring layer located between the second metal posts and the auxiliary chip; the third rewiring layer includes a plurality of third traces, and the fourth rewiring layer includes a plurality of fourth traces; the first conductive post is electrically connected to the data processing chip, and each of the third traces is connected to the first conductive post and the second metal post respectively; each of the fourth traces is connected to the second conductive post respectively, and some of the fourth traces are connected to the second metal post; at least one of the fourth traces is electrically connected to the capacitor.

[0016] In some embodiments, the data processing chip includes at least one of a logic chip and a system-on-a-chip.

[0017] A second aspect of this application provides an electronic device comprising the chip packaging structure described above.

[0018] The chip packaging structure provided in this application embodiment separates the data processing chip and the storage chip into independent chips. Compared to solutions that integrate data processing and storage functions into a single chip, this reduces the size of a single chip and avoids performance degradation during manufacturing due to excessive chip size. Furthermore, the data processing chip and the storage chip can employ different process technologies. For example, the data processing chip can use a more advanced process to improve its processing power, while the storage chip can use a more mature and economical process node, thereby reducing the manufacturing cost of the chip packaging structure.

[0019] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0020] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0021] Figure 1 This is a schematic diagram of a chip packaging structure provided in an embodiment of this application. Detailed Implementation

[0022] The technical solutions in the embodiments (or "implementations") of this application will be clearly and completely described herein with reference to the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements.

[0023] If the embodiments of this application contain terms relating to directional indications or positional relationships (such as up, down, left, right, front, back, inside, outside, top, bottom, center, vertical, horizontal, longitudinal, transverse, length, width, counterclockwise, clockwise, axial, radial, circumferential, etc.), such terms are only used to explain the relative positional relationships and movements between components in a specific posture (as shown in the attached figures); if the specific posture changes, the directional indications or positional relationships will also change accordingly. Furthermore, the terms "first" and "second" used in the embodiments of this application are only for descriptive convenience and should not be construed as indicating or implying relative importance.

[0024] In chip manufacturing, photolithography is used to transfer patterns from a photomask onto the chip, thus realizing the circuit patterning of the chip. The size of the photomask is limited by the manufacturing process.

[0025] As a chip integrates more modules, each module requires a certain area of ​​space, thus increasing the chip area. Since the size of the photomask determines the area exposed in a single exposure, when the chip area exceeds the single exposure area of ​​the photomask, multiple exposures are needed to create the circuit pattern. During chip manufacturing, each photolithography process may introduce deviations, and multiple photolithography processes can lead to error accumulation, severely affecting the accuracy of the chip's circuit pattern, thereby reducing chip performance or even causing chip malfunction.

[0026] The chip packaging structure and electronic device of the present application embodiments are described in detail below with reference to the accompanying drawings. Unless otherwise specified, the features of the following embodiments and implementation methods can complement or combine with each other.

[0027] This application provides a chip packaging structure, such as... Figure 1As shown, the chip packaging structure includes a data processing chip 10, a storage chip 20, and an auxiliary chip 30.

[0028] The data processing chip 10 receives and processes data. The storage chip 20 is electrically connected to the data processing chip 10. The data processing chip 10 can read data from the storage chip 20, and data generated during data processing can also be written to the storage chip 20. The auxiliary chip 30 includes a capacitor 31, which is electrically connected to the data processing chip 10. The capacitor 31 filters and decouples the input signal, providing a stable, low-noise signal to the data processing chip 10.

[0029] The chip packaging structure provided in this application embodiment has a separate data processing chip 10 and a storage chip 20. Compared to a solution that integrates data processing and storage functions into a single chip, this reduces the size of a single chip and avoids performance degradation during manufacturing due to excessive chip size. Furthermore, the data processing chip 10 and the storage chip 20 can employ different process technologies. For example, the data processing chip 10 can use a more advanced process to improve its processing power, while the storage chip 20 can use a more mature process node, thereby reducing the manufacturing cost of the chip packaging structure. By including an auxiliary chip 30 with a capacitor 31 in the chip packaging structure, the number of capacitor components on the circuit board connected to the chip packaging structure can be reduced.

[0030] In one embodiment, the data processing chip 10 includes at least one of a logic chip and a system-on-a-chip (SoC). The logic chip can perform logical operations, while the SoC can perform complex operations and system control, thus achieving a balance between the functionality and integration of the data processing chip 10.

[0031] In one embodiment, the data processing chip 10 includes a plurality of processors 11, including but not limited to a central processing unit, a graphics processing unit, etc.

[0032] In one embodiment, the memory chip 20 includes a static storage module for temporarily storing data required by the processor. The memory chip 20 may also include modules such as an input module and an output module. The memory module can be electrically connected to the data processing chip 10 through the input module and the output module, thereby enabling data to be transferred between the memory module and the processor.

[0033] In one embodiment, the capacitor 31 in the auxiliary chip 30 is a deep trench capacitor 31. Compared with ordinary capacitors, deep trench capacitors 31 have a higher capacitance density, which can more effectively filter out noise in the signal and improve the quality of the signal input to the data processing chip 10.

[0034] In one embodiment, the depth of the deep trench capacitor 31 is less than the thickness of the auxiliary chip 30. The thickness of the auxiliary chip 30 can range from 10 μm to 50 μm, and the depth of the deep trench capacitor 31 can range from 1 μm to 10 μm. The capacitance density of the deep trench capacitor 31 can range from 1 μF / mm². 2 ~10μF / mm 2 .

[0035] In one embodiment, such as Figure 1 As shown, the auxiliary chip 30 has multiple trenches, and the deep trench capacitor 31 includes a first conductive layer 311, a dielectric layer 312 and a second conductive layer 313 located in the trench. The first conductive layer 311 is disposed on the inner surface of the trench, and the dielectric layer 312 covers the first conductive layer 311 and isolates the first conductive layer 311 from the second conductive layer 313.

[0036] In one embodiment, the auxiliary chip 30 is provided with at least one capacitor bank, which includes a plurality of deep trench capacitors 31 arranged at intervals. Figure 1 As shown, the first conductive layers 311 of multiple capacitors 31 in the same capacitor group 31 are connected, and the second conductive layers 313 are connected.

[0037] In one embodiment, each processor 11 and a capacitor bank are opposite each other in the stacking direction of the auxiliary chip 30 and the memory chip 20, and the processor 11 is electrically connected to the capacitor 31 of the opposite capacitor bank. This configuration results in shorter traces between the processor 11 and the opposite capacitor bank, effectively reducing signal transmission losses, significantly improving signal transmission efficiency, and simplifying chip layout design, making the internal structure of the chip more regular and compact.

[0038] In one embodiment, such as Figure 1 As shown, the data processing chip 10, the storage chip 20, and the auxiliary chip 30 are stacked. Stacking the chips not only shortens the distance between them, reducing signal transmission delay, but also reduces the area occupied by the chip packaging structure.

[0039] In one embodiment, such as Figure 1 As shown, the storage chip 20 is located between the data processing chip 10 and the auxiliary chip 30, and the data storage chip 20 is bonded to both the processing chip and the auxiliary chip 30. The data processing chip 10 generates a large amount of heat during operation. Placing the data processing chip 10 on the outermost side improves the heat dissipation performance of the chip package structure and prevents localized overheating.

[0040] In one embodiment, such as Figure 1As shown, the chip package structure also includes multiple conductive structures 40 located on the side of the auxiliary chip 30 away from the memory chip 20. Each conductive structure 40 is electrically connected to the data processing chip 10, and at least one conductive structure 40 is electrically connected to the capacitor 31. The conductive structure 40 is the structure of the chip package structure used to connect to an external circuit board. By placing the conductive structure 40 on the side of the auxiliary chip 30 away from the memory chip 20, the connection routing between the conductive structure 40 and the capacitor 31 is relatively simple. Compared to placing the conductive structure 40 on the side of the data processing chip 10 away from the memory chip 20, redundant routing can be reduced, and the internal routing complexity of the chip package structure can be reduced.

[0041] In one embodiment, such as Figure 1 As shown, the conductive structure 40 includes a first type of conductive structure 41 and a second type of conductive structure 42. The first type of conductive structure 41 is electrically connected to the capacitor 31, while the second type of conductive structure 42 is not electrically connected to the capacitor 31. The first type of conductive structure 41 can be used to input power signals. After the power signals are filtered and decoupled by the capacitor 31, they are transmitted to the data processing chip 10. The second type of conductive structure 42 can be used to transmit data signals.

[0042] In one embodiment, the conductive structure 40 includes metal bumps and solder located on the side of the metal bumps away from the auxiliary chip 30. The chip package structure can be soldered to a circuit board using solder. The metal bumps can be made of copper, and the solder can be solder paste.

[0043] In one embodiment, the active surface of the data processing chip 10 faces the memory chip 20, and the active surface of the memory chip 20 faces the data processing chip 10. The fact that the active surfaces of the data processing chip 10 and the memory chip 20 are positioned opposite each other simplifies the wiring structure between them and reduces signal transmission delay.

[0044] In one embodiment, such as Figure 1 As shown, the chip package structure also includes a first redistribution structure 50 located between the data processing chip 10 and the memory chip 20. The active surface of the data processing chip 10 is electrically connected to the active surface of the memory chip 20 through the first redistribution structure 50, and the memory chip 20 and the data processing chip 10 are bonded through the first redistribution structure 50.

[0045] Specifically, the first redistribution structure 50 includes a first redistribution layer 51, a plurality of first metal pillars 53 located on the side of the first redistribution layer 51 facing the memory chip 20, and a second redistribution layer 52 located between the first metal pillars 53 and the memory chip 20. The first redistribution layer 51 includes a plurality of first traces 511, and the second redistribution layer 52 includes a plurality of second traces 521. Each first trace 511 is connected to the active surface of the data processing chip 10 and the first metal pillars 53, and each second trace 521 is connected to the first metal pillars 53. Some of the second traces 521 are connected to the active surface of the data processing chip 10. A plurality of first metal pillars 53 are respectively provided between each first trace 511 and the corresponding second trace 521, that is, each first trace 511 is electrically connected to the second trace 521 through the first metal pillars 53. In this way, the data processing chip 10 is electrically connected to the memory chip 20 through the first traces 511, the first metal pillars 53, and the second traces 521 in sequence. At least one second trace 521 is not connected to the active surface of the memory chip 20, and this portion of the second trace 521 is used for electrical connection to the capacitor 31.

[0046] In one embodiment, the first metal post 53 is formed by bonding two metal protrusions together, thereby bonding the data processing chip 10 and the memory chip 20 together.

[0047] In one embodiment, the chip package structure further includes a first insulating layer 54 located between the first redistribution layer 51 and the second redistribution layer 52, with a first metal pillar 53 penetrating through the first insulating layer 54. The first insulating layer 54 may be formed by bonding two insulating film layers together, thereby bonding the data processing chip 10 and the memory chip 20 together.

[0048] In one embodiment, such as Figure 1As shown, the chip packaging structure also includes a first conductive post 61 penetrating the memory chip 20, a second conductive post 62 penetrating the auxiliary chip 30, and a second redistribution structure 70 located between the auxiliary chip 30 and the memory chip 20. The second redistribution structure 70 includes a third redistribution layer 71, a plurality of second metal posts 73 located on the side of the third redistribution layer 71 facing the auxiliary chip 30, and a fourth redistribution layer 72 located between the second metal posts 73 and the auxiliary chip 30. The third redistribution layer 71 includes a plurality of third traces 711, and the fourth redistribution layer 72 includes a plurality of fourth traces 721. Each first conductive post 61 is electrically connected to the data processing chip 10. Specifically, each first conductive post 61 is electrically connected to the second trace 521, and sequentially connected to the active surface of the data processing chip 10 through the second trace 521, the first metal post 53, and the first trace 511. Each third trace 711 is connected to the first conductive post 61 and the second metal post 73, respectively. Each fourth trace 721 is connected to the second metal post 73 and the second conductive post 62, respectively. At least one fourth trace 721 is electrically connected to the capacitor 31. Multiple second metal posts 73 are provided between each third trace 711 and the corresponding fourth trace 721, meaning each third trace 711 is electrically connected to the fourth trace 721 through a second metal post 73. The fourth trace 721 connected to the first type of conductive structure 41 is electrically connected to the capacitor 31, while the fourth trace 721 connected to the second type of conductive structure 42 is not electrically connected to the capacitor 31. Thus, the first type of conductive structure 41 is electrically connected to the data processing chip 10 in sequence through the second conductive post 62, the fourth trace 721, the capacitor 31, the second metal post 73, the third trace 711, the first conductive post 61, and the first redistribution structure 50. The second type of conductive structure 42 is electrically connected to the data processing chip 10 in sequence through the second conductive post 62, the fourth trace 721, the second metal post 73, the third trace 711, the first conductive post 61, and the first redistribution structure 50.

[0049] In one embodiment, the second metal post 73 is formed by bonding two metal protrusions together, thereby bonding the auxiliary chip 30 to the memory chip 20.

[0050] In one embodiment, the chip package structure further includes a second insulating layer 74 located between the third redistribution layer 71 and the fourth redistribution layer 72, with the second metal pillar 73 penetrating through the second insulating layer 74. The second insulating layer 74 may be formed by bonding two insulating film layers together, thereby bonding the auxiliary chip 30 and the memory chip 20 together.

[0051] In one embodiment, the first conductive post 61 can be formed by filling a through-hole through the memory chip 20 with conductive material, and the second conductive post 62 can be formed by filling a through-hole through the auxiliary chip 30 with conductive material.

[0052] The signal transmission process of the chip packaging structure in this application is as follows: the power signal is input to the auxiliary chip 30 through the first type of conductive structure 41, passes through the second conductive pillar 62 and reaches the fourth redistribution layer 72, and is transmitted to the capacitor 31 through the fourth trace 721 for filtering and decoupling. Then the power signal is transmitted to the third redistribution layer 71 through the second metal pillar 73, and then sequentially passes through the first conductive pillar 61, the second redistribution layer 52 and the first redistribution layer 51 to the data processing chip 10; other data signals are sequentially transmitted to the data processing chip 10 through the second type of conductive structure 42, the second conductive pillar 62, the fourth redistribution layer 72, the third redistribution layer 71, the first conductive pillar 61, the second redistribution layer 52 and the first redistribution layer 51.

[0053] The intermediate signal output by the data processing chip 10 can be output to the memory chip 20 through the first rewiring structure 50, or the data stored in the memory chip 20 can be read through the first rewiring structure 50. The signal output by the data processing chip 10 can pass through the first rewiring structure 50, the first conductive post 61, the second rewiring structure 70 and the second conductive post 62 in sequence, and then be output through the corresponding second type of conductive structure 42.

[0054] This application also provides an electronic device, which includes the chip packaging structure described above. The electronic device further includes a circuit board, and the conductive structure of the chip packaging structure is soldered to the circuit board.

[0055] In one embodiment, the electronic device may be a computer, mobile phone, wearable display device, e-book, or other similar product.

[0056] It should be noted that the technical solutions or features described in the above embodiments can be combined or supplemented with each other without conflict. The scope of protection of this application is not limited to the precise structures described in the above embodiments and shown in the accompanying drawings; all modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A chip packaging structure, characterized in that, The chip packaging structure includes: Data processing chip; A storage chip, electrically connected to the data processing chip; An auxiliary chip is provided with a capacitor, which is electrically connected to the data processing chip.

2. The chip packaging structure according to claim 1, characterized in that, The data processing chip, the storage chip, and the auxiliary chip are stacked together.

3. The chip packaging structure according to claim 2, characterized in that, The storage chip is located between the data processing chip and the auxiliary chip, and the storage chip is bonded to both the processing chip and the auxiliary chip.

4. The chip packaging structure according to claim 3, characterized in that, The chip packaging structure also includes a plurality of conductive structures located on the side of the auxiliary chip away from the memory chip; each of the conductive structures is electrically connected to the data processing chip, and at least one of the conductive structures is electrically connected to the capacitor.

5. The chip packaging structure according to any one of claims 1 to 4, characterized in that, The capacitor is a deep-groove capacitor.

6. The chip packaging structure according to claim 5, characterized in that, The data processing chip includes a processor; the auxiliary chip is provided with at least one capacitor bank, the capacitor bank including a plurality of deep trench capacitors arranged at intervals; each processor and one of the capacitor banks are opposite to each other in the stacking direction of the processing chip and the memory chip, and the processor is electrically connected to the capacitors of the opposite capacitor bank.

7. The chip packaging structure according to claim 3, characterized in that, The active surface of the data processing chip faces the memory chip, and the active surface of the memory chip faces the data processing chip. The chip packaging structure further includes a first redistribution structure located between the data processing chip and the memory chip. The first redistribution structure includes a first redistribution layer, a plurality of first metal pillars located on the side of the first redistribution layer facing the memory chip, and a second redistribution layer located between the first metal pillars and the memory chip. The first redistribution layer includes a plurality of first traces, and the second redistribution layer includes a plurality of second traces. Each first trace is connected to the active surface of the data processing chip and the first metal pillar, and each second trace is connected to the first metal pillar. Some of the second traces are connected to the active surface of the memory chip.

8. The chip packaging structure according to claim 3, characterized in that, The chip packaging structure further includes a first conductive pillar penetrating the memory chip, a second conductive pillar penetrating the auxiliary chip, and a second rewiring structure located between the auxiliary chip and the memory chip; the second rewiring structure includes a third rewiring layer, a plurality of second metal pillars located on the side of the third rewiring layer facing the auxiliary chip, and a fourth rewiring layer located between the second metal pillars and the auxiliary chip; the third rewiring layer includes a plurality of third traces, and the fourth rewiring layer includes a plurality of fourth traces; the first conductive pillar is electrically connected to the data processing chip, and each of the third traces is respectively connected to the first conductive pillar and the second metal pillar; each of the fourth traces is respectively connected to the second conductive pillar, and some of the fourth traces are connected to the second metal pillar; at least one of the fourth traces is electrically connected to the capacitor.

9. The chip packaging structure according to claim 1, characterized in that, The data processing chip includes at least one of a logic chip and a system-on-a-chip.

10. An electronic device, characterized in that, The electronic device includes the chip packaging structure according to any one of claims 1 to 9.

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