A circuit for use in optical storage

Abstract

The utility model belongs to the field of light storage technology discloses a kind of circuit for light storage, including port BUS+, the one end of capacitor C386 connected to port BUS+, the one end of capacitor C385, the negative end of diode D11 and the one end of inductor L12, the positive end of diode D11 is connected to the negative end of diode D10, the positive end of diode D10 is connected to the one end of inductor L13 and the one end of capacitor C208, the other end of capacitor C208 is connected to the one end of capacitor C209, the other end of capacitor C209 is connected to the pin 1 of switch tube Q47, the other end of inductor L12 and the one end of capacitor C1.The utility model has the beneficial effect that: the reliability of power supply is higher, the probability of failure is lower, loop response is faster, output voltage control range is wider, applicable to wide input, wide output voltage range power supply scene.

Description

Technical Field

[0001] This utility model relates to the field of optical energy storage technology, and in particular to a circuit used in optical energy storage. Background Technology

[0002] Photovoltaic energy storage, also known as solar-to-battery energy storage, consists of Boost / Buck units, DC / DC units, control units, communication units, and other components. It is professionally applied in solar power systems, home appliance energy storage systems, and mobile energy storage for consumer use. It can operate independently or interact with AC sources (grid, generators, etc.). Increasingly, photovoltaic energy storage systems are gaining popularity among consumers and are finding widespread application in the field of green carbon neutrality.

[0003] Traditional DC-DC converters use an LLC resonant circuit to step down the voltage before charging the battery. The advantages of this circuit are high overall efficiency, good temperature rise control, low component stress, and good EMI performance. The disadvantage is that because the output is controlled by frequency modulation (PWF), the overall range is limited by the input and output voltage range, resulting in a narrow adjustment range and making it difficult to achieve a wide output range.

[0004] Therefore, it is necessary to provide a circuit for optical storage that has a faster loop response, a wider output voltage control range, and is suitable for power supply scenarios with a wide input and output voltage range. Utility Model Content

[0005] This utility model discloses a circuit for optical storage, which can effectively solve the technical problems involved in the background art.

[0006] To achieve the above objectives, the technical solution of this utility model is as follows:

[0007] A circuit for use in optical storage includes a port BUS+, which is connected to one end of capacitor C386, one end of capacitor C385, the negative terminal of diode D11, and one end of inductor L12. The positive terminal of diode D11 is connected to the negative terminal of diode D10. The positive terminal of diode D10 is connected to one end of inductor L13 and one end of capacitor C208. The other end of capacitor C208 is connected to one end of capacitor C209. The other end of capacitor C209 is connected to pin 1 of switching transistor Q47, the other end of inductor L12, and one end of capacitor C1. The other end of capacitor C1 is connected to pin 2 of transformer TX2. The inductor L13... The other end is connected to the negative terminal of diode D51. The positive terminal of diode D51 is connected to the negative terminal of diode D55. The positive terminal of diode D55 is connected to port BUS-, the other end of capacitor C386, the other end of capacitor C385, pin 2 of switch Q47, and pin 1 of transformer TX2. Pin 4 of switch Q47 is connected to one end of capacitor C104, one end of resistor R449, and port DRV.SP. The other end of capacitor C104 is connected to one end of resistor R1. Pin 3 of switch Q47 is connected to the other end of resistor R1, the other end of resistor R449, and port BUS-.

[0008] Pin 3 of transformer TX2 is connected to the negative terminal of diode D60, one end of capacitor C33, one end of capacitor C16, one end of capacitor C382, and port BAT+. The positive terminal of diode D60 is connected to one end of capacitor C205 and the negative terminal of diode D62. The positive terminal of diode D62 is connected to one end of inductor L6. The other end of inductor L6 is connected to port AGND. Pin 4 of transformer TX2 is connected to the other end of capacitor C205. The other end of capacitor C33 is connected to the other end of capacitor C16, the other end of capacitor C382, port AGND, and pin 1 of sampling resistor R44. Pin 4 of sampling resistor R44 is connected to port BAT-. Pin 2 of sampling resistor R44 is connected to one end of resistor R24. The other end of resistor R24 ​​is connected to port I.BAT-. Pin 3 of sampling resistor R44 is connected to one end of resistor R23. The other end of resistor R23 is connected to port I.BAT+.

[0009] The other end of capacitor C205 is connected to one end of capacitor C181, the drain of MOSFET Q131, one end of capacitor C163, the drain of MOSFET Q116, one end of capacitor C162, the drain of MOSFET Q112, one end of capacitor C160, and the drain of MOSFET Q113. The gate of MOSFET Q131 is connected to one end of resistor R461 and one end of resistor R460. The other end of resistor R461 is connected to one end of resistor R459 and port DRV1.SP. The other end of resistor R459 is connected to the gate of MOSFET Q116 and one end of resistor R162. The gate of MOSFET Q112 is connected to one end of resistor R457 and one end of resistor R456. The other end of resistor R457 is connected to one end of resistor R455 and port DR. V2.SP, the other end of resistor R455 is connected to the gate of MOSFET Q113 and one end of resistor R454, the other end of capacitor C181 is connected to the source of MOSFET Q131, the other end of resistor R460, the other end of capacitor C163, the source of MOSFET Q116, the other end of resistor R458, the other end of capacitor C162, the source of MOSFET Q112, the other end of resistor R456, the other end of capacitor C160, the source of MOSFET Q113, the other end of resistor R454, port AGND and one end of capacitor CY14, the other end of capacitor CY14 is connected to one end of capacitor CY26, and the other end of capacitor CY26 is connected to pin 1 of transformer TX2.

[0010] As a preferred improvement of this utility model: one end of capacitor C1 is connected to one end of capacitor C183, and the other end of capacitor C1 is connected to the other end of capacitor C183.

[0011] As a preferred improvement of this utility model: pin 1 of the switching transistor Q47 is connected to the negative terminal of diode D61, and pin 2 of the switching transistor Q47 is connected to the positive terminal of diode D61.

[0012] As a preferred improvement of this utility model: the port BAT+ is connected to one end of the fuse F2, the other end of the fuse F2 is connected to one end of the capacitor C286, the other end of the capacitor C286 is connected to one end of the port PE and one end of the port C287, and the other end of the capacitor C287 is connected to the port BAT-.

[0013] As a preferred improvement of this utility model: one end of the capacitor C286 is connected to the socket interface CON3, and the other end of the capacitor C287 is connected to the socket interface CON2.

[0014] As a preferred improvement of this utility model: the ports DRV.SP, DRV1.SP, DRV2.SP, I.BAT-, and I.BAT+ are connected to the MCU.

[0015] As a preferred improvement of this utility model, the port AGND and the port PE are connected to different grounding terminals.

[0016] The beneficial effects of this utility model are as follows:

[0017] A SEPIC circuit is disclosed. Compared with the traditional circuit structure, the SEPIC circuit is simpler in structure and avoids the risk of common contact between the upper and lower transistors. The power supply is more reliable and has a lower probability of failure. In addition, it adopts a PWM control loop, which has a faster loop response and a wider output voltage control range, making it suitable for power supply scenarios with a wide input and output voltage range. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein:

[0019] Figure 1 This is a schematic diagram of the photovoltaic energy storage principle;

[0020] Figure 2 This is a schematic diagram of the BOOST circuit.

[0021] Figure 3 This is a schematic diagram of an LLC circuit structure;

[0022] Figure 4 This is a schematic diagram of a circuit used in optical storage according to the present invention;

[0023] Figure 5 for Figure 4 Enlarged schematic diagram of the structural connection at Q112;

[0024] Figure 6 for Figure 4 Enlarged illustration Figure 1 ;

[0025] Figure 7 for Figure 4 Enlarged illustration Figure 2 . Detailed Implementation

[0026] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0027] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indication will also change accordingly.

[0028] Furthermore, in this invention, descriptions involving "first," "second," etc., are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0029] In this invention, unless otherwise explicitly specified and limited, the terms "connection," "fixed," etc., should be interpreted broadly. For example, "fixed" can mean a fixed connection, a detachable connection, or an integral part; it can mean a mechanical connection or an electrical connection; it can mean a direct connection or an indirect connection through an intermediate medium; it can mean the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0030] Furthermore, the technical solutions of the various embodiments of the present invention can be combined with each other, but only if they are feasible for those skilled in the art. If the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the scope of protection claimed by the present invention.

[0031] Please see Figure 1 As shown, the DC-DC converter receives input from the solar panel (70-500V), and after passing through the Boost circuit, obtains a stable bus voltage of approximately 400V. This bus voltage is then converted to a DC-DC converter to provide a 20-30V DC voltage to charge the 24V battery. Currently, the commonly used standard battery rated voltages are 12V / 24V / 48V; this example uses a 24V battery. The energy storage battery charging process can be divided into several stages: trickle charging, equalization charging, and float charging. The solar charging diagram is roughly as follows: Figures 1-2 .

[0032] Traditional DC-DC converters use LLC resonant circuits to step down the voltage before charging the battery. The advantages of this circuit are high overall efficiency, good temperature rise, low component stress, and good EMI control. The disadvantage is that because the output is controlled by frequency modulation (PWF), the overall range is limited by the input and output voltage range, resulting in a narrow adjustment range and making it difficult to achieve a wide output range. Another disadvantage of LLC resonant circuits is that the high-voltage side is implemented using a half-bridge or full-bridge circuit, involving upper and lower transistors. Energy transfer on the secondary side is achieved by controlling the alternating conduction of these transistors. This makes control complex and carries the risk of transistor swarming. If swarming occurs, the entire circuit will burn out. Therefore, the reliability of LLC circuits is somewhat limited. The basic principle of an LLC circuit is as follows: Figure 3 As shown, MOSFETs Q7 and Q8 conduct alternately throughout the cycle, each accounting for 50%. They then resonate through inductor L5, capacitor C4, and transformer T1 to achieve soft switching, transferring energy to the secondary side via the transformer. To address the narrow output and frequency modulation ranges, a Sepic circuit is introduced in the DC-DC section. Unlike LLC circuits which use a power voltmeter (PWF) to control the output voltage, Sepic circuits use pulse-width modulation (PWM) to control the output voltage. PWM offers advantages over PWFs: a wider adjustment range, faster loop response, a wider output voltage range even with unstable input voltage, and lower output ripple.

[0033] Please see Figures 4-7As shown, this utility model provides a circuit (sepic circuit) for optical storage, including a port BUS+. Port BUS+ is connected to one end of capacitor C386, one end of capacitor C385, the negative terminal of diode D11, and one end of inductor L12. The positive terminal of diode D11 is connected to the negative terminal of diode D10. The positive terminal of diode D10 is connected to one end of inductor L13 and one end of capacitor C208. The other end of capacitor C208 is connected to one end of capacitor C209. The other end of capacitor C209 is connected to pin 1 of switching transistor Q47, the other end of inductor L12, and one end of capacitor C1. The other end of capacitor C1 is connected to pin 2 of transformer TX2. The other end of inductor L13 is connected to the negative terminal of diode D51, and the positive terminal of diode D51 is connected to the negative terminal of diode D55. The diode D55's positive terminal is connected to port BUS-, the other end of capacitor C386, the other end of capacitor C385, pin 2 of switch Q47, and pin 1 of transformer TX2. Switch Q47's pin 4 is connected to one end of capacitor C104, one end of resistor R449, and port DRV.SP. The other end of capacitor C104 is connected to one end of resistor R1. Switch Q47's pin 3 is connected to the other end of resistor R1, the other end of resistor R449, and port BUS-. One end of capacitor C1 is connected to one end of capacitor C183, and the other end of capacitor C1 is connected to the other end of capacitor C183. Switch Q47's pin 1 is connected to the negative terminal of diode D61, and switch Q47's pin 2 is connected to the positive terminal of diode D61.

[0034] Pin 3 of transformer TX2 is connected to the negative terminal of diode D60, one end of capacitor C33, one end of capacitor C16, one end of capacitor C382, and port BAT+. The positive terminal of diode D60 is connected to one end of capacitor C205 and the negative terminal of diode D62. The positive terminal of diode D62 is connected to one end of inductor L6. The other end of inductor L6 is connected to port AGND. Pin 4 of transformer TX2 is connected to the other end of capacitor C205. The other end of capacitor C33 is connected to the other end of capacitor C16, the other end of capacitor C382, port AGND, and pin 1 of sampling resistor R44. Pin 4 of sampling resistor R44 is connected to port BAT+. AT-, pin 2 of the sampling resistor R44 is connected to one end of resistor R24, and the other end of resistor R24 ​​is connected to port I.BAT-, pin 3 of the sampling resistor R44 is connected to one end of resistor R23, and the other end of resistor R23 is connected to port I.BAT+, port BAT+ is connected to one end of fuse F2, the other end of fuse F2 is connected to one end of capacitor C286, the other end of capacitor C286 is connected to port PE and one end of port C287, the other end of capacitor C287 is connected to port BAT-, one end of capacitor C286 is connected to socket interface CON3, and the other end of capacitor C287 is connected to socket interface CON2.

[0035] The other end of capacitor C205 is connected to one end of capacitor C181, the drain of MOSFET Q131, one end of capacitor C163, the drain of MOSFET Q116, one end of capacitor C162, the drain of MOSFET Q112, one end of capacitor C160, and the drain of MOSFET Q113. The gate of MOSFET Q131 is connected to one end of resistor R461 and one end of resistor R460. The other end of resistor R461 is connected to one end of resistor R459 and port DRV1.SP. The other end of resistor R459 is connected to the gate of MOSFET Q116 and one end of resistor R162. The gate of MOSFET Q112 is connected to one end of resistor R457 and one end of resistor R456. The other end of resistor R457 is connected to one end of resistor R455 and port DRV2.SP. The other end of resistor R455 is connected to the gate of MOSFET Q113 and one end of resistor R454. The other end of capacitor C181 is connected to the source of MOSFET Q131, the other end of resistor R460, the other end of capacitor C163, the source of MOSFET Q116, the other end of resistor R458, the other end of capacitor C162, the source of MOSFET Q112, the other end of resistor R456, the other end of capacitor C160, the source of MOSFET Q113, the other end of resistor R454, port AGND, and one end of capacitor CY14. The other end of capacitor CY14 is connected to one end of capacitor CY26. The other end of capacitor CY26 is connected to pin 1 of transformer TX2. Ports DRV.SP, DRV1.SP, DRV2.SP, I.BAT-, and I.BAT+ are connected to the MCU. Ports AGND and PE are connected to different ground terminals.

[0036] Circuit principle explanation:

[0037] The circuit is divided into two parts, isolated by transformers. The primary side is a Sepic circuit, and the secondary side is a rectifier circuit. The primary MOSFET Q47 and the secondary MOSFETs Q112 / Q113 / Q116 / Q131 conduct alternately, complementing each other within one cycle, similar to a flyback circuit. However, a significant advantage over a flyback circuit is that the primary side can perform buck-boost functions, offering wider and more flexible adjustment capabilities. Since both the primary and secondary sides use only a single transistor, reliability is improved, and there is no issue of mutual complementarity. Let the turns ratio of the transformer TX2 be n, the switching period be T, the duty cycle be D, the bus voltage be Vin, and the output voltage be Vo.

[0038] Let's start with the principle analysis from the primary edge:

[0039] Stage 1: When Q47 is turned on, inductor L12 begins to store energy, and capacitor C1 releases energy. The four MOSFETs on the secondary side are in the off state, and the load is powered by the output capacitor. Let the on-state voltage of inductor L12 be VLon, and the voltage of the primary transformer winding be VTon. Since the voltage across the DC blocking capacitor C1 cannot change abruptly whether it is turned on or off, assume that the voltage across C1 remains constant at Vc.

[0040] Stage 2: When Q47 is turned off, inductor L12 releases energy, capacitor C1 stores energy, transformer TX2 transfers energy to the secondary side, and the four MOSFETs on the secondary side are in the on state. Let the turn-off voltage of inductor L12 be VLoff, at this time the voltage of the primary transformer winding is nVo (Vo is the secondary output voltage), and C1 is still Vc.

[0041] Combining Phase 1 and Phase 2, we obtain the following formula:

[0042] Analysis of inductors using the volt-second law:

[0043] VL on *T on =VL off *T off Equation 1;

[0044] VL on =V in Equation 2;

[0045] VL off =nV o +V c -V in Equation 3;

[0046] T on =T*D,T off =T(1-D), Equation 4;

[0047] Analysis of transformers using the volt-second law:

[0048] V c *T*D=nV o *T(1-D), Equation 5;

[0049] Based on equations 1-5, after simplification, we obtain the following formula:

[0050]

[0051] Equation 6 yields a relationship between the output Vo and the input Vin. When D < 0.5, it can be understood as a buck state; when D > 0.5, it can be understood as a boost state; when D = 0.5, ... The output voltage is exactly equal to the input voltage divided by the transformer turns ratio; it neither steps down nor steps up the voltage.

[0052] Parameter settings

[0053] Assume the input voltage BUS+ is rated at 385V and has a maximum voltage of 400V; the output rated voltage is 24V, with a maximum value of 30V and an output power of 1000W; and the transformer turns ratio is 16:1. Then, with both input and output at their rated voltages, according to Equation 6, the duty cycle D is exactly 0.5.

[0054] 1) Since the maximum voltage of the solar panel may reach 500V, the input capacitor withstand voltage should be at least 500V. Here, C385 / C386 is set to 470uF / 500V.

[0055] 2) With D = 0.5, the primary-side switching transistor has Vds = Vc + nVo = 2Vin. Therefore, the rated voltage of Q47 (D61) is at least 1000V. To ensure sufficient margin, a 1200V silicon carbide MOSFET with a maximum current of 30A is selected. The DC blocking capacitors C1 / C183 should maintain the same withstand voltage as the input voltage; 630V CBB capacitors with a capacitance of 2.2uF are selected.

[0056] 3) To save costs, the BOOST inductor L12 can be made of iron-silicon material with an inductance of 1mH.

[0057] 4) Other components on the primary side are Q47 stress lossless absorption circuits, the purpose of which is to reduce the voltage stress of Q47.

[0058] 5) The platform voltage of the secondary-side MOSFETs Q112 / Q113 / Q116 / Q131 should be at least twice the output voltage, similar to a forward topology. Therefore, MOSFETs with a rated voltage of 100V are selected. To ensure sufficient current withstand capability to handle a 1000W load, four 200A TO-247 packaged MOSFETs are selected.

[0059] 6) Select 4700uF / 63V standard capacitors for output capacitors C16 / C33 / C382.

[0060] The secondary side D60 / D62 / L6 / C205 form a lossless absorption circuit to reduce the voltage stress on the secondary side rectifier MOSFET. D60 / D62 can be selected as 100V Schottky, C205 can be selected as 104 / 100V capacitance, and L6 can be selected as a small 2.2UH inductor.

[0061] Traditional solar energy storage designs employ LLC resonant modules and synchronous rectification modules. Compared to traditional circuit structures, this practical circuit is simpler in structure, avoiding the risk of common circuitry between the upper and lower transistors. The power supply reliability is higher, and the probability of failure is lower. Furthermore, the use of a PWM control loop results in faster loop response and a wider output voltage control range, making it suitable for power supply scenarios with wide input and output voltage ranges.

[0062] This circuit is relatively mature, highly reliable, and widely used in the market. It possesses all the functions of an inverter-charger and is suitable for yacht, vehicle-mounted, and land-based off-grid and grid-connected systems. Whether for photovoltaic energy storage, mobile energy storage, or home grid-connected energy storage, this power circuit can be applied, making its application range very wide. It has a broad market in areas with abundant solar energy, unstable grids, and high electricity costs. As a portable AC / DC energy storage and photovoltaic energy storage power source, it is also favored by outdoor enthusiasts and can be used to power coffee machines, ice makers, portable LED lights, and even refrigerators and air conditioners.

[0063] Although the embodiments of this utility model have been disclosed above, they are not limited to the applications listed in the specification and embodiments. They can be applied to various fields suitable for this utility model. For those skilled in the art, other modifications can be easily made. Therefore, without departing from the general concept defined by the claims and their equivalents, this utility model is not limited to the specific details and the illustrations shown and described herein.

Claims

1. A circuit for use in optical storage, characterized in that: The circuit includes port BUS+, which is connected to one end of capacitor C386, one end of capacitor C385, the negative terminal of diode D11, and one end of inductor L12. The positive terminal of diode D11 is connected to the negative terminal of diode D10. The positive terminal of diode D10 is connected to one end of inductor L13 and one end of capacitor C208. The other end of capacitor C208 is connected to one end of capacitor C209. The other end of capacitor C209 is connected to pin 1 of switching transistor Q47, the other end of inductor L12, and one end of capacitor C1. The other end of capacitor C1 is connected to pin 2 of transformer TX2. The other end of inductor L13 is connected to... Connect the negative terminal of diode D51 to the negative terminal of diode D55. Connect the positive terminal of diode D55 to port BUS-, the other end of capacitor C386, the other end of capacitor C385, pin 2 of switch Q47, and pin 1 of transformer TX2. Connect pin 4 of switch Q47 to one end of capacitor C104, one end of resistor R449, and port DRV.SP. Connect the other end of capacitor C104 to one end of resistor R1. Connect pin 3 of switch Q47 to the other end of resistor R1, the other end of resistor R449, and port BUS-. Pin 3 of transformer TX2 is connected to the negative terminal of diode D60, one end of capacitor C33, one end of capacitor C16, one end of capacitor C382, and port BAT+. The positive terminal of diode D60 is connected to one end of capacitor C205 and the negative terminal of diode D62. The positive terminal of diode D62 is connected to one end of inductor L6. The other end of inductor L6 is connected to port AGND. Pin 4 of transformer TX2 is connected to the other end of capacitor C205. The other end of capacitor C33 is connected to the other end of capacitor C16, the other end of capacitor C382, port AGND, and pin 1 of sampling resistor R44. Pin 4 of sampling resistor R44 is connected to port BAT-. Pin 2 of sampling resistor R44 is connected to one end of resistor R24. The other end of resistor R24 ​​is connected to port I.BAT-. Pin 3 of sampling resistor R44 is connected to one end of resistor R23. The other end of resistor R23 is connected to port I.BAT+. The other end of capacitor C205 is connected to one end of capacitor C181, the drain of MOSFET Q131, one end of capacitor C163, the drain of MOSFET Q116, one end of capacitor C162, the drain of MOSFET Q112, one end of capacitor C160, and the drain of MOSFET Q113. The gate of MOSFET Q131 is connected to one end of resistor R461 and one end of resistor R460. The other end of resistor R461 is connected to one end of resistor R459 and port DRV1.SP. The other end of resistor R459 is connected to the gate of MOSFET Q116 and one end of resistor R162. The gate of MOSFET Q112 is connected to one end of resistor R457 and one end of resistor R456. The other end of resistor R457 is connected to one end of resistor R455 and port DR. V2.SP, the other end of resistor R455 is connected to the gate of MOSFET Q113 and one end of resistor R454, the other end of capacitor C181 is connected to the source of MOSFET Q131, the other end of resistor R460, the other end of capacitor C163, the source of MOSFET Q116, the other end of resistor R458, the other end of capacitor C162, the source of MOSFET Q112, the other end of resistor R456, the other end of capacitor C160, the source of MOSFET Q113, the other end of resistor R454, port AGND and one end of capacitor CY14, the other end of capacitor CY14 is connected to one end of capacitor CY26, and the other end of capacitor CY26 is connected to pin 1 of transformer TX2.

2. The circuit for optical storage according to claim 1, characterized in that: One end of capacitor C1 is connected to one end of capacitor C183, and the other end of capacitor C1 is connected to the other end of capacitor C183.

3. The circuit for optical storage according to claim 1, characterized in that: Pin 1 of the switching transistor Q47 is connected to the negative terminal of diode D61, and pin 2 of the switching transistor Q47 is connected to the positive terminal of diode D61.

4. The circuit for optical storage according to claim 1, characterized in that: The port BAT+ is connected to one end of the fuse F2, the other end of the fuse F2 is connected to one end of the capacitor C286, the other end of the capacitor C286 is connected to one end of the port PE and one end of the port C287, and the other end of the capacitor C287 is connected to the port BAT-.

5. A circuit for optical storage according to claim 4, characterized in that: One end of capacitor C286 is connected to socket interface CON3, and the other end of capacitor C287 is connected to socket interface CON2.

6. A circuit for optical storage according to claim 1, characterized in that: The ports DRV.SP, DRV1.SP, DRV2.SP, I.BAT-, and I.BAT+ are connected to the MCU.

7. A circuit for optical storage according to claim 4, characterized in that: The AGND port and the PE port are connected to different grounding terminals.

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