Second pulse signal switching circuit

Abstract

The utility model discloses a kind of second pulse signal switching circuit, including first signal detection module, second signal detection module, monitoring reset module, first switching control module and second switching control module;Wherein, the output end of first signal detection module is connected with the input end of first switching control module, the output end of second signal detection module is connected with the input end of second switching control module and the input end of monitoring reset module respectively, the output end of monitoring reset module is connected with the controlled end of first switching control module and the controlled end of second switching control module respectively, monitoring reset module is configured as: when receiving the second pulse signal of the output end of second signal detection module, to the controlled end of second switching control module Output switching control signal, to make second switching control module output second pulse signal.The utility model can provide stable second pulse signal output by two-way switching, improve the reliability and stability of electronic equipment and communication system.

Description

Technical Field

[0001] This utility model relates to the field of time synchronization technology, and in particular to a second pulse signal switching circuit. Background Technology

[0002] In numerous high-precision time synchronization applications, such as aerospace, communication networks, power systems, and scientific research, there are stringent requirements for the accuracy and reliability of time synchronization. To meet this need, 1PPS (one pulse per second) signals are widely used as a high-precision time reference signal. However, a single 1PPS signal source often cannot ensure the continuous and stable operation of the system, especially in complex and changing working environments. The signal source may malfunction or be subject to interference, leading to interruptions or inaccuracies in time synchronization.

[0003] Existing signal source switching circuits have a slow response speed, making it difficult to react quickly when the signal source malfunctions or malfunctions. This results in the system being unable to receive an accurate 1PPS signal for an extended period, thus affecting the timeliness of time synchronization. Secondly, the unevenness of the switching process can cause instantaneous jumps in system time and may also exacerbate clock jitter within the system, affecting the normal operation of other devices that rely on precise time synchronization. Utility Model Content

[0004] The purpose of this invention is to solve at least one of the technical problems existing in the prior art, and to provide a second pulse signal switching circuit that can not only detect low voltage second pulse signal input and narrow duty cycle second pulse signal, but also provide a stable second pulse signal output through dual-channel switching, thereby improving the reliability and stability of electronic equipment and communication systems.

[0005] The second pulse signal switching circuit according to an embodiment of the present invention includes a first signal detection module, a second signal detection module, a monitoring and reset module, a first switching control module, and a second switching control module. The output terminal of the first signal detection module is connected to the input terminal of the first switching control module. The output terminal of the second signal detection module is connected to both the input terminal of the second switching control module and the input terminal of the monitoring and reset module. The output terminal of the monitoring and reset module is connected to both the controlled terminal of the first switching control module and the controlled terminal of the second switching control module. The monitoring and reset module is configured to: upon receiving a second pulse signal from the output terminal of the second signal detection module, output a switching control signal to the controlled terminal of the second switching control module, so that the second switching control module outputs the second pulse signal.

[0006] The second pulse signal switching circuit provided according to the embodiments of this utility model has at least the following beneficial effects: the first signal detection module detects one second pulse signal and outputs it to the first switching control module, and the second signal detection module detects another second pulse signal and outputs it to the second switching control module and the monitoring and reset module. The monitoring and reset module controls the first switching module to output the first second pulse signal by default. When the monitoring and reset module receives the second pulse signal from the second signal detection module, it sends a switching control signal to the second switching control module to switch to output the second pulse signal from the second signal detection module. This not only enables the detection of low-voltage second pulse signal input and narrow duty cycle second pulse signal, but also provides a stable second pulse signal output through dual-channel switching, ensuring the time synchronization accuracy of electronic equipment and communication systems, and improving the reliability and stability of the system.

[0007] According to some embodiments of the present invention, it further includes a first second pulse signal input terminal and a second second pulse signal input terminal, wherein the input terminal of the first signal detection module is connected to the first second pulse signal input terminal, and the input terminal of the second signal detection module is connected to the second second pulse signal input terminal.

[0008] According to some embodiments of the present invention, a second pulse signal output terminal is also included, which is connected to the output terminal of the first switching control module and the output terminal of the second switching control module respectively.

[0009] According to some embodiments of this utility model, the first signal detection module includes resistors R1, R2, R3, R4, R5, R6, R7, and R8, a capacitor C1, transistors Q1 and Q2, and a chip U1. The base of transistor Q1 is connected to one end of resistor R1 and one end of resistor R2, respectively. The collector of transistor Q1 is connected to one end of resistor R3, one end of resistor R4, and one end of resistor R5, respectively. The other end of resistor R4 is connected to the base of transistor Q2, and the collector of transistor Q2 is connected to... One end of resistor R6 is connected to one end of resistor R7, the other end of resistor R7 is connected to one end of resistor R8, the other end of resistor R5 is connected to pin 2 of chip U1, the other end of resistor R8 is connected to pin 4 of chip U1, the other end of resistor R3, the other end of resistor R6, one end of capacitor C1, and pin 5 of chip U1 are respectively connected to the power supply voltage terminal VCC, and the other end of resistor R2, the emitter of transistor Q1, the emitter of transistor Q2, the other end of capacitor C1, and pin 3 of chip U1 are respectively grounded.

[0010] According to some embodiments of the present invention, the first switching control module includes a resistor R9, a capacitor C2 and a chip U2. Pin 2 of the chip U2 is connected to the connection point of the resistor R7 and the resistor R8. One end of the resistor R9 is connected to pin 4 of the chip U2. One end of the capacitor C2 and pin 5 of the chip U2 are connected to the power supply voltage terminal VCC. The other end of the capacitor C2 and pin 3 of the chip U2 are respectively grounded.

[0011] According to some embodiments of this utility model, the second signal detection module includes resistors R10, R11, R12, R13, R14, R15, R16, and R17, a capacitor C3, transistors Q3 and Q4, and a chip U3. The base of transistor Q3 is connected to one end of resistor R10 and one end of resistor R11, respectively. The collector of transistor Q3 is connected to one end of resistor R12, one end of resistor R13, and one end of resistor R14, respectively. The other end of resistor R13 is connected to the base of transistor Q4, and the collector of transistor Q4 is connected to... One end of resistor R15 and one end of resistor R16 are connected to each other. The other end of resistor R16 is connected to one end of resistor R17. The other end of resistor R14 is connected to pin 2 of chip U3. The other end of resistor R17 is connected to pin 4 of chip U3. The other end of resistor R12, the other end of resistor R15, one end of capacitor C3, and pin 5 of chip U3 are respectively connected to the power supply voltage terminal VCC. The other end of resistor R11, the emitter of transistor Q3, the emitter of transistor Q4, the other end of capacitor C3, and pin 3 of chip U3 are respectively grounded.

[0012] According to some embodiments of this utility model, the second switching control module includes resistors R18, R19, R20, and R21, capacitor C4, transistor Q5, and chip U4. One end of resistor R18 is connected to one end of resistor R19, and the other end of resistor R19 is connected to the base of transistor Q5. The collector of transistor Q5 is connected to one end of resistor R20 and pin 1 of chip U4, respectively. Pin 2 of chip U4 is connected to the connection point of resistors R16 and R17. One end of resistor R21 is connected to pin 4 of chip U4. One end of capacitor C4 and pin 5 of chip U4 are connected to the power supply voltage terminal VCC. The other end of capacitor C4, the emitter of transistor Q5, and pin 3 of chip U4 are grounded.

[0013] According to some embodiments of this utility model, the monitoring reset module includes a resistor R22, a capacitor C5, and a chip U5. One end of the resistor R22 is connected to pin 4 of the chip U5. One end of the capacitor C5 and pin 2 of the chip U5 are connected to the power supply voltage terminal VCC. The other end of the resistor R22, the other end of the capacitor C5, and pin 3 of the chip U5 are respectively grounded. Pin 6 of the chip U5 is connected to the connection point of the resistor R16, the resistor R17, and pin 2 of the chip U4. Pin 8 of the chip U5 is connected to the connection point of the resistor R18 and the resistor R19, and pin 1 of the chip U2.

[0014] According to some embodiments of the present invention, the first second pulse signal input terminal includes an interface J1 and a resistor R23, and the second second pulse signal input terminal includes an interface J2 and a resistor R24. Pin 1 of the interface J1 is connected to the other end of the resistor R1 and one end of the resistor R23, respectively. Pin 1 of the interface J2 is connected to the other end of the resistor R10 and one end of the resistor R24, respectively. The other ends of the resistor R23 and the other ends of the resistor R24 ​​are respectively connected to ground.

[0015] According to some embodiments of the present invention, the second pulse signal output terminal includes an interface J3, and pin 1 of the interface J3 is connected to the other end of the resistor R9 and the other end of the resistor R21, respectively.

[0016] Other features and advantages of this invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of this invention can be realized and obtained by means of the structures particularly pointed out in the description and the drawings. Attached Figure Description

[0017] The accompanying drawings are provided to further understand the technical solution of this utility model and constitute a part of the specification. They are used together with the embodiments of this utility model to explain the technical solution of this utility model, and do not constitute a limitation on the technical solution of this utility model.

[0018] The present invention will be further described below with reference to the accompanying drawings and embodiments;

[0019] Figure 1 This is a functional block diagram of the second pulse signal switching circuit according to an embodiment of the present invention;

[0020] Figure 2 This is a circuit diagram of the second pulse signal switching circuit according to an embodiment of the present invention;

[0021] Figure 3This is a circuit diagram of a second pulse signal switching circuit according to another embodiment of the present invention;

[0022] Figure 4 This is a circuit diagram of the monitoring and reset module according to an embodiment of the present invention;

[0023] Figure 5 This is a circuit diagram of the second pulse signal output terminal in an embodiment of the present invention. Detailed Implementation

[0024] This section will describe in detail the specific embodiments of the present utility model. The preferred embodiments of the present utility model are shown in the accompanying drawings. The purpose of the drawings is to supplement the textual description with graphics, so that people can intuitively and vividly understand each technical feature and the overall technical solution of the present utility model, but they should not be construed as limiting the scope of protection of the present utility model.

[0025] In the description of this utility model, it should be understood that the directional descriptions, such as up, down, front, back, left, right, etc., indicate the directional or positional relationship based on the directional or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.

[0026] In the description of this utility model, "several" means one or more, "multiple" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. If "first" or "second" is used in the description, it is only for the purpose of distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0027] In the description of this utility model, unless otherwise explicitly defined, terms such as "setting," "installation," and "connection" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this utility model in conjunction with the specific content of the technical solution.

[0028] In numerous high-precision time synchronization applications, such as aerospace, communication networks, power systems, and scientific research, there are stringent requirements for the accuracy and reliability of time synchronization. To meet this need, 1PPS (one pulse per second) signals are widely used as a high-precision time reference signal. However, a single 1PPS signal source often cannot ensure the continuous and stable operation of the system, especially in complex and changing working environments. The signal source may malfunction or be subject to interference, leading to interruptions or inaccuracies in time synchronization.

[0029] Existing signal source switching circuits have a slow response speed, making it difficult to react quickly when the signal source malfunctions or malfunctions. This results in the system being unable to receive an accurate 1PPS signal for an extended period, thus affecting the timeliness of time synchronization. Secondly, the unevenness of the switching process can cause instantaneous jumps in system time and may also exacerbate clock jitter within the system, affecting the normal operation of other devices that rely on precise time synchronization.

[0030] Based on this, the present invention provides a second pulse signal switching circuit, which can not only detect low voltage second pulse signal input and narrow duty cycle second pulse signal, but also provide stable second pulse signal output through dual-channel switching, thereby improving the reliability and stability of electronic equipment and communication systems.

[0031] The embodiments of this utility model will be further described below with reference to the accompanying drawings.

[0032] See Figure 1 This utility model provides a second pulse signal switching circuit, including a first signal detection module, a second signal detection module, a monitoring and reset module, a first switching control module, and a second switching control module. The output terminal of the first signal detection module is connected to the input terminal of the first switching control module. The output terminal of the second signal detection module is connected to both the input terminal of the second switching control module and the input terminal of the monitoring and reset module. The output terminal of the monitoring and reset module is connected to the controlled terminals of both the first and second switching control modules. The monitoring and reset module is configured to: upon receiving a second pulse signal from the output terminal of the second signal detection module, output a switching control signal to the controlled terminal of the second switching control module, thereby causing the second switching control module to output a second pulse signal.

[0033] Under normal operating conditions, the first signal detection module and the second signal detection module simultaneously detect the validity of the second pulse signal, for example, detecting the voltage range and duty cycle of the input second pulse signal. In one embodiment, the voltage detection range of the first signal detection module and the second signal detection module may specifically include 1.7V-3.3V. In another embodiment, the lower limit of the duty cycle detection range of the first signal detection module and the second signal detection module may include 0.001%. It should be noted that the monitoring and reset module outputs a control signal to the controlled terminal of the first switching control module by default, causing the first switching control module to be in the working state and outputting the second pulse signal detected by the first signal detection module. Further, when the second signal detection module detects a valid second pulse signal, it transmits the signal to the second switching control module and the monitoring and reset module. The monitoring and reset module then uses the second pulse signal as a reference to output a switching control signal to the controlled terminal of the second switching control module. Further, after receiving the switching control signal, the second switching control module quickly switches to the working state and begins to output the second pulse signal detected by the second signal detection module. At the same time, the first switching control module stops outputting the first signal, so that when the main signal source has a problem or needs to be switched to the backup signal source, the system can quickly and smoothly switch to another signal source, select the appropriate second pulse signal and make a smooth transition.

[0034] According to the second pulse signal switching circuit provided by this utility model, a first signal detection module detects one second pulse signal and outputs it to a first switching control module, while a second signal detection module detects another second pulse signal and outputs it to a second switching control module and a monitoring and reset module. The monitoring and reset module controls the first switching module to output the first second pulse signal by default. When the monitoring and reset module receives the second pulse signal from the second signal detection module, it sends a switching control signal to the second switching control module, causing it to switch to output the second pulse signal from the second signal detection module. This circuit can not only detect low-voltage second pulse signal input and narrow duty cycle second pulse signals, but also provide a stable second pulse signal output through dual-channel switching, ensuring the time synchronization accuracy of electronic equipment and communication systems, and improving the reliability and stability of the system.

[0035] In some embodiments of the present invention, the second pulse signal switching circuit further includes a first second pulse signal input terminal and a second second pulse signal input terminal. The input terminal of the first signal detection module is connected to the first second pulse signal input terminal, and the input terminal of the second signal detection module is connected to the second second pulse signal input terminal. It should be noted that the first and second second pulse signal input terminals can be interfaces for receiving external second pulse signals. Each input terminal corresponds to an independent second pulse signal source, providing the circuit with the signal input to be processed and switched. Specifically, the first second pulse signal input terminal is connected to the input terminal of the first signal detection module to input the first second pulse signal into the first signal detection module, and the second second pulse signal input terminal is connected to the input terminal of the second signal detection module to input the second second pulse signal into the second signal detection module. This achieves simultaneous monitoring and rapid switching of the two second pulse signals, improving the accuracy of time synchronization and the stability of the system.

[0036] In some embodiments of the present invention, the second pulse signal switching circuit further includes a second pulse signal output terminal, which is connected to the output terminals of the first switching control module and the second switching control module, respectively. It is understood that the second pulse signal output terminal can be an interface for outputting the second pulse signal to subsequent circuits or external devices. By setting an independent second pulse signal output terminal, it is possible to flexibly switch between two second pulse signals and stably output the selected appropriate second pulse signal to subsequent circuits or external devices.

[0037] See Figure 1 and Figure 2 In the second pulse signal switching circuit provided in some embodiments of this utility model, the first signal detection module includes resistors R1, R2, R3, R4, R5, R6, R7, and R8, capacitor C1, transistors Q1 and Q2, and chip U1. The base of transistor Q1 is connected to one end of resistor R1 and one end of resistor R2, and the collector of transistor Q1 is connected to one end of resistor R3, one end of resistor R4, and one end of resistor R5. The other end of resistor R4 is connected to the base of transistor Q2. The collector of transistor Q2 is connected to one end of resistor R6 and one end of resistor R7, the other end of resistor R7 is connected to one end of resistor R8, the other end of resistor R5 is connected to pin 2 of chip U1, the other end of resistor R8 is connected to pin 4 of chip U1, the other end of resistor R3, the other end of resistor R6, one end of capacitor C1 and pin 5 of chip U1 are connected to the power supply voltage terminal VCC, the other end of resistor R2, the emitter of transistor Q1, the emitter of transistor Q2, the other end of capacitor C1 and pin 3 of chip U1 are grounded.

[0038] It should be noted that one second pulse signal is input to the circuit through the first second pulse signal input terminal of the corresponding first signal detection module. After current limiting by resistor R1, it is input to the base of transistor Q1. Transistors Q1 and Q2 are both ultra-high frequency NPN transistors. Their working principle is based on the conduction and cutoff characteristics of transistors to detect the input second pulse signal. When the input second pulse signal reaches the base of transistor Q1, if the signal amplitude is sufficient to turn on transistor Q1, it enters the conduction state, which is equivalent to forming a low-resistance path in the circuit, allowing the signal to pass through and be transmitted to subsequent circuits. Specifically, transistor Q1 amplifies the input second pulse signal using its high-gain characteristics. When the input signal is high, the base current turns on transistor Q1; when the input signal is low, transistor Q1 is cut off. Furthermore, due to the conduction and cutoff characteristics of transistors, the output signal at the collector of transistor Q1 presents a level opposite to that of the input signal, thereby achieving inversion of the second pulse signal. Furthermore, the second pulse signal output by transistor Q1 can be reversed again through two paths: one is through transistor Q2, and the other is through chip U1. Simultaneously, the signal is shaped to ensure signal integrity. Then, the reversed second pulse signal is output either through the collector of transistor Q2 connected to resistor R7, or through pin 4 (signal output pin) of chip U1 connected to resistor R8. It should be understood that for transistor Q2, when transistor Q1 outputs a high level, transistor Q2 is turned on and outputs a low level; when transistor Q1 outputs a low level, transistor Q2 is turned off and outputs a high level. In one embodiment, chip U1 can be a single-channel inverter, whose internal structure inverts the input second pulse signal. In another embodiment, pin 2 (signal input pin) of chip U1 can be selected via a jumper using resistor R4 or resistor R5, allowing flexible selection of the signal input path according to actual needs, improving the circuit's adaptability and configurability.

[0039] See Figure 1 and Figure 2 In the second pulse signal switching circuit provided in some embodiments of this utility model, the first switching control module includes a resistor R9, a capacitor C2 and a chip U2. Pin 2 of the chip U2 is connected to the connection point of resistors R7 and R8. One end of resistor R9 is connected to pin 4 of chip U2. One end of capacitor C2 and pin 5 of chip U2 are connected to the power supply voltage terminal VCC. The other end of capacitor C2 and pin 3 of chip U2 are respectively grounded.

[0040] It is understood that the first switching control module consists of resistor R9, capacitor C2, and chip U2, where chip U2 can be a single-channel tri-state control buffer. Specifically, pin 2 of chip U2 is connected to the junction of resistors R7 and R8 to receive the second pulse signal output by the first signal detection module. One end of resistor R9 is connected to pin 5 (signal output pin) of U2, and one end of capacitor C2 is connected to pin 5 (VCC pin) of chip U2 and the power supply voltage terminal VCC to provide power voltage for the first switching control module. Pin 3 (GND pin) of chip U2 and the other end of capacitor C2 are grounded together for filtering to ensure power supply stability. Furthermore, pin 1 of chip U2 serves as the controlled terminal of the first switching control module and is active low. Therefore, when pin 1 of chip U2 receives a low-level signal, chip U2 is activated, and the second pulse signal input at pin 1 of chip U2 is output from pin 4 of chip U2 after passing through chip U2. It should be understood that the buffer used in chip U2 can enhance the signal driving capability and ensure signal integrity. At the same time, chip U2 can effectively isolate the signal distortion that may occur during the switching process, ensuring the stability and reliability of the output second pulse signal.

[0041] See Figures 1 to 3 In some embodiments of the present invention, the second signal detection module includes resistors R10, R11, R12, R13, R14, R15, R16, and R17, capacitor C3, transistors Q3 and Q4, and chip U3. The base of transistor Q3 is connected to one end of resistor R10 and one end of resistor R11, and the collector of transistor Q3 is connected to one end of resistor R12, one end of resistor R13, and one end of resistor R14. The other end of resistor R13 is connected to the base of transistor Q4. The collector of transistor Q4 is connected to one end of resistor R15 and one end of resistor R16, the other end of resistor R16 is connected to one end of resistor R17, the other end of resistor R14 is connected to pin 2 of chip U3, the other end of resistor R17 is connected to pin 4 of chip U3, the other end of resistor R12, the other end of resistor R15, one end of capacitor C3 and pin 5 of chip U3 are connected to the power supply voltage terminal VCC, and the other end of resistor R11, the emitter of transistor Q3, the emitter of transistor Q4, the other end of capacitor C3 and pin 3 of chip U3 are grounded.

[0042] It should be noted that the other second pulse signal is connected to the circuit through the second second pulse signal input terminal of the corresponding second signal detection module. After current limiting by resistor R10, it is input to the base of transistor Q3. Transistors Q3 and Q4 are both ultra-high frequency NPN transistors. Their working principle is based on the conduction and cutoff characteristics of transistors to detect the input second pulse signal. When the input second pulse signal reaches the base of transistor Q3, if the signal amplitude is sufficient to turn on transistor Q3, it enters the conduction state, which is equivalent to forming a low-resistance path in the circuit, allowing the signal to pass through and be transmitted to the subsequent circuit. Specifically, transistor Q3 amplifies the input second pulse signal using its high-gain characteristics. When the input signal is high, the base current turns on transistor Q3; when the input signal is low, transistor Q3 is cut off. Furthermore, due to the conduction and cutoff characteristics of transistors, the output signal at the collector of transistor Q3 presents a level opposite to that of the input signal, thereby achieving inversion of the second pulse signal. Furthermore, the second pulse signal output by transistor Q3 can be reversed again through two paths: one is through transistor Q4, and the other is through chip U3. Simultaneously, the signal is shaped to ensure signal integrity. Then, the reversed second pulse signal is output through either the collector of transistor Q4 connected to resistor R16, or through pin 4 (signal output pin) of chip U3 connected to resistor R17. It should be understood that for transistor Q4, when transistor Q3 outputs a high level, transistor Q4 is turned on and outputs a low level; when transistor Q3 outputs a low level, transistor Q4 is turned off and outputs a high level. In one embodiment, chip U3 can be a single-channel inverter, whose internal structure inverts the input second pulse signal. In another embodiment, pin 2 (signal input pin) of chip U3 can be selected via a jumper using resistor R13 or resistor R14, allowing flexible selection of the signal input path according to actual needs, improving the circuit's adaptability and configurability.

[0043] See Figures 1 to 3 In the second pulse signal switching circuit provided in some embodiments of this utility model, the second switching control module includes resistors R18, R19, R20, and R21, capacitor C4, transistor Q5, and chip U4. One end of resistor R18 is connected to one end of resistor R19, and the other end of resistor R19 is connected to the base of transistor Q5. The collector of transistor Q5 is connected to one end of resistor R20 and pin 1 of chip U4, respectively. Pin 2 of chip U4 is connected to the connection point of resistors R16 and R17. One end of resistor R21 is connected to pin 4 of chip U4. One end of capacitor C4 and pin 5 of chip U4 are connected to the power supply voltage terminal VCC. The other end of capacitor C4, the emitter of transistor Q5, and pin 3 of chip U4 are grounded.

[0044] Understandably, the second switching control module consists of resistors R18, R19, R20, R21, capacitor C4, transistor Q5, and chip U4. Resistors R18 and R19 are connected in series and then connected to the circuit. The other end of R19 is connected to the base of transistor Q5 to control the base current. The collector of transistor Q5 is connected to resistor R20 and pin 1 of chip U4 to transmit the output second pulse signal. Pin 2 (signal input pin) of chip U4 is connected to the junction of resistors R16 and R17 to obtain the inverted second pulse signal output from the second signal detection module. Furthermore, resistor R21 is connected to pin 4 (signal output pin) of chip U4, and capacitor C4 is connected to pin 5 (VCC pin) of chip U4 and grounded to stabilize the power supply voltage. Simultaneously, pin 3 of chip U4 is grounded, and the emitter of transistor Q5 is also grounded. It should be noted that chip U4 can employ a single-channel tri-state control buffer. Pin 1 of chip U4 serves as the controlled terminal of the second switching control module and is active low. Therefore, when pin 1 of chip U4 receives a low-level signal, chip U4 is activated. The second pulse signal input from pin 2 of chip U4 passes through chip U4 and is output from pin 4. It should be understood that using a buffer in chip U4 enhances the signal driving capability and ensures signal integrity. Simultaneously, chip U4 effectively isolates signal distortion that may occur during switching, ensuring the stability and reliability of the output second pulse signal.

[0045] See Figures 1 to 4 In the second pulse signal switching circuit provided in some embodiments of this utility model, the monitoring reset module includes a resistor R22, a capacitor C5 and a chip U5. One end of the resistor R22 is connected to pin 4 of the chip U5, one end of the capacitor C5 and pin 2 of the chip U5 are connected to the power supply voltage terminal VCC, the other end of the resistor R22, the other end of the capacitor C5 and pin 3 of the chip U5 are respectively grounded, pin 6 of the chip U5 is connected to the connection point of the resistor R16, the resistor R17 and pin 2 of the chip U4, and pin 8 of the chip U5 is respectively connected to the connection point of the resistor R18 and the resistor R19 and pin 1 of the chip U2.

[0046] It should be noted that the monitoring and reset module consists of resistor R22, capacitor C5, and chip U5. One end of resistor R22 is connected to pin 4 of chip U5, and one end of capacitor C5 and pin 2 (VCC pin) of chip U5 are connected to the power supply voltage terminal VCC to provide power voltage for the monitoring and reset module. Capacitor C5 is used for filtering and stabilizing the power supply voltage. The other ends of resistor R22, capacitor C5, and pin 3 (GND pin) of chip U5 are grounded to ensure power supply stability and normal operation of the monitoring and reset module. Pin 6 (signal input pin) of chip U5 is connected to the connection point A of resistors R16 and R17 and pin 2 of chip U4, serving as the input terminal of the monitoring and reset module to monitor the status of the input second pulse signal. In addition, pin 8 (signal output pin) of chip U5 is connected to the connection point B of resistors R18 and R19 and pin 1 of chip U2, serving as the output terminal of the monitoring and reset module to control the first switching control module or the second switching control module to output the second pulse signal.

[0047] It is understood that chip U5 is a monitoring and reset chip, and its working logic is as follows: when pin 6 of chip U5 detects a low-level signal that persists for a period of time, pin 8 of chip U5 outputs a low-level signal as the output terminal of the monitoring and reset module; conversely, pin 8 of chip U5 outputs a high-level signal. In one embodiment, according to the manual of the monitoring and reset chip, the preset detection time of pin 6 of chip U5 is set to 1.6 seconds.

[0048] Specifically, this can be explained in conjunction with the above embodiments. When the second pulse signal is not connected to the second pulse signal switching circuit through the second second pulse signal input terminal, if pin 6 of chip U5 continuously detects a low-level signal output by the second signal monitoring module for 1.6 seconds, then pin 8 of chip U5 outputs a low-level signal. Simultaneously, pin 1 of chip U2 is active low, chip U2 is turned on, and thus outputs the second pulse signal connected to the second pulse switching circuit through the first second pulse signal input terminal. Pin 1 of chip U4 is connected to the collector of transistor Q5 as a control switch. When pin 8 of chip U5 outputs a low-level signal, transistor Q5 is turned off; when pin 1 of chip U4 detects a high-level signal, chip U4 is turned off.

[0049] Furthermore, when the second pulse signal is input to the second pulse signal switching circuit from the second second pulse signal input terminal, pin 6 of chip U5 detects the pulse signal output by the second signal detection module, and pin 8 of chip U5 outputs a high-level signal. Simultaneously, pin 1 of chip U2 is high-level and invalid, and chip U2 is turned off. Pin 1 of chip U4 is connected to the collector of transistor Q5 as a control switch. When pin 8 of chip U5 outputs a high-level signal, transistor Q5 conducts; pin 1 of chip U4 detects a low-level signal, and chip U4 conducts, thereby outputting the second pulse signal input to the second pulse signal switching circuit from the second second pulse signal input terminal.

[0050] See Figures 1 to 3 In the second pulse signal switching circuit provided in some embodiments of this utility model, the first second pulse signal input terminal includes interface J1 and resistor R23, and the second second pulse signal input terminal includes interface J2 and resistor R24. Pin 1 of interface J1 is connected to the other end of resistor R1 and one end of resistor R23, respectively. Pin 1 of interface J2 is connected to the other end of resistor R10 and one end of resistor R24, respectively. The other ends of resistor R23 and resistor R24 ​​are respectively connected to ground. It can be understood that pins 2, 3, 4, and 5 of interface J1 are grounded together, and pins 2, 3, 4, and 5 of interface J2 are grounded together. Both interface J1 and interface J2 are SMA RF interfaces for connecting external devices, which can receive two external second pulse signals 1PPS_IN1 and 1PPS_IN2. Resistors R23 and R24 not only limit the current but also filter high-frequency noise in the input second pulse signal. Through the coordinated work of the SMA RF interface and the current-limiting resistor, high-fidelity signal transmission and circuit reliability are ensured.

[0051] See Figures 1 to 5 In some embodiments of the present invention, the second pulse signal switching circuit includes an interface J3. Pin 1 of interface J3 is connected to the other end of resistor R9 and resistor R21, respectively. It should be noted that the second pulse signal output terminal is composed of interface J3, with pin 1 of interface J3 connected to the other ends of resistors R9 and R21, and pins 2, 3, 4, and 5 of interface J3 grounded. Interface J3 serves as the output interface for two second pulse signals, 1PPS_OUT1 and 1PPS_OUT2, outputting the processed and amplified second pulse signals to external devices. Simultaneously, the main function of resistors R9 and R21 is current limiting, protecting interface J3 and subsequent circuits from overcurrent damage and ensuring the stability of the second pulse signal transmission.

[0052] The embodiments of the present utility model have been described in detail above with reference to the accompanying drawings. However, the present utility model is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of the present utility model.

Claims

1. A pulese signal switching circuit, characterized by, The system includes a first signal detection module, a second signal detection module, a monitoring and reset module, a first switching control module, and a second switching control module. The output of the first signal detection module is connected to the input of the first switching control module. The output of the second signal detection module is connected to both the input of the second switching control module and the input of the monitoring and reset module. The output of the monitoring and reset module is connected to both the controlled end of the first switching control module and the controlled end of the second switching control module. The monitoring and reset module is configured to: upon receiving a second pulse signal from the output of the second signal detection module, output a switching control signal to the controlled end of the second switching control module, thereby causing the second switching control module to output the second pulse signal.

2. The second-pulse signal switching circuit according to claim 1, characterized by, It also includes a first-second pulse signal input terminal and a second-second pulse signal input terminal, with the input terminal of the first signal detection module connected to the first-second pulse signal input terminal and the input terminal of the second signal detection module connected to the second-second pulse signal input terminal.

3. The second-pulse signal switching circuit according to claim 2, characterized by, It also includes a second pulse signal output terminal, which is connected to the output terminal of the first switching control module and the output terminal of the second switching control module, respectively.

4. The second-pulse signal switching circuit according to claim 3, characterized by, The first signal detection module includes resistors R1, R2, R3, R4, R5, R6, R7, and R8, a capacitor C1, transistors Q1 and Q2, and a chip U1. The base of transistor Q1 is connected to one end of resistor R1 and one end of resistor R2, respectively. The collector of transistor Q1 is connected to one end of resistor R3, one end of resistor R4, and one end of resistor R5, respectively. The other end of resistor R4 is connected to the base of transistor Q2. The collector of transistor Q2 is connected to one end of resistor R6. One end of resistor R7 is connected to the other end of resistor R7, and the other end of resistor R7 is connected to one end of resistor R8. The other end of resistor R5 is connected to pin 2 of chip U1, and the other end of resistor R8 is connected to pin 4 of chip U1. The other end of resistor R3, the other end of resistor R6, one end of capacitor C1, and pin 5 of chip U1 are respectively connected to the power supply voltage terminal VCC. The other end of resistor R2, the emitter of transistor Q1, the emitter of transistor Q2, the other end of capacitor C1, and pin 3 of chip U1 are respectively grounded.

5. The second-pulse signal switching circuit according to claim 4, characterized by, The first switching control module includes a resistor R9, a capacitor C2 and a chip U2. Pin 2 of the chip U2 is connected to the connection point of the resistors R7 and R8. One end of the resistor R9 is connected to pin 4 of the chip U2. One end of the capacitor C2 and pin 5 of the chip U2 are connected to the power supply voltage terminal VCC. The other end of the capacitor C2 and pin 3 of the chip U2 are respectively grounded.

6. The second-pulse signal switching circuit according to claim 5, characterized by The second signal detection module includes resistors R10, R11, R12, R13, R14, R15, R16, and R17, capacitor C3, transistors Q3 and Q4, and chip U3. The base of transistor Q3 is connected to one end of resistor R10 and one end of resistor R11, respectively. The collector of transistor Q3 is connected to one end of resistor R12, one end of resistor R13, and one end of resistor R14, respectively. The other end of resistor R13 is connected to the base of transistor Q4, and the collector of transistor Q4 is connected to resistors R10, R11, R12, R13, R14, and R15, respectively. One end of resistor R5 is connected to one end of resistor R16, the other end of resistor R16 is connected to one end of resistor R17, the other end of resistor R14 is connected to pin 2 of chip U3, the other end of resistor R17 is connected to pin 4 of chip U3, the other end of resistor R12, the other end of resistor R15, one end of capacitor C3 and pin 5 of chip U3 are respectively connected to the power supply voltage terminal VCC, and the other end of resistor R11, the emitter of transistor Q3, the emitter of transistor Q4, the other end of capacitor C3 and pin 3 of chip U3 are respectively grounded.

7. The second-pulse signal switching circuit according to claim 6, characterized by The second switching control module includes resistors R18, R19, R20, and R21, capacitor C4, transistor Q5, and chip U4. One end of resistor R18 is connected to one end of resistor R19, and the other end of resistor R19 is connected to the base of transistor Q5. The collector of transistor Q5 is connected to one end of resistor R20 and pin 1 of chip U4. Pin 2 of chip U4 is connected to the connection point of resistors R16 and R17. One end of resistor R21 is connected to pin 4 of chip U4. One end of capacitor C4 and pin 5 of chip U4 are connected to the power supply voltage terminal VCC. The other end of capacitor C4, the emitter of transistor Q5, and pin 3 of chip U4 are grounded.

8. The second-pulse signal switching circuit according to claim 7, characterized by The monitoring and reset module includes a resistor R22, a capacitor C5, and a chip U5. One end of the resistor R22 is connected to pin 4 of the chip U5. One end of the capacitor C5 and pin 2 of the chip U5 are connected to the power supply voltage terminal VCC. The other end of the resistor R22, the other end of the capacitor C5, and pin 3 of the chip U5 are grounded respectively. Pin 6 of the chip U5 is connected to the connection point of the resistor R16, the resistor R17, and pin 2 of the chip U4. Pin 8 of the chip U5 is connected to the connection point of the resistor R18 and the resistor R19, and pin 1 of the chip U2.

9. The second-pulse signal switching circuit according to claim 8, characterized by The first second pulse signal input end includes interface J1 and resistance R23, the second second pulse signal input end includes interface J2 and resistance R24, the pin 1 of the interface J1 is connected with the other end of the resistance R1 and one end of the resistance R23 respectively, the pin 1 of the interface J2 is connected with the other end of the resistance R10 and one end of the resistance R24 respectively, the other end of the resistance R23 and the other end of the resistance R24 are connected with ground respectively.

10. The second-pulse signal switching circuit according to claim 9, characterized by, The second pulse signal output end includes interface J3, the pin 1 of the interface J3 is connected with the other end of the resistance R9 and the other end of the resistance R21 respectively.

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