A pcie fiber communication board for dedicated components

Abstract

The utility model discloses a kind of PCIE optical fiber communication boards for special components, including FPGA, FPGA is integrally connected with synchronous clock input interface, three-way digital optical fiber receiving interface, SMA input interface, TypeC interface group, independent SDRAM storage unit and optical signal output port by function interface;FPGA is coordinated each above-mentioned component module work, realizes the protocol conversion of PCIE protocol and optical fiber communication, data encoding and decoding, cache management function.The utility model innovatively adopts mixed clock domain architecture, organically combines synchronous clock tree and asynchronous data channel, simultaneously supports the mixed networking mode of copper cable and optical fiber through photoelectric composite interface design, while guaranteeing high-speed data transmission, effectively reduce the electromagnetic interference influence in transmission path;In addition, the multi-protocol conversion engine and hardware acceleration module integrated in FPGA further improve the processing efficiency and flexibility of system.

Description

Technical Field

[0001] This utility model relates to the field of communication technology, specifically to a PCIE fiber optic communication board for dedicated components. Background Technology

[0002] Traditional copper-cable PCIe transmission methods have significant limitations in terms of long-distance transmission, electromagnetic interference (EMI) immunity, and signal integrity, making it difficult to meet the stringent requirements of certain specialized equipment. Magnetic resonance imaging (MRI) systems, as crucial equipment in modern medical diagnostics, rely heavily on high-speed, stable data transmission between components. However, because these systems commonly use copper-cable electrical signal transmission, strong electromagnetic interference generated by radio frequency components and gradient power amplifiers during operation can couple into the electrical signal transmission lines through conduction and radiation, resulting in strong interference signals in the transmitted signal. This, in turn, affects system communication, imaging quality, and even the normal operation of the system. Furthermore, with the current development of multi-channel array coils, data transmission is growing exponentially, further highlighting the limitations of electrical signal transmission in terms of bandwidth and transmission distance.

[0003] Fiber optic communication, with its advantages of high bandwidth, low loss, interference resistance, and long-distance transmission, has become an ideal alternative to copper cables. Compared with electrical signal transmission, optical signal transmission has inherent electromagnetic interference resistance and is completely unaffected by strong magnetic field environments. Furthermore, fiber optic transmission has significant advantages in bandwidth, transmission distance, and signal integrity. However, most fiber optic conversion solutions currently on the market use independent external modules, which suffer from problems such as large size, high power consumption, and low integration, making them difficult to embed directly into the compact structure of dedicated equipment. Therefore, we provide a highly integrated PCIe fiber optic communication board to solve these problems. Utility Model Content

[0004] The purpose of this invention is to provide a PCIe fiber optic communication board for specialized components. Through optimized photoelectric conversion circuitry, embedded signal conditioning, and a compact optical module design, it achieves efficient fiber optic transmission of PCIe signals, making it suitable for demanding applications in magnetic resonance imaging (MRI) component scenarios with stringent requirements for space, interference immunity, and stability. It not only effectively solves electromagnetic interference problems but also meets the stringent high-speed data transmission requirements of MRI systems, providing reliable technical support for improving the overall performance of MRI systems.

[0005] This utility model can be achieved through the following technical solution: a PCIE fiber optic communication board for dedicated components, including an FPGA, wherein the FPGA is integrated with a synchronous clock input interface, three digital fiber optic receiving interfaces, an SMA input interface, a Type C interface group, an independent SDRAM storage unit and an optical signal output port through functional interfaces.

[0006] The synchronous clock input interface provides precise clock configuration through a clock buffer, and the three digital fiber optic receiver interfaces adopt asynchronous communication to achieve high-speed data interaction with external modules.

[0007] The FPGA, as the core processing unit, is responsible for coordinating the work of the above-mentioned component modules and realizing the functions of protocol conversion between PCIe protocol and fiber optic communication, data encoding and decoding, and cache management.

[0008] A further technical improvement of this utility model is that the FPGA adopts Arri a10 series devices, can be configured with FIFO protocol, and supports PCIe 4×Gen3.

[0009] A further technical improvement of this utility model is that the SMA interface and the Type-C interface group serve as backup interfaces to provide expansion capabilities.

[0010] A further technical improvement of this utility model is that three independent SDRAM memory units provide high-speed data cache support for the system, all of which adopt a 32M×16Bi t capacity configuration.

[0011] A further technical improvement of this utility model is that the optical signal output port adopts an SFP+ module, which supports an adjustable transmission rate of 2.5Gbps-10.3Gbps.

[0012] Compared with the prior art, the present invention has the following beneficial effects:

[0013] This utility model's fiber optic communication board innovatively adopts a hybrid clock domain architecture, organically combining a synchronous clock tree with an asynchronous data channel. At the same time, it supports hybrid networking of copper cables and optical fibers through an optoelectronic composite interface design, effectively reducing the impact of electromagnetic interference in the transmission path while ensuring high-speed data transmission. In addition, the multi-protocol conversion engine and hardware acceleration module integrated within the FPGA further improve the system's processing efficiency and flexibility. Attached Figure Description

[0014] To facilitate understanding by those skilled in the art, the present invention will be further described below with reference to the accompanying drawings.

[0015] Figure 1 This is a frame diagram of the PCIE fiber optic communication board of this utility model.

[0016] In the diagram: 1. Synchronous clock input interface; 2. Three-channel digital fiber optic receiver interface; 3. SMA input interface; 4. Type-C interface group; 5. Independent SDRAM storage unit; 6. Optical signal output port. Detailed Implementation

[0017] To further illustrate the technical means and effects adopted by this utility model in order to achieve the intended utility model purpose, the following detailed description of the specific implementation methods, structure, features and effects of this utility model is provided in conjunction with the accompanying drawings and preferred embodiments.

[0018] A PCIE fiber optic communication board for dedicated components is based on an integrated architecture design based on Intel Arria 10 series FPGAs. The FPGA is used as the core processing unit and the modular design enables the collaborative operation of various functional interfaces.

[0019] The FPGA uses Arri a10 series devices. The FPGA has a large number of interfaces, which can meet the data communication between various different buses. It can be configured with FIFO protocol and supports optical signal data communication up to 2.5Gps. Different acquisition speeds can be achieved through different rate modules. It supports PCIe 4×Gen3 to achieve high-speed communication with commercial server PCs.

[0020] like Figure 1 As shown, the fiber optic communication board integrates a synchronous clock input interface 1, three digital fiber optic receiver interfaces 2, an SMA input interface 3, a Type-C interface group 4, an independent SDRAM memory unit 5, and an optical signal output port 6; wherein:

[0021] The synchronous clock input interface 1 uses a high-precision clock distributor to achieve multi-channel clock distribution, converting the externally input synchronous clock signal into multiple synchronous clock signals, thereby driving the various functional banks of the FPGA, such as the core working clock bank, high-speed data interface bank and other key modules, to ensure that the system clock synchronization accuracy is better than 100ps.

[0022] The three-channel digital fiber optic receiver interface 2 is used as the optical signal interaction port for external modules. It supports optical signal conversion in the wavelength range of 1260 to 1625 nm and adopts an asynchronous communication architecture to realize independent clock domain processing for each channel. It adaptively matches the transmission efficiency of 1 Mbps to 2.5 Gbps, providing a reliable external data interaction channel for the system.

[0023] In this embodiment, three SMA input interfaces 3 are provided. Three 50Ω impedance-matched SMA connectors are used as backup expansion interfaces. They support gated signals and asynchronous serial data reception at a maximum rate of 380MHz and have a complete ESD protection design, serving as backup expansion interfaces for the system.

[0024] In this embodiment, four Type-C interface groups 4 are provided as backup expansion interfaces, compatible with the USB 3.1 Gen1 protocol, used for external electrical signal data communication, and can support high-speed data transmission of up to 115.2kbps, providing the system with flexible external electrical signal communication expansion capabilities;

[0025] The independent SDRAM memory unit 5 is set into three groups, each with a capacity of 32M×16B it, and each supports a maximum communication rate of 133MHz, providing the processor with high-speed data storage and access support for storing the operating system, real-time data processing, etc.

[0026] Optical signal output port 6 uses an SFP+ module and supports adjustable transmission rates from 2.5Gbps to 10.3Gbps. In this embodiment, 2.5Gbps high-speed data transmission is used, converting the high-speed electrical signal data generated by the processor into optical signals. Long-distance transmission of over 10 kilometers can be achieved through single-mode optical fiber, and it also features anti-electromagnetic interference designs such as automatic laser power control.

[0027] The above description is merely a preferred embodiment of the present utility model and is not intended to limit the present utility model in any way. Although the present utility model has been disclosed above with reference to a preferred embodiment, it is not intended to limit the present utility model. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present utility model. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present utility model without departing from the scope of the present utility model shall still fall within the scope of the present utility model.

Claims

1. A PCIE fiber optic communication board for dedicated components, characterized in that, The FPGA includes a synchronous clock input interface (1), a three-channel digital fiber optic receiver interface (2), an SMA input interface (3), a Type C interface group (4), an independent SDRAM storage unit (5), and an optical signal output port (6) integrated through a functional interface. The synchronous clock input interface (1) provides precise clock configuration through a clock buffer, and the three digital fiber optic receiving interfaces (2) adopt asynchronous communication to achieve high-speed data interaction with external modules; The FPGA, as the core processing unit, is responsible for coordinating the work of the above-mentioned component modules and realizing the functions of protocol conversion between PCIe protocol and fiber optic communication, data encoding and decoding, and cache management.

2. The PCIE fiber optic communication board for a dedicated component according to claim 1, characterized in that, The FPGA uses Arria10 series devices, is configurable with FIFO protocol, and supports PCIe 4× Gen3.

3. A PCIE fiber optic communication board for dedicated components according to claim 1, characterized in that, The SMA input interface (3) and the Type C interface group (4) serve as backup interfaces, providing expansion capabilities.

4. A PCIE fiber optic communication board for dedicated components according to claim 1, characterized in that, Three independent SDRAM memory units (5) provide high-speed data cache support for the system, all of which are configured with a capacity of 32M×16 Bit.

5. A PCIE fiber optic communication board for dedicated components according to claim 1, characterized in that, The optical signal output port (6) adopts an SFP+ module and supports an adjustable transmission rate of 2.5Gbps-10.3Gbps.

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