Marine HUD circuitry
By designing a marine HUD circuit system, the problem of HUD display being easily covered under direct sunlight was solved, and stable control of HUD and vehicle lights was achieved, meeting the needs of ship navigation safety and communication, and improving the operating experience and efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- SHANGHAI INESA ELECTRONICS (GRP) CO LTD
- Filing Date
- 2025-08-15
- Publication Date
- 2026-06-23
AI Technical Summary
Existing marine HUDs are easily obscured by strong light under direct sunlight and have poor compatibility, failing to meet the needs of ship navigation safety and maritime communication.
A marine HUD circuit system was designed, including a main controller, a lighting controller, a display driver module, and a power adapter module. Through components such as synchronous step-down converters, switching regulators, and linear regulators, a stable power supply and signal drive are provided. Combined with the HUD control and vehicle light control switching module, stable control of the HUD display and vehicle lights is achieved.
Stable display of navigation parameters under direct sunlight conditions, meeting the ship's lighting and communication needs, improving navigation efficiency and handling experience, and ensuring stable navigation.
Smart Images
Figure CN224401710U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of marine display equipment technology, specifically to a marine HUD circuit system. Background Technology
[0002] A head-up display (HUD) is a transparent display technology that projects critical information into the user's field of vision. Originally designed for fighter pilots, it is now widely used in the automotive, marine, aerospace, and industrial sectors. Its core objective is to allow users to access information without looking down, thereby improving operational safety and efficiency.
[0003] Common HUDs have poor environmental adaptability, especially those used on ships. Since ships often sail in vast waters such as rivers, lakes and seas, there are no obstructions and direct sunlight. When exposed to direct sunlight, the display is more likely to be covered by strong light due to insufficient brightness, which poses a safety hazard.
[0004] In addition, since some ships sail on the sea, in order to ensure navigation safety, they need to access maritime communication protocols, radar, AIS and other protocols. Common HUDs have poor compatibility and cannot meet the above connection requirements. Utility Model Content
[0005] This invention aims to solve the technical problems existing in the prior art, and innovatively proposes a marine HUD circuit system that can stably drive the HUD for display.
[0006] To achieve the above objectives, this utility model provides a marine HUD circuit system, including a main controller. The main controller's lighting signal output terminal is connected to the lighting signal input terminal of a lighting controller. The lighting controller's drive signal output terminal is connected to the drive signal input terminal of a headlight driver. The main controller's display drive signal output terminal is connected to the display signal input terminal of a display driver module. The system also includes a power adapter module, which is used to supply power to various electrical devices.
[0007] In the above scheme: the power adapter module includes a synchronous buck converter. The power input terminal of the synchronous buck converter is connected to one end of capacitor C31, one end of capacitor C37, one end of resistor R540, one end of capacitor C41, and one end of capacitor C23. The other end of capacitor C23 is connected to one end of inductor L5 and the ship's main information output terminal. The other end of inductor L5 is connected to one end of terminal block J1 and one end of capacitor C571. The ground terminal of the synchronous buck converter, the other end of capacitor C31, capacitor C37, capacitor C41, capacitor C23, and capacitor C571 are all connected to the power ground. The other end of resistor R540 is connected to the enable terminal of the synchronous buck converter. The VCC terminal of the synchronous buck converter is connected to one end of capacitor C587, and the other end of capacitor C587 is connected to the power ground.
[0008] The BOOT terminal of the synchronous buck converter is connected to one end of capacitor C38. The other end of capacitor C38 is connected to the NC terminal of the synchronous buck converter and one end of inductor L2. The other end of inductor L2 is connected to one end of capacitor C26, one end of capacitor C536, one end of resistor R535, one end of capacitor C19, one end of capacitor C18, one end of resistor R20, one end of capacitor C537, the VIN terminal of the switching regulator, the VIN terminal of the load switch, and the VIN terminal of the regulator. The other end of capacitor C26 is connected to resistor R536. The other end of resistor R544 is connected to the feedback terminal of the synchronous buck converter and one end of resistor R544. The other ends of resistor R544, capacitor C536, capacitor C19, and capacitor C18 are all connected to power ground. The other end of resistor R20 is connected to the CTRL terminal of the switching regulator and the PG terminal of the synchronous buck converter. The COMP terminal of the switching regulator is connected to one end of resistor R517. The other end of resistor R517 is connected to the other end of capacitor C519. The other end of capacitor C519 is connected to power ground.
[0009] The SW terminal of the switching regulator is connected to one end of inductor L516 and the positive terminal of diode D1. The other end of inductor L516 is connected to the VIN terminal of the switching regulator. The negative terminal of diode D1 is connected to one end of resistor R508, one end of capacitor C2, one end of capacitor C513, one end of resistor R505, one end of capacitor C512, and the IN and IN2 terminals of the linear regulator. The other end of resistor R508 is connected to the feedback terminal of the switching regulator and one end of resistor R4. The other end of resistor R4, the ground terminal of the switching regulator, the other end of capacitor C2, the other end of capacitor C513, the other end of capacitor C512, and the ground terminal of the linear regulator are all connected to the power supply ground. The output terminal and SNS terminal of the linear regulator are both connected to one end of resistor R500. The other end of resistor R500 is connected to one end of capacitor C516. The other end of capacitor C516 is connected to the power supply ground.
[0010] In the above scheme: the ON terminal of the load switch is connected to the enable terminal of the lighting controller and one end of the resistor R5, the other end of the resistor R5 and the ground terminal of the load switch are connected to the power supply ground, the output terminal of the load switch outputs 3.3V voltage, which is the 3.3V power supply terminal of the power adapter module, and is connected to one end of the resistor R9, the other end of the resistor R9 is connected to the QOD terminal of the load switch, and the CT terminal of the load switch is connected to the power supply ground;
[0011] The first enable terminal of the voltage regulator is connected to the enable terminal of the lighting controller and one end of resistor R13. The second enable terminal of the voltage regulator is connected to the enable terminal of the lighting controller and one end of resistor R16. The other ends of resistor R13, resistor R16, and the voltage regulator's ground terminal are connected to the power supply ground. The voltage regulator's MODE / DATA terminal is connected to one end of resistor R21, and the other end of resistor R21 is connected to the power supply ground. The first output terminal of the voltage regulator is connected to one end of inductor L518. The other end of inductor L518 outputs a 1.8V voltage, which is the 1.8V power supply terminal for the power adapter module. The other end of inductor L518 is also connected to the voltage regulator's feedback terminal, one end of resistor R513, one end of capacitor C526, and one end of capacitor C525. The other end of resistor R513 is connected to one end of resistor R514. The other ends of resistor R514, capacitor C526, and capacitor C525 are all connected to the power supply ground. The second output terminal of the voltage regulator is connected to one end of inductor L520. The other end of inductor L520 outputs a 1.1V voltage, which is the 1.1V power supply terminal for the power adapter module. The other end of inductor L520 is also connected to one end of capacitor C561, one end of resistor R24, one end of capacitor C559, and one end of capacitor C27. The other end of resistor R24 is connected to one end of resistor R32. The other ends of resistor R32, capacitor C559, and capacitor C27 are all connected to the power supply ground. The other end of capacitor C561 is connected to the ADJ2 terminal of the voltage regulator.
[0012] In the above scheme: the input terminal of the main controller PLL_REFCLK is connected to one end of capacitor C518, one end of resistor R509, and the first terminal of oscillator Y500; the output terminal of the main controller PLL_REFCLK is connected to the other end of resistor R509 and one end of resistor R520; one end of resistor R520 is connected to the third terminal of oscillator Y500 and one end of capacitor C521; the other end of capacitor C521 and the other end of capacitor C518 are connected to power ground; the VCC3IO_COSC terminal of the main controller is connected to one end of ferrite bead L519 and one end of capacitor C542; the other end of ferrite bead L519 is connected to the 3.3V power supply terminal; the GNDIOLA_COSC terminal of the main controller is connected to the other end of capacitor C542 and connected to power ground; the VCC11AD_PLLM terminal of the main controller is connected to the power supply ground. One end of capacitor C533, one end of capacitor C4, and one end of ferrite bead L512 are connected. The main controller's GND11AD_PLLM terminal is connected to the other end of capacitor C533, the other end of capacitor C4, and one end of ferrite bead L513. The other end of ferrite bead L512 is connected to the 1.1V power supply terminal and one end of capacitor C1. The other end of capacitor C1 and the other end of ferrite bead L513 are connected to power ground. The main controller's VCC11AD_PLLD terminal is connected to one end of capacitor C534, one end of capacitor C5, and one end of ferrite bead L515. The main controller's GND11AD_PLLD terminal is connected to the other end of capacitor C534, the other end of capacitor C5, and one end of ferrite bead L517. The other end of ferrite bead L515 is connected to the 1.1V power supply terminal and one end of capacitor C9. The other end of capacitor C9 and the other end of ferrite bead L517 are connected to power ground.
[0013] The PMIC_SPI_DIN terminal of the master controller is connected to the SPI1_DOUT terminal of the lighting controller. The PMIC_SPI_DOUT terminal of the master controller is connected to the SPI1_DIN terminal of the lighting controller and one end of resistor R574. The other end of resistor R574 is connected to power ground. The PMIC_SPI_CSZ_0 terminal of the master controller is connected to the SPI1_SS terminal of the lighting controller and one end of resistor R61. The PMIC_SPI_CLK terminal of the master controller is connected to the SPI1_CLK terminal of the lighting controller and one end of resistor R575. The other ends of resistor R61 and resistor R575 are connected to power ground.
[0014] The GPIO_00 pin of the main controller is connected to one end of resistor R532. The other end of resistor R532 is connected to one end of ferrite bead FB1 and one end of resistor R512. The other end of resistor R512 is connected to power ground. The other end of ferrite bead FB1 is connected to the seventh pin of the headlight driver interface J2, and is connected to the headlight driver through the headlight driver interface J2. The PMIC_LEDSEL_0_S pin of the main controller is connected to one end of resistor R521. The other end of resistor R521 is connected to the first pin of the headlight driver interface J2. The main controller PMIC_LEDSEL_1_S terminal is connected to one end of resistor R12, and the other end of resistor R12 is connected to the second terminal of the headlight driver interface J2. The main controller PMIC_LEDSEL_2_S terminal is connected to one end of resistor R522, and the other end of resistor R522 is connected to the third terminal of the headlight driver interface J2. The main controller PMIC_LEDSEL_3_S terminal is connected to one end of resistor R11, and the other end of resistor R11 is connected to the fourth terminal of the headlight driver interface J2.
[0015] The main controller's GPIO_04 terminal is connected to one end of resistor R54 and the lighting controller's D_EN terminal, with the other end of resistor R54 connected to the power supply ground. The main controller's GPIO_03 terminal is connected to one end of resistor R569 and the lighting controller's S_EN terminal, with the other end of resistor R569 connected to the power supply ground. The main controller's PMIC_AD3_POCI terminal is connected to the lighting controller's AD3_MISO terminal. The main controller's PMIC_AD3_PICO terminal is connected to one end of resistor R41 and the lighting controller's AD3_MOSI terminal, with the other end of resistor R41 connected to the power supply ground. The main controller's PMIC_AD3_SEQ_CLK terminal is connected to one end of resistor R41 and the lighting controller's SEQ_CLK terminal, with the other end of resistor R41 connected to the power supply ground.
[0016] The main controller PMIC_WD1_S terminal is connected to one end of resistor R546, and the other end of resistor R546 is connected to the lighting controller WD1 terminal. The main controller PMIC_SEQ_STRT_S terminal is connected to one end of resistor R19, and the other end of resistor R19 is connected to the lighting controller WD2 terminal. The main controller PWM1_COMPOUT_S terminal is connected to one end of resistor R10, and the other end of resistor R10 is connected to one end of ferrite bead FB2. The other end of ferrite bead FB2 is connected to the eighth terminal of the headlight driver interface J2. The main controller PMIC_INTZ terminal is connected to one end of resistor R561 and the lighting controller INT terminal, and the other end of resistor R561 is connected to the 3.3V power supply terminal. The main controller PMIC_PARKZ terminal is connected to one end of resistor R559 and the lighting controller PARK terminal, and the other end of resistor R559 is connected to the power supply ground. The main controller RESETZ terminal is connected to one end of resistor R50 and the lighting controller reset terminal, and the other end of resistor R50 is connected to the power supply ground.
[0017] The lighting controller R_EN terminal is connected to one end of ferrite bead L506, and the other end of ferrite bead L506 is connected to the tenth terminal of terminal block J500. The headlight driver is connected through terminal block J500. The lighting controller G_EN terminal is connected to one end of ferrite bead L505, and the other end of ferrite bead L505 is connected to the eleventh terminal of terminal block J500. The lighting controller B_EN terminal is connected to one end of ferrite bead L504, and the other end of ferrite bead L504 is connected to the twelfth terminal of terminal block J500. The lighting controller PMIC_SEN1 terminal is connected to one end of ferrite bead L509, and the other end of ferrite bead L509 is connected to the fifth terminal of terminal block J500. The lighting controller PMIC_SEN2 terminal is connected to one end of ferrite bead L507, and the other end of ferrite bead L507 is connected to the eighth terminal of terminal block J500.
[0018] The lighting controller PMIC_CMODE terminal is connected to one end of ferrite bead L508, and the other end of ferrite bead L508 is connected to the seventh terminal of terminal block J500. The lighting controller PMIC_LM3409_DRVEN terminal is connected to one end of ferrite bead L510, and the other end of ferrite bead L510 is connected to the third terminal of terminal block J500. The lighting controller PMIC_LS_SENSE_P terminal is connected to one end of ferrite bead L502, and the other end of ferrite bead L502 is connected to the sixteenth terminal of terminal block J500. The MIC_LS_SENSE_N terminal is connected to one end of the ferrite bead L501, and the other end of the ferrite bead L501 is connected to the seventeenth terminal of the terminal block J500. The lighting controller PMIC_LM3409_SYNC terminal is connected to one end of the ferrite bead L511, and the other end of the ferrite bead L511 is connected to the first terminal of the terminal block J500. The lighting controller PMIC_LM3409_IADJ terminal is connected to one end of the ferrite bead L500, and the other end of the ferrite bead L500 is connected to the nineteenth terminal of the terminal block J500.
[0019] The above solution also includes a HUD control and headlight control switching module, comprising a signal switch U10, wherein terminal U10A is connected to the other end of resistor R523, the low-level enable terminal of signal switch U10 is connected to the GPIO_9 terminal of the main controller, terminal U10B is connected to the PMIC_LM3409_DRVEN terminal of the lighting controller, and terminal U10VCC is connected to a 3.3V power supply terminal; and a signal switch U9, wherein terminal U9A is connected to the PMIC_COMPOUT terminal of the lighting controller, the low-level enable terminal of signal switch U9 is connected to the GPIO_9 terminal of the main controller, terminal U9B is connected to the PWM1_COMPOUT_S terminal of the main controller, and terminal U9VCC is connected to a 3.3V power supply terminal;
[0020] It also includes a NOT gate buffer U13, whose VCC terminal is connected to one end of resistor R570, the 3.3V power supply terminal, and one end of capacitor C59. The other end of resistor R570 and the A terminal of NOT gate buffer U13 are both connected to the GPIO_9 terminal of the main controller, and the other end of capacitor C59 is connected to the power supply ground. The Y terminal of NOT gate buffer U13 is connected to the first input terminal of each AND gate group of AND gate chip U14. The other input terminal of the first group of AND gate chip U14 is connected to the other end of resistor R521. The first group of output terminals of AND gate chip U14 is connected to the lighting controller HUD_LEDS. The AND gate chip U14 has the following terminals: EL_0 terminal; another input terminal of the second group of AND gate chip U14 is connected to the other end of resistor R521, and the output terminal of the second group of AND gate chip U14 is connected to the HUD_LEDSEL_1 terminal of the lighting controller; another input terminal of the third group of AND gate chip U14 is connected to the other end of resistor R521, and the output terminal of the third group of AND gate chip U14 is connected to the HUD_LEDSEL_2 terminal of the lighting controller; another input terminal of the fourth group of AND gate chip U14 is connected to the other end of resistor R521, and the output terminal of the fourth group of AND gate chip U14 is connected to the HUD_LEDSEL_3 terminal of the lighting controller.
[0021] The JTAGRSTZ terminal of the main controller is connected to one end of resistor R531, and the other end of resistor R531 is connected to power ground; the GPIO_11 terminal of the main controller is connected to one end of resistor R18, and the other end of resistor R18 is connected to power ground; the GPIO_12 terminal of the main controller is connected to one end of resistor R533, and the other end of resistor R533 is connected to power ground; the GPIO_10 terminal of the main controller is connected to one end of resistor R536, and the other end of resistor R536 is connected to power ground; the GPIO_13 terminal of the main controller is connected to resistor R22. One end of resistor R22 is connected to power ground; the main controller GPIO_22 is connected to one end of resistor R548, and the other end of resistor R548 is connected to power ground; the main controller GPIO_23 is connected to one end of resistor R547, and the other end of resistor R547 is connected to power ground; the main controller GPIO_24 is connected to one end of resistor R542, and the other end of resistor R542 is connected to power ground; the main controller GPIO_25 is connected to one end of resistor R550, and the other end of resistor R550 is connected to power ground.
[0022] The main controller's TESTPT0 terminal is connected to one end of resistor R549, and the other end of resistor R549 is connected to the digital bus switch U510B terminal. The digital bus switch U510A terminal and VCC terminal are both connected to the 3.3V power supply terminal. The low-level enable terminal of the digital bus switch U510 is connected to one end of resistor R571, and the other end of resistor R571 is connected to the 3.3V power supply terminal. The ground terminal of the digital bus switch U510 is connected to the power supply ground.
[0023] The main controller's CHKSUM_SEL terminal is connected to one end of resistor R552, the other end of resistor R552 is connected to the first terminal of DIP switch SW1, and the second terminal of DIP switch SW1 is connected to the 3.3V power supply terminal; the main controller's HOST_IF_SEL terminal is connected to one end of resistor R37, the other end of resistor R37 is connected to the first terminal of DIP switch SW2, and the second terminal of DIP switch SW2 is connected to the 3.3V power supply terminal; the main controller's HOST_SPI_MODE terminal is connected to one end of resistor R38, the other end of resistor R38 is connected to the first terminal of DIP switch SW3, and the second terminal of DIP switch SW3 is connected to the 3.3V power supply terminal; the main controller's TESTPT5 terminal is connected to one end of resistor R556, the other end of resistor R556 is connected to the first terminal of DIP switch SW4, and the second terminal of DIP switch SW4 is connected to the 3.3V power supply terminal.
[0024] In the above scheme: the display driver module includes a DVI receiver, the parallel data bus signal terminal of the main controller is connected to the parallel data bus signal terminal of the DVI receiver, the differential signal terminal of the DVI receiver is connected to the differential signal terminal of the filter module, and the filtered signal output terminal of the filter module is connected to the filtered signal input terminal of the HDMI input interface J4.
[0025] In the above scheme: the filtering module includes four modules, namely a first filtering module, a second filtering module, a third filtering module, and a fourth filtering module. The positive terminal of the third channel of the differential signal of the DVI receiver is connected to the C1 terminal of the fourth filtering module, the negative terminal of the third channel of the differential signal of the DVI receiver is connected to the C2 terminal of the fourth filtering module, the positive terminal of the third channel of the filtered signal of the fourth filtering module is connected to the J4TMDS_data_2+ terminal of the HDMI input interface, and the negative terminal of the third channel of the filtered signal of the fourth filtering module is connected to the J4TMDS_data_2- terminal of the HDMI input interface.
[0026] The positive terminal of the second differential signal channel of the DVI receiver is connected to the C1 terminal of the third filter module, the negative terminal of the second differential signal channel of the DVI receiver is connected to the C2 terminal of the third filter module, the positive terminal of the second filtered signal channel of the third filter module is connected to the J4TMDS_data_1+ terminal of the HDMI input interface, and the negative terminal of the second filtered signal channel of the third filter module is connected to the J4TMDS_data_1- terminal of the HDMI input interface.
[0027] The positive terminal of the first differential signal channel of the DVI receiver is connected to the C1 terminal of the second filter module, the negative terminal of the first differential signal channel of the DVI receiver is connected to the C2 terminal of the second filter module, the positive terminal of the first filtered signal channel of the second filter module is connected to the J4TMDS_data_1+ terminal of the HDMI input interface, and the negative terminal of the first filtered signal channel of the second filter module is connected to the J4TMDS_data_1- terminal of the HDMI input interface.
[0028] The positive terminal of the differential signal clock channel of the DVI receiver is connected to the C1 terminal of the first filter module, the negative terminal of the differential signal clock channel of the DVI receiver is connected to the C2 terminal of the first filter module, the positive terminal of the filter signal clock channel of the first filter module is connected to the J4TMDS_clock+ terminal of the HDMI input interface, and the negative terminal of the filter signal clock channel of the first filter module is connected to the J4TMDS_clock+ terminal of the HDMI input interface.
[0029] The HDMI input interface J4 DDC_data terminal is connected to the second input terminal of the ESD protection module U502, one end of resistor R507, and the SDA terminal of the storage module U503. The other end of resistor R507 is connected to the HDMI input interface J4+5V_power terminal. The HDMI input interface J4 DDC_clock terminal is connected to the second input terminal of the ESD protection module U502, one end of resistor R518, and the SCL terminal of the storage module U503. The other end of resistor R518 and the VCC terminal of the storage module U503 are connected to the HDMI input interface J4+5V_power terminal. The third terminal of the ESD protection module U502 is connected to the power ground.
[0030] The host controller's HOST_IRQ_S terminal is connected to one end of resistor R39. The other end of resistor R39 is connected to the NOT gate buffer U15A terminal and the SPI protection chip U17D1+. The NOT gate buffer U15VCC terminal is connected to the 3.3V power supply terminal. The NOT gate buffer U15Y terminal is connected to one end of resistor R572 and the bridge U11GPIO_16 terminal. The other end of resistor R572 is connected to the other end of inductor L2. The host controller's HOST_I2C_SDA terminal is connected to the level converter U7A1 terminal and the first input terminal of the ESD protection chip U16. The host controller's HOST_I2C_SCL terminal is connected to the level converter U7A2 terminal and the second input terminal of the ESD protection chip U16. The ground terminal of the ESD protection chip U16 is connected to the power supply ground.
[0031] The above solution also includes a jumper module for switching between Cypress and SPI buses. This includes connecting the host controller's HOST_SPI_CLK terminal to the second terminal of connector J10; connecting the first terminal of connector J10 to one end of resistor R582; connecting the other end of resistor R582 to the seventh terminal of SPI connector J15 and the SPI protection chip U512D1+; connecting the third terminal of connector J10 to one end of resistor R567; and connecting the other end of resistor R567 to the SPI bus transceiver U12B3 terminal.
[0032] The host controller HOST_SPI_CSZ terminal is connected to the second terminal of connector J12. The first terminal of connector J12 is connected to one end of resistor R581. The other end of resistor R581 is connected to the ninth terminal of SPI connector J15 and the D2- terminal of SPI protection chip U512. The third terminal of connector J12 is connected to one end of resistor R564. The other end of resistor R564 is connected to the SPI bus transceiver U12B4 terminal.
[0033] The host controller HOST_SPI_PICO terminal is connected to the second terminal of connector J11. The first terminal of connector J11 is connected to one end of resistor R583 and the SPI protection chip U512D1- terminal. The other end of resistor R583 is connected to the eighth terminal of SPI connector J15. The third terminal of connector J11 is connected to one end of resistor R568. The other end of resistor R568 is connected to the SPI bus transceiver U12B1 terminal.
[0034] One end of resistor R555 at the HOST_SPI_POCI terminal of the master controller is connected to the second end of connector J13. The first end of connector J10 is connected to the fifth end of SPI connector J15 and the SPI protection chip U512D2+. The third end of connector J10 is connected to the SPI bus transceiver U12B2.
[0035] The bridge U11 VBUS terminal is connected to the first terminal of the USB input interface J9 and one terminal of the capacitor C603. The other terminal of the capacitor C603 is connected to the power ground. The bridge U11 USBDM terminal is connected to the second terminal of the USB input interface J9. The bridge U11 USBDP terminal is connected to the third terminal of the USB input interface J9.
[0036] The bridge U11GPIO_7 terminal is connected to one end of resistor R560 and the NOT gate buffer U8A terminal. The NOT gate buffer U8B terminal is connected to the master controller PROJ_ON terminal. The other end of resistor R560 is connected to one end of capacitor C593, the NOT gate buffer U8VCC terminal and the other end of inductor L2. The other end of capacitor C593 is connected to power ground.
[0037] The bridge U11CY_HOST_SCL terminal is connected to the level converter U7B2 terminal and one end of resistor R49. The other end of resistor R49 is connected to the other end of inductor L2. The bridge U11CY_HOST_SDA terminal is connected to the level converter U7B1 terminal and one end of resistor R48. The other end of resistor R48 is connected to the other end of inductor L2. The bridge U11CY_HOST_I2C_OE terminal is connected to the level converter U7OE terminal and one end of resistor R40. The other end of resistor R40 is connected to power ground.
[0038] In summary, the beneficial effects of this utility model are: it can stably drive the HUD to display various parameters during navigation, while also meeting the needs of ship lighting and communication, ensuring stable navigation, and improving driving efficiency and handling experience. The power adapter module can stably supply power to various electrical devices, and the lighting controller can stably drive the headlight driver for illumination. The display driver module can stably display prompts, and the HUD control and headlight control switching module can meet the main controller's needs for HUD display and headlight control under different conditions, offering diverse functions. Attached Figure Description
[0039] Figure 1 This is a system diagram of this utility model.
[0040] Figure 2 This is the circuit diagram of the synchronous step-down converter of this utility model.
[0041] Figure 3 This is the circuit diagram of a switching regulator.
[0042] Figure 4 This is a circuit diagram of a load switch and a voltage regulator.
[0043] Figure 5 This is the circuit diagram of an oscillator.
[0044] Figure 6 This is the circuit diagram of the main controller.
[0045] Figure 7 This is the circuit diagram for the lighting controller.
[0046] Figure 8 This is the circuit diagram for the HUD control and headlight control switching module.
[0047] Figure 9 This is the circuit diagram of the main controller and the lighting controller.
[0048] Figure 10 This is the circuit diagram for connecting terminal blocks J500 and J2 of the headlight driver.
[0049] Figure 11This is the circuit diagram of the main controller's configuration circuit.
[0050] Figure 12 This is the circuit diagram of the main controller and the DVI receiver.
[0051] Figure 13 It is a circuit diagram of the filter module and the memory chip.
[0052] Figure 14 This is a circuit diagram of the LDO video connection module and connector.
[0053] Figure 15 This is a circuit diagram of an SPI protection chip and an ESD protection chip.
[0054] Figure 16 This is the circuit diagram of the jumper module.
[0055] Figure 17 This is a circuit diagram of a bridge and an SPI bus transceiver.
[0056] Figure 18 This is a terminal diagram showing the connection between the main controller and the HS bus.
[0057] Figure 19 This is the circuit diagram of the first HS bus terminal block J1A and the second HS bus terminal block J1B. Detailed Implementation
[0058] The present invention will be further described below with reference to embodiments and accompanying drawings:
[0059] like Figures 1 to 19 As shown, a marine HUD circuit system includes a main controller U2. The lighting signal output terminal of the main controller U2 is connected to the lighting signal input terminal of the lighting controller U6. The drive signal output terminal of the lighting controller U6 is connected to the drive signal input terminal of the headlight driver. The display drive signal output terminal of the main controller U2 is connected to the display signal input terminal of the display driver module. The system also includes a power adapter module for supplying power to various electrical devices.
[0060] The power adapter module includes a synchronous buck converter U5. The power input terminal of the synchronous buck converter U5 is connected to one end of capacitor C31, one end of capacitor C37, one end of resistor R540, one end of capacitor C41, and one end of capacitor C23. The other end of capacitor C23 is connected to one end of inductor L5 and the ship's main information output terminal. The other end of inductor L5 is connected to one end of terminal block J1 and one end of capacitor C571. The ground terminal of the synchronous buck converter U5, the other ends of capacitors C31, C37, C41, C23, and C571 are all connected to power ground. The other end of resistor R540 is connected to the enable terminal of the synchronous buck converter U5. The VCC terminal of the synchronous buck converter U5 is connected to one end of capacitor C587, and the other end of capacitor C587 is connected to power ground.
[0061] The BOOT terminal of the synchronous buck converter U5 is connected to one end of capacitor C38. The other end of capacitor C38 is connected to the NC terminal of the synchronous buck converter U5 and one end of inductor L2. The other end of inductor L2 is connected to one end of capacitor C26, one end of capacitor C536, one end of resistor R535, one end of capacitor C19, one end of capacitor C18, one end of resistor R20, one end of capacitor C537, the VIN terminal of switching regulator U504, the VIN terminal of load switch U1, and the VIN terminal of regulator U3. The other ends of capacitor C26 and resistor R535 are both connected to the feedback terminal of synchronous buck converter U5 and one end of resistor R544. The other ends of resistor R544, capacitor C536, capacitor C19, and capacitor C18 are all connected to the power supply ground. The other end of resistor R20 is connected to the CTRL terminal of switching regulator U504 and the PG terminal of synchronous buck converter U504. The COMP terminal of switching regulator U504 is connected to one end of resistor R517. The other end of resistor R517 is connected to the other end of capacitor C519. The other end of capacitor C519 is connected to power ground.
[0062] The SW terminal of the switching regulator U504 is connected to one end of inductor L516 and the positive terminal of diode D1. The other end of inductor L516 is connected to the VIN terminal of the switching regulator U504. The negative terminal of diode D1 is connected to one end of resistor R508, one end of capacitor C2, one end of capacitor C513, one end of resistor R505, one end of capacitor C512, and the IN and IN2 terminals of linear regulator U500. The other end of resistor R508 is connected to the feedback terminal of switching regulator U504 and one end of resistor R4. The other end of resistor R4, the ground terminal of switching regulator U504, the other end of capacitor C2, the other end of capacitor C513, the other end of capacitor C512, and the ground terminal of linear regulator U500 are all connected to the power supply ground. The output and SNS terminals of the linear regulator U500 are both connected to one end of resistor R500. The other end of resistor R500 is connected to one end of capacitor C516, and the other end of capacitor C516 is connected to the power supply ground.
[0063] The ON terminal of load switch U1 is connected to the enable terminal of lighting controller U6 and one end of resistor R5. The other end of resistor R5 and the ground terminal of load switch U1 are connected to the power supply ground. The output terminal of load switch U1 outputs a 3.3V voltage, which is the 3.3V power supply terminal of the power adapter module, and is connected to one end of resistor R9. The other end of resistor R9 is connected to the QOD terminal of load switch U1, and the CT terminal of load switch U1 is connected to the power supply ground.
[0064] The first enable terminal of voltage regulator U3 is connected to the enable terminal of lighting controller U6 and one end of resistor R13. The second enable terminal of voltage regulator U3 is connected to the enable terminal of lighting controller U6 and one end of resistor R16. The other ends of resistor R13, resistor R16, and the ground terminal of voltage regulator U3 are connected to the power supply ground. The MODE / DATA terminal of voltage regulator U3 is connected to one end of resistor R21, and the other end of resistor R21 is connected to the power supply ground. The first output terminal of voltage regulator U3 is connected to one end of inductor L518. The other end of inductor L518 outputs a 1.8V voltage, which is the 1.8V power supply terminal for the power adapter module. The other end of inductor L518 is also connected to the feedback terminal of voltage regulator U3, one end of resistor R513, one end of capacitor C526, and capacitor C525. One end of resistor R513 is connected to one end of resistor R514. The other ends of resistor R514, capacitor C526, and capacitor C525 are all connected to the power supply ground. The second output of voltage regulator U3 is connected to one end of inductor L520. The other end of inductor L520 outputs 1.1V, which is the 1.1V power supply terminal for the power adapter module. The other end of inductor L520 is also connected to one end of capacitor C561, one end of resistor R24, one end of capacitor C559, and one end of capacitor C27. The other end of resistor R24 is connected to one end of resistor R32. The other ends of resistor R32, capacitor C559, and capacitor C27 are all connected to the power supply ground. The other end of capacitor C561 is connected to the ADJ2 terminal of voltage regulator U3.
[0065] The input terminal of the main controller U2PLL_REFCLK is connected to one end of capacitor C518, one end of resistor R509, and the first terminal of oscillator Y500. The output terminal of the main controller U2PLL_REFCLK is connected to the other end of resistor R509 and one end of resistor R520. One end of resistor R520 is connected to the third terminal of oscillator Y500 and one end of capacitor C521. The other ends of capacitor C521 and capacitor C518 are connected to power ground. The main controller U2VCC3IO_COSC terminal is connected to one end of ferrite bead L519 and one end of capacitor C542. The other end of ferrite bead L519 is connected to the 3.3V power supply terminal. The main controller U2GNDIOLA_COSC terminal is connected to the other end of capacitor C542 and connected to power ground. The main controller U2VCC11AD_PLLM terminal is connected to one end of capacitor C533, one end of capacitor C4, and one end of ferrite bead L512. The main controller U2GND11AD_PLLM terminal is connected to the other end of capacitor C533, the other end of capacitor C4, and one end of ferrite bead L513. The other end of ferrite bead L512 is connected to the 1.1V power supply terminal and one end of capacitor C1. The other end of capacitor C1 and the other end of ferrite bead L513 are connected to power ground. The main controller U2VCC11AD_PLLD terminal is connected to one end of capacitor C534, one end of capacitor C5, and one end of ferrite bead L515. The main controller U2GND11AD_PLLD terminal is connected to the other end of capacitor C534, the other end of capacitor C5, and one end of ferrite bead L517. The other end of ferrite bead L515 is connected to the 1.1V power supply terminal and one end of capacitor C9. The other end of capacitor C9 and the other end of ferrite bead L517 are connected to power ground.
[0066] The main controller's U2HS bus data terminal is connected to the HS bus terminal block data terminal. This embodiment also includes two HS bus terminal blocks, namely the first HS bus terminal block J1A and the second HS bus terminal block J1B, as detailed below. Figure 19 and Figure 18 As shown.
[0067] The main controller's U2PMIC_SPI_DIN terminal is connected to the lighting controller's U6SPI1_DOUT terminal. The main controller's U2PMIC_SPI_DOUT terminal is also connected to the lighting controller's U6SPI1_DIN terminal and one end of resistor R574. The other end of resistor R574 is connected to power ground. The main controller's U2PMIC_SPI_CSZ_0 terminal is connected to the lighting controller's U6SPI1_SS terminal and one end of resistor R61. The main controller's U2PMIC_SPI_CLK terminal is connected to the lighting controller's U6SPI1_CLK terminal and one end of resistor R575. The other ends of resistors R61 and R575 are connected to power ground.
[0068] The main controller's U2GPIO_00 pin is connected to one end of resistor R532. The other end of resistor R532 is connected to one end of ferrite bead FB1 and one end of resistor R512. The other end of resistor R512 is connected to power ground. The other end of ferrite bead FB1 is connected to the seventh pin of the headlight driver interface J2, which in turn connects to the headlight driver. The main controller U2PMIC_LEDSEL_0_S terminal is connected to one end of resistor R521, and the other end of resistor R521 is connected to the first terminal of the headlight driver interface J2. The main controller U2PMIC_LEDSEL_1_S terminal is connected to one end of resistor R12, and the other end of resistor R12 is connected to the second terminal of the headlight driver interface J2. The main controller U2PMIC_LEDSEL_2_S terminal is connected to one end of resistor R522, and the other end of resistor R522 is connected to the third terminal of the headlight driver interface J2. The main controller U2PMIC_LEDSEL_3_S terminal is connected to one end of resistor R11, and the other end of resistor R11 is connected to the fourth terminal of the headlight driver interface J2.
[0069] The main controller's U2GPIO_04 pin is connected to one end of resistor R54 and the lighting controller's U6D_EN pin; the other end of resistor R54 is connected to the power supply ground. The main controller's U2GPIO_03 pin is connected to one end of resistor R569 and the lighting controller's U6S_EN pin; the other end of resistor R569 is connected to the power supply ground. The main controller's U2PMIC_AD3_POCI pin is connected to the lighting controller's U6AD3_MISO pin. The main controller's U2PMIC_AD3_PICO pin is connected to one end of resistor R41 and the lighting controller's U6AD3_MOSI pin; the other end of resistor R41 is connected to the power supply ground. The main controller's U2PMIC_AD3_SEQ_CLK pin is connected to one end of resistor R41 and the lighting controller's U6SEQ_CLK pin; the other end of resistor R41 is connected to the power supply ground.
[0070] The main controller U2PMIC_WD1_S terminal is connected to one end of resistor R546, and the other end of resistor R546 is connected to the lighting controller U6WD1 terminal. The main controller U2PMIC_SEQ_STRT_S terminal is connected to one end of resistor R19, and the other end of resistor R19 is connected to the lighting controller U6WD2 terminal. The main controller U2PWM1_COMPOUT_S terminal is connected to one end of resistor R10, and the other end of resistor R10 is connected to one end of ferrite bead FB2. The other end of ferrite bead FB2 is connected to the eighth terminal of the headlight driver interface J2. The main controller U2PMIC_INTZ terminal is connected to one end of resistor R561 and the lighting controller U6INT terminal. The other end of resistor R561 is connected to the 3.3V power supply terminal. The main controller U2PMIC_PARKZ terminal is connected to one end of resistor R559 and the lighting controller U6PARK terminal. The other end of resistor R559 is connected to the power supply ground. The main controller U2RESETZ terminal is connected to one end of resistor R50 and the reset terminal of lighting controller U6, and the other end of resistor R50 is connected to the power supply ground.
[0071] The lighting controller U6R_EN terminal is connected to one end of the ferrite bead L506, and the other end of the ferrite bead L506 is connected to the tenth terminal of the terminal block J500. The headlight driver is connected through the terminal block J500. The lighting controller U6G_EN terminal is connected to one end of the ferrite bead L505, and the other end of the ferrite bead L505 is connected to the eleventh terminal of the terminal block J500. The lighting controller U6B_EN terminal is connected to one end of the ferrite bead L504, and the other end of the ferrite bead L504 is connected to the twelfth terminal of the terminal block J500. The lighting controller U6PMIC_SEN1 terminal is connected to one end of the ferrite bead L509, and the other end of the ferrite bead L509 is connected to the fifth terminal of the terminal block J500. The lighting controller U6PMIC_SEN2 terminal is connected to one end of the ferrite bead L507, and the other end of the ferrite bead L507 is connected to the eighth terminal of the terminal block J500.
[0072] The lighting controller U6PMIC_CMODE terminal connects to one end of ferrite bead L508, and the other end of ferrite bead L508 connects to terminal 7 of terminal block J500. The lighting controller U6PMIC_LM3409_DRVEN terminal connects to one end of ferrite bead L510, and the other end of ferrite bead L510 connects to terminal 3 of terminal block J500. The lighting controller U6PMIC_LS_SENSE_P terminal connects to one end of ferrite bead L502, and the other end of ferrite bead L502 connects to terminal 16 of terminal block J500. The lighting controller U6P... The MIC_LS_SENSE_N terminal is connected to one end of the ferrite bead L501, and the other end of the ferrite bead L501 is connected to the seventeenth terminal of the terminal block J500. The lighting controller U6PMIC_LM3409_SYNC terminal is connected to one end of the ferrite bead L511, and the other end of the ferrite bead L511 is connected to the first terminal of the terminal block J500. The lighting controller U6PMIC_LM3409_IADJ terminal is connected to one end of the ferrite bead L500, and the other end of the ferrite bead L500 is connected to the nineteenth terminal of the terminal block J500.
[0073] It also includes a HUD control and headlight control switching module, comprising signal switch U10. Terminal A of signal switch U10 is connected to the other end of resistor R523. The low-level enable terminal of signal switch U10 is connected to the main controller U2GPIO_9 terminal. Terminal B of signal switch U10 is connected to the lighting controller U6PMIC_LM3409_DRVEN terminal. The VCC terminal of signal switch U10 is connected to the 3.3V power supply. It also includes signal switch U9. Terminal A of signal switch U9 is connected to the lighting controller U6PMIC_COMPOUT terminal. The low-level enable terminal of signal switch U9 is connected to the main controller U2GPIO_9 terminal. Terminal B of signal switch U9 is connected to the main controller U2PWM1_COMPOUT_S terminal. The VCC terminal of signal switch U9 is connected to the 3.3V power supply.
[0074] It also includes a NOT gate buffer U13. The VCC terminal of the NOT gate buffer U13 is connected to one end of resistor R570, the 3.3V power supply terminal, and one end of capacitor C59. The other end of resistor R570 and the A terminal of the NOT gate buffer U13 are both connected to the main controller U2GPIO_9 terminal. The other end of capacitor C59 is connected to the power supply ground. The Y terminal of the NOT gate buffer U13 is connected to the first input terminal of each group of AND gates of AND gate chip U14. The other input terminal of the first group of AND gate chip U14 is connected to the other end of resistor R521. The first output terminal of AND gate chip U14 is connected to the lighting controller U6HUD_LEDSEL_0 terminal. The other input terminal of the second group of AND gate chip U14 is connected to the other end of resistor R521. The second output terminal of AND gate chip U14 is connected to the lighting controller U6HUD_LEDSEL_1 terminal. The other input terminal of the third group of AND gate chip U14 is connected to the other end of resistor R521. The third output terminal of AND gate chip U14 is connected to the lighting controller U6HUD_LEDSEL_2 terminal. The other input terminal of the fourth group of AND gate chip U14 is connected to the other end of resistor R521, and the output terminal of the fourth group of AND gate chip U14 is connected to the terminal of lighting controller U6HUD_LEDSEL_3.
[0075] The main controller U2JTAGRSTZ terminal is connected to one end of resistor R531, and the other end of resistor R531 is connected to power ground. The main controller U2GPIO_11 is connected to one end of resistor R18, and the other end of resistor R18 is connected to power ground. The main controller U2GPIO_12 is connected to one end of resistor R533, and the other end of resistor R533 is connected to power ground. The main controller U2GPIO_10 is connected to one end of resistor R536, and the other end of resistor R536 is connected to power ground. The main controller U2GPIO_13 is connected to one end of resistor R22, and the other end of resistor R22 is connected to power ground. The main controller U2GPIO_22 is connected to one end of resistor R548, and the other end of resistor R548 is connected to power ground. The main controller U2GPIO_23 is connected to one end of resistor R547, and the other end of resistor R547 is connected to power ground. The main controller U2GPIO_24 is connected to one end of resistor R542, and the other end of resistor R542 is connected to power ground. The main controller U2GPIO_25 is connected to one end of resistor R550, and the other end of resistor R550 is connected to power ground.
[0076] The main controller U2TESTPT0 terminal is connected to one end of resistor R549, and the other end of resistor R549 is connected to the digital bus switch U510B terminal. The digital bus switch U510A terminal and VCC terminal are both connected to the 3.3V power supply terminal. The low-level enable terminal of the digital bus switch U510 is connected to one end of resistor R571, and the other end of resistor R571 is connected to the 3.3V power supply terminal. The ground terminal of the digital bus switch U510 is connected to the power supply ground.
[0077] The main controller U2CHKSUM_SEL terminal is connected to one end of resistor R552. The other end of resistor R552 is connected to the first terminal of DIP switch SW1, and the second terminal of DIP switch SW1 is connected to the 3.3V power supply. The main controller U2HOST_IF_SEL terminal is connected to one end of resistor R37. The other end of resistor R37 is connected to the first terminal of DIP switch SW2, and the second terminal of DIP switch SW2 is connected to the 3.3V power supply. The main controller U2HOST_SPI_MODE terminal is connected to one end of resistor R38. The other end of resistor R38 is connected to the first terminal of DIP switch SW3, and the second terminal of DIP switch SW3 is connected to the 3.3V power supply. The main controller U2TESTPT5 terminal is connected to one end of resistor R556. The other end of resistor R556 is connected to the first terminal of DIP switch SW4, and the second terminal of DIP switch SW4 is connected to the 3.3V power supply.
[0078] The display driver module includes a DVI receiver U501. The parallel data bus signal terminal of the main controller U2 is connected to the parallel data bus signal terminal of the DVI receiver U501. The differential signal terminal of the DVI receiver U501 is connected to the differential signal terminal of the filter module. The filtered signal output terminal of the filter module is connected to the filtered signal input terminal of the HDMI input interface J4.
[0079] Specifically: the DVI receiver U501OCK_INV terminal is connected to one end of resistor R1, and the other end of resistor R1 is connected to the 3.3V power supply terminal; the DVI receiver U501STAGZ terminal is connected to one end of resistor R502, and the other end of resistor R502 is connected to the 3.3V power supply terminal; the DVI receiver U501ST terminal is connected to one end of resistor R503, and the other end of resistor R503 is connected to the 3.3V power supply terminal; the DVI receiver U501PDZ terminal is connected to one end of resistor R501, and the other end of resistor R501 is connected to the 3.3V power supply terminal.
[0080] The first signal terminal of the parallel data bus of the master controller U2 is connected to the ninth terminal of the resistor array R3, and the eighth terminal of the resistor array R3 is connected to the first signal terminal of the parallel data bus of the DVI receiver U501. The second signal terminal of the parallel data bus of the master controller U2 is connected to the tenth terminal of the resistor array R3, and the seventh terminal of the resistor array R3 is connected to the second signal terminal of the parallel data bus of the DVI receiver U501. The third signal terminal of the parallel data bus of the master controller U2 is connected to the eleventh terminal of the resistor array R3, and the sixth terminal of the resistor array R3 is connected to the third signal terminal of the parallel data bus of the DVI receiver U501. The fourth signal terminal of the parallel data bus of the master controller U2 is connected to the twelfth terminal of the resistor array R3, and the fifth terminal of the resistor array R3 is connected to the fourth signal terminal of the parallel data bus of the DVI receiver U501. The fifth signal terminal of the parallel data bus of the master controller U2 is connected to the thirteenth terminal of the resistor array R3, and the fourth terminal of the resistor array R3 is connected to the fifth signal terminal of the parallel data bus of the DVI receiver U501. The sixth signal terminal of the parallel data bus of the main controller U2 is connected to the fourteenth terminal of the resistor array R3, and the third terminal of the resistor array R3 is connected to the sixth signal terminal of the parallel data bus of the DVI receiver U501. The seventh signal terminal of the parallel data bus of the main controller U2 is connected to the fifteenth terminal of the resistor array R3, and the second terminal of the resistor array R3 is connected to the seventh signal terminal of the parallel data bus of the DVI receiver U501. The eighth signal terminal of the parallel data bus of the main controller U2 is connected to the sixteenth terminal of the resistor array R3, and the first terminal of the resistor array R3 is connected to the eighth signal terminal of the parallel data bus of the DVI receiver U501.
[0081] The ninth signal terminal of the parallel data bus of the main controller U2 is connected to the ninth terminal of the resistor array RN2, and the first terminal of the resistor array RN2 is connected to the ninth signal terminal of the parallel data bus of the DVI receiver U501. The tenth signal terminal of the parallel data bus of the main controller U2 is connected to the tenth terminal of the resistor array RN2, and the seventh terminal of the resistor array RN2 is connected to the tenth signal terminal of the parallel data bus of the DVI receiver U501. The eleventh signal terminal of the parallel data bus of the main controller U2 is connected to the eleventh terminal of the resistor array RN2, and the sixth terminal of the resistor array RN2 is connected to the eleventh signal terminal of the parallel data bus of the DVI receiver U501. The twelfth signal terminal of the parallel data bus of the main controller U2 is connected to the twelfth terminal of the resistor array RN2, and the fifth terminal of the resistor array RN2 is connected to the twelfth signal terminal of the parallel data bus of the DVI receiver U501. The thirteenth signal terminal of the parallel data bus of the main controller U2 is connected to the thirteenth terminal of the resistor array RN2, and the fourth terminal of the resistor array RN2 is connected to the thirteenth signal terminal of the parallel data bus of the DVI receiver U501. The fourteenth signal terminal of the parallel data bus of the master controller U2 is connected to the fourteenth terminal of the resistor array RN2, and the third terminal of the resistor array RN2 is connected to the fourteenth signal terminal of the parallel data bus of the DVI receiver U501. The fifteenth signal terminal of the parallel data bus of the master controller U2 is connected to the fifteenth terminal of the resistor array RN2, and the second terminal of the resistor array RN2 is connected to the fifteenth signal terminal of the parallel data bus of the DVI receiver U501. The sixteenth signal terminal of the parallel data bus of the master controller U2 is connected to the sixteenth terminal of the resistor array RN2, and the first terminal of the resistor array RN2 is connected to the sixteenth signal terminal of the parallel data bus of the DVI receiver U501.
[0082] The seventeenth signal terminal of the parallel data bus of the master controller U2 is connected to the ninth terminal of the resistor array RN1, and the first terminal of the resistor array RN1 is connected to the seventeenth signal terminal of the parallel data bus of the DVI receiver U501. The eighteenth signal terminal of the parallel data bus of the master controller U2 is connected to the tenth terminal of the resistor array RN1, and the seventh terminal of the resistor array RN1 is connected to the eighteenth signal terminal of the parallel data bus of the DVI receiver U501. The nineteenth signal terminal of the parallel data bus of the master controller U2 is connected to the eleventh terminal of the resistor array RN1, and the sixth terminal of the resistor array RN1 is connected to the nineteenth signal terminal of the parallel data bus of the DVI receiver U501. The twentieth signal terminal of the parallel data bus of the master controller U2 is connected to the twelfth terminal of the resistor array RN1, and the fifth terminal of the resistor array RN1 is connected to the twentieth signal terminal of the parallel data bus of the DVI receiver U501. The twenty-first signal terminal of the parallel data bus of the master controller U2 is connected to the thirteenth terminal of the resistor array RN1, and the fourth terminal of the resistor array RN1 is connected to the twenty-first signal terminal of the parallel data bus of the DVI receiver U501. The 22nd signal terminal of the parallel data bus of the main controller U2 is connected to the 14th terminal of the resistor array RN1, and the 3rd terminal of the resistor array RN1 is connected to the 22nd signal terminal of the parallel data bus of the DVI receiver U501. The 23rd signal terminal of the parallel data bus of the main controller U2 is connected to the 15th terminal of the resistor array RN1, and the 2nd terminal of the resistor array RN1 is connected to the 23rd signal terminal of the parallel data bus of the DVI receiver U501. The 24th signal terminal of the parallel data bus of the main controller U2 is connected to the 16th terminal of the resistor array RN1, and the 1st terminal of the resistor array RN1 is connected to the 24th signal terminal of the parallel data bus of the DVI receiver U501.
[0083] The filtering module includes four modules: the first filtering module U505B, the second filtering module U505A, the third filtering module U506B, and the fourth filtering module U506A. The positive terminal of the third channel of the differential signal of the DVI receiver U501 is connected to the AC1 terminal of the fourth filtering module U506A, and the negative terminal of the third channel of the differential signal of the DVI receiver U501 is connected to the AC2 terminal of the fourth filtering module U506A. The positive terminal of the third channel of the filtered signal of the fourth filtering module U506A is connected to the J4TMDS_data_2+ terminal of the HDMI input interface, and the negative terminal of the third channel of the filtered signal of the fourth filtering module U506A is connected to the J4TMDS_data_2- terminal of the HDMI input interface.
[0084] The positive terminal of the second differential signal channel of the DVI receiver U501 is connected to the terminal of the third filter module U506BC1, and the negative terminal of the second differential signal channel of the DVI receiver U501 is connected to the terminal of the third filter module U506BC2. The positive terminal of the second filter signal channel of the third filter module U506B is connected to the terminal of the HDMI input interface J4TMDS_data_1+, and the negative terminal of the second filter signal channel of the third filter module U506B is connected to the terminal of the HDMI input interface J4TMDS_data_1-.
[0085] The positive terminal of the first differential signal channel of the DVI receiver U501 is connected to the terminal of the second filter module U505AC1, and the negative terminal of the first differential signal channel of the DVI receiver U501 is connected to the terminal of the second filter module U505AC2. The positive terminal of the first filtered signal channel of the second filter module U505A is connected to the terminal of the HDMI input interface J4TMDS_data_1+, and the negative terminal of the first filtered signal channel of the second filter module U505A is connected to the terminal of the HDMI input interface J4TMDS_data_1-.
[0086] The positive terminal of the differential signal clock channel of the DVI receiver U501 is connected to the first filter module U505BC1, and the negative terminal of the differential signal clock channel of the DVI receiver U501 is connected to the first filter module U505BC2. The positive terminal of the filter signal clock channel of the first filter module U505B is connected to the HDMI input interface J4TMDS_clock+, and the negative terminal of the filter signal clock channel of the first filter module U505B is connected to the HDMI input interface J4TMDS_clock+.
[0087] The HDMI input interface J4 DDC_data terminal is connected to the second input terminal of the ESD protection module U502, one end of resistor R507, and the SDA terminal of the storage module U503. The other end of resistor R507 is connected to the HDMI input interface J4+5V_power terminal. The HDMI input interface J4DDC_clock terminal is connected to the second input terminal of the ESD protection module U502, one end of resistor R518, and the SCL terminal of the storage module U503. The other end of resistor R518 and the VCC terminal of the storage module U503 are connected to the HDMI input interface J4+5V_power terminal. The third terminal of the ESD protection module U502 is connected to the power ground.
[0088] The main controller U2HOST_IRQ_S terminal is connected to one end of resistor R39. The other end of resistor R39 is connected to the NOT gate buffer U15A terminal and the SPI protection chip U17D1+. The NOT gate buffer U15VCC terminal is connected to the 3.3V power supply terminal. The NOT gate buffer U15Y terminal is connected to one end of resistor R572 and the bridge U11GPIO_16 terminal. The other end of resistor R572 is connected to the other end of inductor L2. The main controller U2HOST_I2C_SDA terminal is connected to the level converter U7A1 terminal and the first input terminal of the ESD protection chip U16. The main controller U2HOST_I2C_SCL terminal is connected to the level converter U7A2 terminal and the second input terminal of the ESD protection chip U16. The ground terminal of the ESD protection chip U16 is connected to the power supply ground.
[0089] It also includes a jumper module, which is used to switch between Cypress and SPI bus. The jumper module includes a connection between the master controller U2HOST_SPI_CLK terminal and the second terminal of connector J10, a connection between the first terminal of connector J10 and one end of resistor R582, a connection between the other end of resistor R582 and the seventh terminal of SPI connector J15 and the SPI protection chip U512D1+, a connection between the third terminal of connector J10 and one end of resistor R567, and a connection between the other end of resistor R567 and the SPI bus transceiver U12B3 terminal.
[0090] The main controller U2HOST_SPI_CSZ terminal is connected to the second terminal of connector J12. The first terminal of connector J12 is connected to one end of resistor R581. The other end of resistor R581 is connected to the ninth terminal of SPI connector J15 and the D2- terminal of SPI protection chip U512. The third terminal of connector J12 is connected to one end of resistor R564. The other end of resistor R564 is connected to the B4 terminal of SPI bus transceiver U12.
[0091] The main controller U2HOST_SPI_PICO terminal is connected to the second terminal of connector J11. The first terminal of connector J11 is connected to one end of resistor R583 and the SPI protection chip U512D1- terminal. The other end of resistor R583 is connected to the eighth terminal of SPI connector J15. The third terminal of connector J11 is connected to one end of resistor R568. The other end of resistor R568 is connected to the SPI bus transceiver U12B1 terminal.
[0092] One end of resistor R555 at the U2HOST_SPI_POCI terminal of the master controller is connected to the second terminal of connector J13. The other end of resistor R555 is connected to the first terminal of connector J10, which is connected to the fifth terminal of SPI connector J15 and the terminal of SPI protection chip U512D2+. The third terminal of connector J10 is connected to the terminal of SPI bus transceiver U12B2.
[0093] The VBUS terminal of bridge U11 is connected to the first terminal of USB input interface J9 and one terminal of capacitor C603. The other terminal of capacitor C603 is connected to the power ground. The USBDM terminal of bridge U11 is connected to the second terminal of USB input interface J9, and the USBDP terminal of bridge U11 is connected to the third terminal of USB input interface J9.
[0094] The bridge U11GPIO_7 terminal is connected to one end of resistor R560 and the NOT gate buffer U8A terminal. The NOT gate buffer U8B terminal is connected to the master controller U2PROJ_ON terminal. The other end of resistor R560 is connected to one end of capacitor C593, the NOT gate buffer U8VCC terminal and the other end of inductor L2. The other end of capacitor C593 is connected to power ground.
[0095] The bridge U11CY_HOST_SCL terminal is connected to the level converter U7B2 terminal and one end of resistor R49. The other end of resistor R49 is connected to the other end of inductor L2. The bridge U11CY_HOST_SDA terminal is connected to the level converter U7B1 terminal and one end of resistor R48. The other end of resistor R48 is connected to the other end of inductor L2. The bridge U11CY_HOST_I2C_OE terminal is connected to the level converter U7OE terminal and one end of resistor R40. The other end of resistor R40 is connected to power ground.
Claims
1. A marine HUD circuit system, characterized in that: The system includes a main controller (U2), whose lighting signal output terminal is connected to the lighting signal input terminal of a lighting controller (U6), whose drive signal output terminal is connected to the drive signal input terminal of a headlight driver, whose display drive signal output terminal is connected to the display signal input terminal of a display driver module, and also includes a power adapter module for supplying power to various electrical devices.
2. The marine HUD circuit system according to claim 1, characterized in that: The power adapter module includes a synchronous buck converter (U5). The power input terminal of the synchronous buck converter (U5) is connected to one end of capacitor C31, one end of capacitor C37, one end of resistor R540, one end of capacitor C41, and one end of capacitor C23. The other end of capacitor C23 is connected to one end of inductor L5 and the main information output terminal of the ship. The other end of inductor L5 is connected to one end of terminal block J1 and one end of capacitor C571. The ground terminal of the synchronous buck converter (U5), the other end of capacitor C31, capacitor C37, capacitor C41, capacitor C23, and capacitor C571 are all connected to the power ground. The other end of resistor R540 is connected to the enable terminal of the synchronous buck converter (U5). The VCC terminal of the synchronous buck converter (U5) is connected to one end of capacitor C587, and the other end of capacitor C587 is connected to the power ground. The BOOT terminal of the synchronous buck converter (U5) is connected to one end of capacitor C38. The other end of capacitor C38 is connected to the NC terminal of the synchronous buck converter (U5) and one end of inductor L2. The other end of inductor L2 is connected to one end of capacitor C26, one end of capacitor C536, one end of resistor R535, one end of capacitor C19, one end of capacitor C18, one end of resistor R20, one end of capacitor C537, the VIN terminal of switching regulator (U504), the VIN terminal of load switch (U1), and the VIN terminal of regulator (U3). The other end of capacitor C26 is connected to resistor R... The other end of 535 is connected to the feedback terminal of the synchronous buck converter (U5) and one end of resistor R544. The other ends of resistor R544, capacitor C536, capacitor C19, and capacitor C18 are all connected to power ground. The other end of resistor R20 is connected to the CTRL terminal of the switching regulator (U504) and the PG terminal of the synchronous buck converter (U5). The COMP terminal of the switching regulator (U504) is connected to one end of resistor R517. The other end of resistor R517 is connected to the other end of capacitor C519. The other end of capacitor C519 is connected to power ground. The SW terminal of the switching regulator (U504) is connected to one end of inductor L516 and the positive terminal of diode D1. The other end of inductor L516 is connected to the VIN terminal of the switching regulator (U504). The negative terminal of diode D1 is connected to one end of resistor R508, one end of capacitor C2, one end of capacitor C513, one end of resistor R505, one end of capacitor C512, and the IN and IN2 terminals of the linear regulator (U500). The other end of resistor R508 is connected to the switch... The feedback terminal of the voltage regulator (U504) and one end of the resistor R4, the other end of the resistor R4, the ground terminal of the switching regulator (U504), the other end of the capacitor C2, the other end of the capacitor C513, the other end of the capacitor C512, and the ground terminal of the linear regulator (U500) are all connected to the power supply ground; the output terminal and the SNS terminal of the linear regulator (U500) are both connected to one end of the resistor R500, the other end of the resistor R500 is connected to one end of the capacitor C516, and the other end of the capacitor C516 is connected to the power supply ground.
3. The marine HUD circuit system according to claim 2, characterized in that: The ON terminal of the load switch (U1) is connected to the enable terminal of the lighting controller (U6) and one end of the resistor R5. The other end of the resistor R5 and the ground terminal of the load switch (U1) are connected to the power supply ground. The output terminal of the load switch (U1) outputs a 3.3V voltage, which is the 3.3V power supply terminal for the power adapter module, and is connected to one end of the resistor R9. The other end of the resistor R9 is connected to the QOD terminal of the load switch (U1). The CT terminal of the load switch (U1) is connected to the power supply ground. The first enable terminal of the voltage regulator (U3) is connected to the enable terminal of the lighting controller (U6) and one end of resistor R13. The second enable terminal of the voltage regulator (U3) is connected to the enable terminal of the lighting controller (U6) and one end of resistor R16. The other ends of resistor R13, the other ends of resistor R16, and the ground terminal of the voltage regulator (U3) are connected to the power supply ground. The MODE / DATA terminal of the voltage regulator (U3) is connected to one end of resistor R21, and the other end of resistor R21 is connected to the power supply ground. The first output terminal of the voltage regulator (U3) is connected to one end of inductor L518. The other end of inductor L518 outputs a 1.8V voltage, which is the 1.8V power supply terminal for the power adapter module. The other end of inductor L518 is also connected to the feedback terminal of the voltage regulator (U3), one end of resistor R513, and one end of capacitor C526. One end of capacitor C525 is connected to the other end of resistor R513, which is connected to one end of resistor R514. The other ends of resistor R514, capacitor C526, and capacitor C525 are all connected to the power supply ground. The second output terminal of the voltage regulator (U3) is connected to one end of inductor L520. The other end of inductor L520 outputs a 1.1V voltage, which is the 1.1V power supply terminal for the power adapter module. The other end of inductor L520 is also connected to one end of capacitor C561, one end of resistor R24, one end of capacitor C559, and one end of capacitor C27. The other end of resistor R24 is connected to one end of resistor R32. The other ends of resistor R32, capacitor C559, and capacitor C27 are all connected to the power supply ground. The other end of capacitor C561 is connected to the ADJ2 terminal of voltage regulator (U3).
4. The marine HUD circuit system according to claim 1, characterized in that: The input terminal of the main controller (U2) PLL_REFCLK is connected to one end of capacitor C518, one end of resistor R509, and the first terminal of oscillator Y500. The output terminal of the main controller (U2) PLL_REFCLK is connected to the other end of resistor R509 and one end of resistor R520. One end of resistor R520 is connected to the third terminal of oscillator Y500 and one end of capacitor C521. The other ends of capacitor C521 and capacitor C518 are connected to the power supply ground. The VCC3IO_COSC terminal of the main controller (U2) is connected to one end of ferrite bead L519 and one end of capacitor C542. The other end of ferrite bead L519 is connected to the 3.3V power supply terminal. The GNDIOLA_COSC terminal of the main controller (U2) is connected to the other end of capacitor C542 and connected to the power supply ground. The VCC11AD_PLLM terminal of the main controller (U2) is connected to... One end of capacitor C533, one end of capacitor C4, and one end of ferrite bead L512 are connected to the other end of capacitor C533, the other end of capacitor C4, and one end of ferrite bead L513. The other end of ferrite bead L512 is connected to the 1.1V power supply terminal and one end of capacitor C1. The other end of capacitor C1 and the other end of ferrite bead L513 are connected to power ground. The VCC11AD_PLLD terminal of the main controller (U2) is connected to one end of capacitor C534, one end of capacitor C5, and one end of ferrite bead L515. The GND11AD_PLLD terminal of the main controller (U2) is connected to the other end of capacitor C534, the other end of capacitor C5, and one end of ferrite bead L517. The other end of ferrite bead L515 is connected to the 1.1V power supply terminal and one end of capacitor C9. The other end of capacitor C9 and the other end of ferrite bead L517 are connected to power ground. The PMIC_SPI_DIN terminal of the main controller (U2) is connected to the SPI1_DOUT terminal of the lighting controller (U6). The PMIC_SPI_DOUT terminal of the main controller (U2) is connected to the SPI1_DIN terminal of the lighting controller (U6) and one end of resistor R574. The other end of resistor R574 is connected to power ground. The PMIC_SPI_CSZ_0 terminal of the main controller (U2) is connected to the SPI1_SS terminal of the lighting controller (U6) and one end of resistor R61. The PMIC_SPI_CLK terminal of the main controller (U2) is connected to the SPI1_CLK terminal of the lighting controller (U6) and one end of resistor R575. The other ends of resistor R61 and resistor R575 are connected to power ground. The main controller (U2) GPIO_00 terminal is connected to one end of resistor R532. The other end of resistor R532 is connected to one end of ferrite bead FB1 and one end of resistor R512. The other end of resistor R512 is connected to power ground. The other end of ferrite bead FB1 is connected to the seventh terminal of the headlight driver interface J2, and is connected to the headlight driver through the headlight driver interface J2. The main controller (U2) PMIC_LEDSEL_0_S terminal is connected to one end of resistor R521. The other end of resistor R521 is connected to the first terminal of the headlight driver interface J2. The main controller (U2) PMIC_LEDSEL_1_S terminal is connected to one end of resistor R12, and the other end of resistor R12 is connected to the second terminal of the headlight driver interface J2. The main controller (U2) PMIC_LEDSEL_2_S terminal is connected to one end of resistor R522, and the other end of resistor R522 is connected to the third terminal of the headlight driver interface J2. The main controller (U2) PMIC_LEDSEL_3_S terminal is connected to one end of resistor R11, and the other end of resistor R11 is connected to the fourth terminal of the headlight driver interface J2. The main controller (U2) GPIO_04 terminal is connected to one end of resistor R54 and the lighting controller (U6) D_EN terminal, with the other end of resistor R54 connected to the power supply ground; the main controller (U2) GPIO_03 terminal is connected to one end of resistor R569 and the lighting controller (U6) S_EN terminal, with the other end of resistor R569 connected to the power supply ground; the main controller (U2) PMIC_AD3_POCI terminal is connected to the lighting controller (U6) AD3_MISO terminal; the main controller (U2) PMIC_AD3_PICO terminal is connected to one end of resistor R41 and the lighting controller (U6) AD3_MOSI terminal, with the other end of resistor R41 connected to the power supply ground; the main controller (U2) PMIC_AD3_SEQ_CLK terminal is connected to one end of resistor R41 and the lighting controller (U6) SEQ_CLK terminal, with the other end of resistor R41 connected to the power supply ground; The main controller (U2) PMIC_WD1_S terminal is connected to one end of resistor R546, and the other end of resistor R546 is connected to the WD1 terminal of the lighting controller (U6). The main controller (U2) PMIC_SEQ_STRT_S terminal is connected to one end of resistor R19, and the other end of resistor R19 is connected to the WD2 terminal of the lighting controller (U6). The main controller (U2) PWM1_COMPOUT_S terminal is connected to one end of resistor R10, and the other end of resistor R10 is connected to one end of ferrite bead FB2. The other end of ferrite bead FB2 is connected to the headlight driver interface J.
2. The eighth terminal: the PMIC_INTZ terminal of the main controller (U2) is connected to one end of resistor R561 and the INT terminal of the lighting controller (U6). The other end of one end of resistor R561 is connected to the 3.3V power supply terminal. The PMIC_PARKZ terminal of the main controller (U2) is connected to one end of resistor R559 and the PARK terminal of the lighting controller (U6). The other end of resistor R559 is connected to the power supply ground. The RESETZ terminal of the main controller (U2) is connected to one end of resistor R50 and the reset terminal of the lighting controller (U6). The other end of resistor R50 is connected to the power supply ground. The lighting controller (U6) R_EN terminal is connected to one end of the ferrite bead L506, and the other end of the ferrite bead L506 is connected to the tenth terminal of the terminal block J500. The headlight driver is connected through the terminal block J500. The lighting controller (U6) G_EN terminal is connected to one end of the ferrite bead L505, and the other end of the ferrite bead L505 is connected to the eleventh terminal of the terminal block J500. The lighting controller (U6) B_EN terminal is connected to one end of the ferrite bead L504, and the other end of the ferrite bead L504 is connected to the twelfth terminal of the terminal block J500. The lighting controller (U6) PMIC_SEN1 terminal is connected to one end of the ferrite bead L509, and the other end of the ferrite bead L509 is connected to the fifth terminal of the terminal block J500. The lighting controller (U6) PMIC_SEN2 terminal is connected to one end of the ferrite bead L507, and the other end of the ferrite bead L507 is connected to the eighth terminal of the terminal block J500. The lighting controller (U6) PMIC_CMODE terminal is connected to one end of ferrite bead L508, and the other end of ferrite bead L508 is connected to the seventh terminal of terminal block J500. The lighting controller (U6) PMIC_LM3409_DRVEN terminal is connected to one end of ferrite bead L510, and the other end of ferrite bead L510 is connected to the third terminal of terminal block J500. The lighting controller (U6) PMIC_LS_SENSE_P terminal is connected to one end of ferrite bead L502, and the other end of ferrite bead L502 is connected to the sixteenth terminal of terminal block J500. The lighting controller (U6) P... The MIC_LS_SENSE_N terminal is connected to one end of the ferrite bead L501, and the other end of the ferrite bead L501 is connected to the seventeenth terminal of the terminal block J500. The lighting controller (U6) PMIC_LM3409_SYNC terminal is connected to one end of the ferrite bead L511, and the other end of the ferrite bead L511 is connected to the first terminal of the terminal block J500. The lighting controller (U6) PMIC_LM3409_IADJ terminal is connected to one end of the ferrite bead L500, and the other end of the ferrite bead L500 is connected to the nineteenth terminal of the terminal block J500.
5. The marine HUD circuit system according to claim 1, characterized in that: It also includes a HUD control and headlight control switching module, including a signal switch U10. The A terminal of the signal switch U10 is connected to the other end of the resistor R523. The low-level enable terminal of the signal switch U10 is connected to the GPIO_9 terminal of the main controller (U2). The B terminal of the signal switch U10 is connected to the PMIC_LM3409_DRVEN terminal of the lighting controller (U6). The VCC terminal of the signal switch U10 is connected to the 3.3V power supply terminal. It also includes a signal switch U9. The A terminal of the signal switch U9 is connected to the PMIC_COMPOUT terminal of the lighting controller (U6). The low-level enable terminal of the signal switch U9 is connected to the GPIO_9 terminal of the main controller (U2). The B terminal of the signal switch U9 is connected to the PWM1_COMPOUT_S terminal of the main controller (U2). The VCC terminal of the signal switch U9 is connected to the 3.3V power supply terminal. It also includes a NOT gate buffer U13, whose VCC terminal is connected to one end of resistor R570, the 3.3V power supply terminal, and one end of capacitor C59. The other end of resistor R570 and the A terminal of NOT gate buffer U13 are both connected to the GPIO_9 terminal of the main controller (U2), and the other end of capacitor C59 is connected to the power supply ground. The Y terminal of NOT gate buffer U13 is connected to the first input terminal of each group of AND gates of AND gate chip U14. The other input terminal of the first group of AND gates of AND gate chip U14 is connected to the other end of resistor R521. The first group of output terminals of AND gate chip U14 is connected to the HUD_LEDSEL of the lighting controller (U6). The second input terminal of the AND gate chip U14 is connected to the other end of the resistor R521, and the output terminal of the second group of the AND gate chip U14 is connected to the HUD_LEDSEL_1 terminal of the lighting controller (U6); the third input terminal of the AND gate chip U14 is connected to the other end of the resistor R521, and the output terminal of the third group of the AND gate chip U14 is connected to the HUD_LEDSEL_2 terminal of the lighting controller (U6); the fourth input terminal of the AND gate chip U14 is connected to the other end of the resistor R521, and the output terminal of the fourth group of the AND gate chip U14 is connected to the HUD_LEDSEL_3 terminal of the lighting controller (U6). The JTAGRSTZ terminal of the main controller (U2) is connected to one end of resistor R531, and the other end of resistor R531 is connected to power ground; the GPIO_11 terminal of the main controller (U2) is connected to one end of resistor R18, and the other end of resistor R18 is connected to power ground; the GPIO_12 terminal of the main controller (U2) is connected to one end of resistor R533, and the other end of resistor R533 is connected to power ground; the GPIO_10 terminal of the main controller (U2) is connected to one end of resistor R536, and the other end of resistor R536 is connected to power ground; the GPIO_13 terminal of the main controller (U2) is connected to resistor R... One end of resistor R22 is connected to the power supply ground. The other end of resistor R22 is connected to the main controller (U2) GPIO_22. The other end of resistor R548 is connected to the power supply ground. The other end of resistor R548 is connected to the main controller (U2) GPIO_23. The other end of resistor R547 is connected to the power supply ground. The other end of resistor R547 is connected to the power supply ground. The other end of resistor R542 is connected to the main controller (U2) GPIO_24. The other end of resistor R542 is connected to the power supply ground. The other end of resistor R550 is connected to the main controller (U2) GPIO_25. The main controller (U2) TESTPT0 terminal is connected to one end of resistor R549, and the other end of resistor R549 is connected to the digital bus switch U510B terminal. The digital bus switch U510A terminal and VCC terminal are both connected to the 3.3V power supply terminal. The low-level enable terminal of the digital bus switch U510 is connected to one end of resistor R571, and the other end of resistor R571 is connected to the 3.3V power supply terminal. The ground terminal of the digital bus switch U510 is connected to the power supply ground. The main controller (U2) CHKSUM_SEL terminal is connected to one end of resistor R552, the other end of resistor R552 is connected to the first terminal of DIP switch SW1, and the second terminal of DIP switch SW1 is connected to the 3.3V power supply terminal; the main controller (U2) HOST_IF_SEL terminal is connected to one end of resistor R37, the other end of resistor R37 is connected to the first terminal of DIP switch SW2, and the second terminal of DIP switch SW2 is connected to the 3.3V power supply terminal; the main controller (U2) HOST_SPI_MODE terminal is connected to one end of resistor R38, the other end of resistor R38 is connected to the first terminal of DIP switch SW3, and the second terminal of DIP switch SW3 is connected to the 3.3V power supply terminal; the main controller (U2) TESTPT5 terminal is connected to one end of resistor R556, the other end of resistor R556 is connected to the first terminal of DIP switch SW4, and the second terminal of DIP switch SW4 is connected to the 3.3V power supply terminal.
6. The marine HUD circuit system according to claim 1, characterized in that: The display driver module includes a DVI receiver (U501). The parallel data bus signal terminal of the main controller (U2) is connected to the parallel data bus signal terminal of the DVI receiver (U501). The differential signal terminal of the DVI receiver (U501) is connected to the differential signal terminal of the filter module. The filtered signal output terminal of the filter module is connected to the filtered signal input terminal of the HDMI input interface J4.
7. The marine HUD circuit system according to claim 6, characterized in that: The filtering module comprises four modules: a first filtering module (U505B), a second filtering module (U505A), a third filtering module (U506B), and a fourth filtering module (U506A). The positive terminal of the third differential signal channel of the DVI receiver (U501) is connected to the C1 terminal of the fourth filtering module (U506A), the negative terminal of the third differential signal channel of the DVI receiver (U501) is connected to the C2 terminal of the fourth filtering module (U506A), the positive terminal of the third filtered signal channel of the fourth filtering module (U506A) is connected to the J4TMDS_data_2+ terminal of the HDMI input interface, and the negative terminal of the third filtered signal channel of the fourth filtering module (U506A) is connected to the J4TMDS_data_2- terminal of the HDMI input interface. The positive terminal of the second differential signal channel of the DVI receiver (U501) is connected to the C1 terminal of the third filter module (U506B), the negative terminal of the second differential signal channel of the DVI receiver (U501) is connected to the C2 terminal of the third filter module (U506B), the positive terminal of the second filter signal channel of the third filter module (U506B) is connected to the J4TMDS_data_1+ terminal of the HDMI input interface, and the negative terminal of the second filter signal channel of the third filter module (U506B) is connected to the J4TMDS_data_1- terminal of the HDMI input interface. The positive terminal of the first differential signal channel of the DVI receiver (U501) is connected to the C1 terminal of the second filter module (U505A), the negative terminal of the first differential signal channel of the DVI receiver (U501) is connected to the C2 terminal of the second filter module (U505A), the positive terminal of the first filtered signal channel of the second filter module (U505A) is connected to the J4TMDS_data_1+ terminal of the HDMI input interface, and the negative terminal of the first filtered signal channel of the second filter module (U505A) is connected to the J4TMDS_data_1- terminal of the HDMI input interface. The positive terminal of the differential signal clock channel of the DVI receiver (U501) is connected to the C1 terminal of the first filter module (U505B), the negative terminal of the differential signal clock channel of the DVI receiver (U501) is connected to the C2 terminal of the first filter module (U505B), the positive terminal of the filter signal clock channel of the first filter module (U505B) is connected to the J4TMDS_clock+ terminal of the HDMI input interface, and the negative terminal of the filter signal clock channel of the first filter module (U505B) is connected to the J4TMDS_clock+ terminal of the HDMI input interface. The HDMI input interface J4 DDC_data terminal is connected to the second input terminal of the ESD protection module U502, one end of resistor R507, and the SDA terminal of the storage module U503. The other end of resistor R507 is connected to the HDMI input interface J4+5V_power terminal. The HDMI input interface J4 DDC_clock terminal is connected to the second input terminal of the ESD protection module U502, one end of resistor R518, and the SCL terminal of the storage module U503. The other end of resistor R518 and the VCC terminal of the storage module U503 are connected to the HDMI input interface J4+5V_power terminal. The third terminal of the ESD protection module U502 is connected to the power ground. The host controller (U2) HOST_IRQ_S terminal is connected to one end of resistor R39. The other end of resistor R39 is connected to the NOT gate buffer U15A terminal and the SPI protection chip U17D1+. The NOT gate buffer U15VCC terminal is connected to the 3.3V power supply terminal. The NOT gate buffer U15Y terminal is connected to one end of resistor R572 and the bridge U11GPIO_16 terminal. The other end of resistor R572 is connected to the other end of inductor L2. The host controller (U2) HOST_I2C_SDA terminal is connected to the level converter U7A1 terminal and the first input terminal of ESD protection chip U16. The host controller (U2) HOST_I2C_SCL terminal is connected to the level converter U7A2 terminal and the second input terminal of ESD protection chip U16. The ground terminal of ESD protection chip U16 is connected to the power supply ground.
8. The marine HUD circuit system according to claim 1, characterized in that: It also includes a jumper module for switching between Cypress and SPI bus. The jumper module includes the host controller (U2) HOST_SPI_CLK terminal connected to the second terminal of connector J10, the first terminal of connector J10 connected to one end of resistor R582, the other end of resistor R582 connected to the seventh terminal of SPI connector J15 and the SPI protection chip U512D1+ terminal, the third terminal of connector J10 connected to one end of resistor R567, and the other end of resistor R567 connected to the SPI bus transceiver U12B3 terminal. The host controller (U2) HOST_SPI_CSZ terminal is connected to the second terminal of connector J12. The first terminal of connector J12 is connected to one end of resistor R581. The other end of resistor R581 is connected to the ninth terminal of SPI connector J15 and the D2- terminal of SPI protection chip U512. The third terminal of connector J12 is connected to one end of resistor R564. The other end of resistor R564 is connected to the B4 terminal of SPI bus transceiver U12. The host controller (U2) HOST_SPI_PICO terminal is connected to the second terminal of connector J11. The first terminal of connector J11 is connected to one end of resistor R583 and the SPI protection chip U512D1- terminal. The other end of resistor R583 is connected to the eighth terminal of SPI connector J15. The third terminal of connector J11 is connected to one end of resistor R568. The other end of resistor R568 is connected to the SPI bus transceiver U12B1 terminal. One end of resistor R555 of the host controller (U2) HOST_SPI_POCI terminal is connected to the second end of connector J13. The first end of connector J10 is connected to the fifth end of SPI connector J15 and the SPI protection chip U512D2+. The third end of connector J10 is connected to the SPI bus transceiver U12B2. The VBUS terminal of the bridge U11 is connected to the first terminal of the USB input interface J9 and one terminal of the capacitor C603. The other terminal of the capacitor C603 is connected to the power ground. The USBDM terminal of the bridge U11 is connected to the second terminal of the USB input interface J9. The USBDP terminal of the bridge U11 is connected to the third terminal of the USB input interface J9. The bridge U11GPIO_7 terminal is connected to one end of resistor R560 and the NOT gate buffer U8A terminal. The NOT gate buffer U8B terminal is connected to the master controller (U2)PROJ_ON terminal. The other end of resistor R560 is connected to one end of capacitor C593, the NOT gate buffer U8VCC terminal and the other end of inductor L2. The other end of capacitor C593 is connected to power ground. The bridge U11CY_HOST_SCL terminal is connected to the level converter U7B2 terminal and one end of resistor R49. The other end of resistor R49 is connected to the other end of inductor L2. The bridge U11CY_HOST_SDA terminal is connected to the level converter U7B1 terminal and one end of resistor R48. The other end of resistor R48 is connected to the other end of inductor L2. The bridge U11CY_HOST_I2C_OE terminal is connected to the level converter U7OE terminal and one end of resistor R40. The other end of resistor R40 is connected to power ground.