A dynamic test circuit
By introducing an overcurrent protection unit into the dynamic test circuit, and utilizing a combination of current detection, comparison, and triggering modules, along with blanking pulse signals and latching control, the problem of untimely overcurrent protection in the dynamic test circuit is solved, achieving fast and reliable overcurrent protection and preventing damage to devices and equipment.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- BEIJING HUAFENG TEST & CONTROL TECH CO LTD
- Filing Date
- 2025-07-01
- Publication Date
- 2026-06-26
AI Technical Summary
Existing dynamic test circuits lack rapid overcurrent protection in third-generation semiconductor silicon carbide devices, resulting in a high risk of device or equipment damage and test fixture damage.
A dynamic test circuit was designed, which includes an overcurrent protection unit. By combining a current detection module, a comparison module, an AND gate module, and a trigger module, it achieves fast response and accurate detection. Combined with a blanking pulse signal and a latching control signal, it ensures the reliability of overcurrent protection.
It achieves rapid overcurrent protection for dynamic test circuits, prevents damage to devices and equipment, reduces the possibility of malfunctions, and ensures the reliability and safety of testing.
Smart Images
Figure CN224416981U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit technology, and in particular to a dynamic test circuit. Background Technology
[0002] Dynamic testing is a widely used method for evaluating the characteristics of power switching components such as field-effect transistors (FETs) and insulated-gate bipolar transistors (IGBTs). In dynamic test circuits, overcurrent protection (OCP) is essential to prevent device or equipment damage. Protection speed and prevention of false alarms are key considerations in OCP circuit design. This is especially true for third-generation semiconductor silicon carbide (SiC) devices, which have stringent timing requirements for OCP circuits, demanding even shorter protection times. Delayed overcurrent protection can damage not only devices or equipment but also test fixtures or probes. Therefore, there is an urgent need to design a dynamic test circuit with fast overcurrent protection to achieve rapid overcurrent protection during dynamic testing. Utility Model Content
[0003] In view of this, this application proposes a dynamic test circuit that provides comprehensive and reliable overcurrent protection for the dynamic test circuit through measures such as fast response, accurate detection, application of blanking pulse signals, introduction of latching control signals, and effective switching control.
[0004] To achieve the above objectives, this application provides a dynamic test circuit, which includes a high-voltage source, an energy storage capacitor, an electronic switch, and a load unit connected in sequence. The control terminal of the electronic switch is connected to a switch driving unit. The circuit also includes an overcurrent protection unit, which includes a current detection module, a comparison module, an AND gate module, and a trigger module.
[0005] The input terminal of the current detection module is connected to the output terminal of the electronic switch, and is used to collect the test current of the dynamic test circuit and convert it into a test voltage, which is then output to the comparison module through the first output terminal. The second output terminal of the current detection module is connected to the input terminal of the load unit.
[0006] The first input terminal of the comparison module is connected to the first output terminal of the current detection module, and is used to compare the test voltage with the reference voltage input at the second input terminal to obtain a first level signal;
[0007] The first input terminal of the AND gate module is connected to the output terminal of the comparison module. Based on the logical operation result of the first level signal and the blanking pulse signal input from the second input terminal, the second level signal is output to the input terminal of the trigger module through its output terminal.
[0008] The first output terminal of the trigger module is connected to the latch terminal of the comparison module and is used to output a latch control signal to the comparison module; the second output terminal is connected to the input terminal of the switch drive unit and is used to output an overcurrent protection signal to the switch drive unit.
[0009] Therefore, this application designs an overcurrent protection unit between the electronic switch and the load unit of the dynamic test circuit. The current detection module within this overcurrent protection unit collects the test current of the dynamic test circuit. When an overcurrent occurs in the dynamic test circuit, the current detection module can quickly collect the abnormal test current and convert it into a test voltage. The comparison module, by comparing the test voltage with a preset reference voltage, can immediately identify the overcurrent state and quickly transmit a signal to the trigger module via an AND gate module. This causes the trigger module to output an overcurrent protection signal to the switch drive unit, thereby quickly shutting off the electronic switch of the dynamic test circuit, cutting off the current path of the dynamic test circuit, and preventing circuit damage. In addition, the trigger module also outputs a latching control signal to the comparison module to lock the output state of the comparison module. That is, when an overcurrent signal is detected, the output of the comparison module will be latched, causing the trigger module to continuously output an overcurrent protection signal to the switch drive unit to maintain the overcurrent protection state. This application provides comprehensive and reliable overcurrent protection for the dynamic test circuit through measures such as fast response, accurate detection, the application of blanking pulse signals, the introduction of latching control signals, and effective switch control.
[0010] Optionally, a signal driving module is also included, which is connected between the AND gate module and the trigger module. The signal driving module includes a signal driver, the input of which is connected to the output of the AND gate module, and the output of which is connected to the input of the trigger module, for driving the second level signal to transmit rapidly.
[0011] As described above, by setting a signal driving module between the AND gate module and the trigger module, the signal driving module can be implemented using a signal driver. Signal drivers typically have high-speed driving capabilities, enabling them to quickly respond to changes in the input signal and output corresponding driving signals within a short time. By setting a signal driver, this application can quickly respond to the second-level signal output by the AND gate module and quickly output it to the trigger module after passing through the back-end circuit, thereby improving the signal transmission speed and reducing the overcurrent protection response time.
[0012] Optionally, a low-pass filter connected between the signal driving module and the triggering module may also be included;
[0013] The low-pass filter includes a filter resistor and a filter capacitor. The filter resistor is connected in series between the output terminal of the signal driving module and the input terminal of the trigger module. One end of the filter capacitor is connected to the output terminal of the filter resistor, and the other end is grounded.
[0014] As described above, by setting a low-pass filter composed of a filter resistor and a filter capacitor between the signal driving module and the triggering module, the signal transmitted from the signal driving module to the triggering module is smoothed, and high-frequency interference signals in the circuit are filtered out, reducing the possibility of false triggering or malfunction caused by signal fluctuations or noise interference.
[0015] Optionally, the low-pass filter may further include a discharge resistor connected in parallel across the filter capacitor.
[0016] Therefore, when the overcurrent protection unit circuit is disconnected, there may still be charge in the filter capacitor of the low-pass filter. A safe discharge path can be provided through the discharge resistor, so that the charge in the filter capacitor can be released quickly.
[0017] Optionally, it also includes a blanking pulse signal generation module, the output of which is connected to the second input of the AND gate module, for outputting a high-level blanking pulse signal to the AND gate module.
[0018] As described above, a blanking pulse signal generation module (e.g., an FPGA chip) can output a continuous high-level blanking pulse signal to one input of an AND gate module. When the first level signal input to the other input of the AND gate module is a low-level signal, the AND gate module outputs a low-level second-level signal after logic operation, and the back-end signal driving module does not respond. When the first level signal input to the other input of the AND gate module is a high-level signal, the AND gate module outputs a high-level second-level signal after logic operation, and the back-end signal driving module responds quickly and outputs the high-level second-level signal to the trigger module, thereby achieving fast overcurrent protection.
[0019] Optionally, it also includes an absorption capacitor connected between the electronic switch and the load unit, with one end of the absorption capacitor connected between the electronic switch and the load unit and the other end grounded;
[0020] The blanking pulse signal generation module is used to output a low-level blanking pulse signal of a first duration and a high-level blanking pulse signal of a second duration to the AND gate module.
[0021] Therefore, in dynamic test circuits, to reduce the impact of parasitic inductance on the test, a snubber capacitor is usually placed between the electronic switch and the load unit. At the beginning of the dynamic test, the transient large current during the charging of the snubber capacitor may cause the overcurrent protection unit to malfunction. Therefore, this application outputs a timing level signal through the FPGA chip, specifically a low-level signal of the first duration and a high-level signal of the second duration. The first duration of the low-level signal needs to cover the charging duration of the snubber capacitor. That is, even if a transient large current occurs during the charging period of the snubber capacitor, causing the comparator module to output a high-level first-level signal, the AND gate module will output a low-level second-level signal due to the low-level blanking pulse signal. When the snubber capacitor is fully charged and enters normal testing, and an overcurrent signal occurs in the dynamic test circuit, the blanking pulse signal switches from a low-level signal to a high-level signal. At this time, the AND gate module can output a high-level second-level signal based on the high-level first-level signal and the high-level blanking pulse signal, thereby causing the trigger module at the back end to output an overcurrent protection signal.
[0022] Optionally, the current detection module includes one of a Rogowski coil, a sampling resistor, a current transformer, and a Hall sensor.
[0023] Based on the specific application requirements and scenarios of the dynamic test circuit, one of the following can be selected as the current detection module: Rogowski coil, sampling resistor, current transformer, and Hall sensor. This module collects the test current of the dynamic test circuit and converts it into a test voltage. Among these, the Rogowski coil is suitable for scenarios requiring fast response and high-precision measurement, the sampling resistor has the advantages of low cost and ease of implementation, the current transformer is advantageous in scenarios requiring electrical isolation and current transformation, and the Hall sensor is more suitable for non-contact measurement and high-accuracy scenarios.
[0024] Optionally, the triggering module includes a trigger;
[0025] The first output terminal of the trigger is connected to the latch terminal of the comparison module, the second output terminal is connected to the input terminal of the switch driving unit, and the reset terminal is connected to a reset module, which is used to apply a reset signal to the trigger.
[0026] As shown above, when an overcurrent signal appears in the dynamic test circuit, the trigger can not only respond quickly to the overcurrent signal and trigger the protection action, but also output a low-level latch control signal and a high-level overcurrent protection signal to control the comparator to maintain its current state and trigger the overcurrent protection mechanism, respectively. When the overcurrent signal in the dynamic test circuit disappears, the trigger can be reset by applying a reset signal to the reset terminal of the trigger, ensuring that the circuit can resume normal operation after returning to normal.
[0027] Optionally, the switch driving unit includes a first input terminal and a second input terminal. The first input terminal is connected to the second output terminal of the trigger module and is used to receive the overcurrent protection signal output by the second output terminal of the trigger module. The second input terminal receives an external control signal. The output terminal of the switch driving unit is connected to the control terminal of the electronic switch and outputs a continuous shutdown signal to the electronic switch according to the valid overcurrent protection signal.
[0028] As described above, the switch driver unit has two input terminals, which receive the overcurrent protection signal output by the trigger module and the external control signal, respectively. When the overcurrent protection signal output by the trigger module is invalid, the switch driver unit will control the electronic switch to close or close according to the external control signal, so as to meet the user or system's manual or automatic control of the electronic switch according to the test requirements. When the overcurrent protection signal output by the trigger module is valid, the switch driver unit will immediately control the electronic switch to remain in the off state according to the overcurrent protection signal, ensuring that the circuit can quickly cut off the power supply when an overcurrent occurs and is no longer affected by the external control signal, preventing the external control signal from mistakenly closing the electronic switch and causing damage to the test circuit.
[0029] Optionally, the comparison module includes a voltage comparator, the first input of which is connected to the output of the current detection module, the second input of which receives an external reference voltage, and the output of which is connected to the first input of the AND gate module.
[0030] As described above, the voltage comparator compares the acquired test voltage with the preset reference voltage to determine whether there is an overcurrent in the test circuit. The voltage comparator has the characteristics of high-precision comparison, fast response, good stability, easy integration and low power consumption, which ensures the accuracy and reliability of overcurrent detection.
[0031] These and other aspects of this application will become more apparent in the description of the following embodiments(s). Attached Figure Description
[0032] Figure 1 A circuit diagram of the first dynamic test circuit provided in the embodiments of this application;
[0033] Figure 2 The timing diagram of the operation of the first overcurrent protection unit provided in the embodiments of this application;
[0034] Figure 3 A circuit diagram of the second dynamic test circuit provided in the embodiments of this application;
[0035] Figure 4 The timing diagram for the operation of the second overcurrent protection unit provided in the embodiments of this application;
[0036] Figure 5 A circuit diagram of a third dynamic test circuit provided in an embodiment of this application.
[0037] It should be understood that the dimensions and shapes of the block diagrams in the above structural diagrams are for reference only and should not constitute an exclusive interpretation of the embodiments of this application. The relative positions and inclusion relationships between the block diagrams presented in the structural diagrams are only schematic representations of the structural relationships between the block diagrams, and are not intended to limit the physical connection methods of the embodiments of this application. Detailed Implementation
[0038] The technical solutions provided in this application will be further described below with reference to the accompanying drawings and embodiments. It should be understood that the system architecture and business scenarios provided in the embodiments of this application are mainly for illustrating possible implementations of the technical solutions of this application and should not be construed as the sole limitation on the technical solutions of this application. Those skilled in the art will recognize that the technical solutions provided in this application are equally applicable to similar technical problems as system architectures evolve and new business scenarios emerge.
[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. In case of any inconsistency, the meaning set forth in this specification or derived from the content described herein shall prevail. Furthermore, the terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit the scope of this application.
[0040] This application proposes a dynamic test circuit that provides comprehensive and reliable overcurrent protection through measures such as fast response, accurate detection, the application of blanking pulse signals, the introduction of latching control signals, and effective switching control. Exemplary applications of this dynamic test circuit may include scenarios suitable for dual-pulse testing or short-circuit testing.
[0041] like Figure 1 As shown, this application embodiment provides a dynamic test circuit, referring to... Figure 1This dynamic test circuit, used in dual-pulse testing, includes a high-voltage source E, an energy storage capacitor C1, an electronic switch K, a dual-pulse load unit RL, and an overcurrent protection unit. One end of the energy storage capacitor C1 is connected to the positive output terminal of the high-voltage source E, and the other end is grounded. The input terminal of the electronic switch K is connected to the positive output terminal of the high-voltage source E, and the output terminal of the electronic switch K is connected to the input terminal of the dual-pulse load unit RL. The control terminal of the electronic switch K is connected to a switch driver U5 (i.e., the aforementioned switch driver unit) and is controlled by the switch driver U5. The switch driver U5 has two input terminals, which respectively receive the overcurrent protection signal output by the overcurrent protection unit and the external control signal DI. When the overcurrent protection unit does not output a valid overcurrent protection signal, the switch driver U5 controls the electronic switch K to close or close according to the external control signal DI. When the overcurrent protection unit outputs a valid overcurrent protection signal, the switch driver U5 controls the electronic switch K to remain closed according to the overcurrent protection signal.
[0042] The overcurrent protection unit comprises, in sequence, a Rogowski coil RC (i.e., the aforementioned current detection module), a comparator U1 (i.e., the aforementioned comparison module), an AND gate device U2 (i.e., the aforementioned AND gate module), a signal driver U3 (i.e., the aforementioned signal driving module), a filter resistor R1, a filter capacitor C3, and a trigger U4 (i.e., the aforementioned trigger module). The input terminal of the Rogowski coil RC is connected to the output terminal of the electronic switch K, and the second output terminal of the Rogowski coil RC is connected to the dual-pulse load unit RL. The first input terminal of the comparator U1 is connected to the first output terminal of the Rogowski coil RC, and the second input terminal receives an externally input reference voltage. The output terminal of the comparator U1 is connected to the first input terminal of the AND gate device U2, which receives an externally input blanking pulse signal. The output terminal of the AND gate device U2 is connected to the input terminal of the signal driver U3. The output terminal of the signal driver U3 is connected in series with the filter resistor R1 and then connected to the input terminal of the trigger U4. The output terminal of the filter resistor R1 is also connected in series with the filter capacitor C3 and then grounded. The trigger U4 has two output terminals: the first output terminal is connected to the latch terminal of the comparator U1, and the second output terminal is connected to the input terminal of the switch driver U5. Specifically, the Rogowski coil RC collects the test current of the dual-pulse test circuit and converts it into a test voltage VRC, which is then output to comparator U1. Comparator U1 outputs a first-level signal to AND gate U2 based on the comparison result of the test voltage VRC and a reference voltage VREF. The other end of AND gate U2 can be provided with a continuously high-level blanking pulse signal BI through an external FPGA chip (i.e., the aforementioned blanking pulse signal generation module). This allows AND gate U2 to perform logical operations based on the first-level signal and the blanking pulse signal BI and output a second-level signal to signal driver U3. When the second-level signal is low, signal driver U3 does not respond. When the second-level signal is high, signal driver U3 responds and quickly charges the filter capacitor C3 through the back-end filter resistor R1, and then enters trigger U4. Trigger U4 then responds and outputs an overcurrent protection signal to the front-end switch driver U5 to drive the electronic switch K to turn off, thereby protecting the dual-pulse test circuit.
[0043] It should be noted that in this embodiment, the comparison module adopts the form of comparator U1, specifically an inverting comparator or a non-inverting comparator, and the specific chip model is not specifically limited in this embodiment, and can be selected as needed; the AND gate module can be a common electronic logic element, or it can be an AND gate circuit composed of MOS transistors, and the corresponding chip type can be selected as needed; similarly, the main function of the blanking pulse signal generation module is to generate the required blanking signal, and it is not limited whether it is generated by the FPGA or by the relevant blanking circuit.
[0044] It should be noted that this embodiment protects the circuit structure of the dynamic test circuit. Through the connection relationships and circuit construction of each module in the overcurrent protection circuit, a rapid response to overcurrent signals is achieved. The comparison of the test voltage with the standard voltage using a comparator, and the logical operations of the AND gate devices, are implementations of the device's own functions and do not involve any methodological improvements.
[0045] based on Figure 1 As shown, the high-voltage source E, energy storage capacitor C1, electronic switch K, switch driver U5, and load unit RL are the basic units constituting the dual-pulse dynamic test circuit. The load unit RL is a dual-pulse load unit. During normal testing, the energy storage capacitor C1 is charged to a certain voltage by the high-voltage source E. A positive voltage control signal DI is input to an input terminal of the switch driver U5 through an external FPGA chip or other chip. This controls the output terminal of the switch driver U5 to output a positive voltage turn-on signal to the electronic switch K. The electronic switch K closes, and the energy storage capacitor C1 supplies power to the dual-pulse load unit RL through the electronic switch K, thus starting the normal dynamic test. When the test is completed, a control signal DI is input to the input terminal of the switch driver U5 through an external FPGA chip or other chip. This controls the output terminal of the switch driver U5 to output a turn-off signal to the electronic switch K. The electronic switch K turns off, and the energy storage capacitor C1 stops supplying power to the dual-pulse load unit RL. The dual-pulse test circuit is then disconnected. When an abnormality occurs during testing, causing an overcurrent situation in the dual-pulse test circuit, i.e., the test current continues to rise, which can easily damage the downstream dual-pulse load unit RL or the test fixture, the overcurrent protection unit of this embodiment needs to respond immediately and turn off the electronic switch K to achieve rapid overcurrent protection for the dual-pulse test circuit.
[0046] It should be noted that the dynamic test circuit provided in this application can also realize the short-circuit current test. By applying the circuit provided by the overcurrent protection unit of this application, fast overcurrent protection for short-circuit current testing can be realized. For the specific implementation method, please refer to the dual-pulse test circuit, which will not be described in detail here.
[0047] It should be noted that during normal testing, the closing or closing of electronic switch K is driven by the control signal D1 received by switch driver U5. When an overcurrent protection signal is present, the overcurrent protection signal received by switch driver U5 has a higher priority than the control signal D1. In other words, the electronic switch K is directly controlled to turn off based on the overcurrent protection signal. At this time, the turning off of electronic switch K is independent of the state of control signal D1.
[0048] Specifically, when an overcurrent signal occurs in the dynamic test circuit, the Rogowski coil RC acquires the test current of the dynamic test circuit and converts it into a test voltage VRC, which is then output to comparator U1. At this time, the test voltage VRC is greater than the reference voltage VREF. Based on the comparison result, comparator U1 outputs a high-level first-level signal to the AND gate device U2. The AND gate device U2 outputs a high-level second-level signal to the signal driver U3 based on the logical operation result of the high-level first-level signal and the high-level blanking pulse signal BI. This signal quickly passes through the signal driver U3 and reaches the low-pass filter composed of the filter resistor R1 and the filter capacitor C3 at the back end to filter out high-frequency interference in the second-level signal. The filtered second-level signal quickly charges the filter capacitor C3 and then reaches the trigger U4. Based on the high-level second-level signal, the trigger U4 outputs a low-level latch control signal Q to the latch terminal of comparator U1 and a high-level overcurrent protection signal, respectively. At the other input terminal of the switch driver U5, the latch control signal Q latches the first-level signal output by comparator U1, meaning comparator U1 continuously outputs a high-level first-level signal, no longer affected by the test voltage VRC acquired by the Rogowski coil RC, preventing repeated changes in the protection state due to subsequent current fluctuations. This overcurrent protection signal... This ensures that the switch driver U5 maintains an output off signal to the electronic switch K, and is no longer affected by the control signal DI.
[0049] It should be noted that in this embodiment, the value of the filter resistor R1 in the low-pass filter can range from 10 to 100Ω, the value of the filter capacitor C3 can range from 100 to 470pF, and the protection time (the time interval between the current reaching the protection threshold and the current reaching its peak value) can be shortened to within 800ns. Other value ranges can be set in other embodiments, and no specific limitation is made here.
[0050] When the overcurrent protection unit needs to be reset, a reset signal can be applied to the reset terminal of flip-flop U4 through a reset module to reset flip-flop U4. The signal level output at the output terminal will then be switched, i.e., a high-level latch control signal Q will be output to the latch terminal of comparator U1 and a low-level overcurrent protection signal will be output respectively. To the other input terminal of the switch driver U5, release the latch state of the comparator U1 and the lock state of the switch driver U5.
[0051] According to the dynamic test circuit of this embodiment, the driving capability of the AND gate module output signal is enhanced by setting the driver in the overcurrent protection circuit. Specifically, it can shorten the charging time of the AND gate module for the filter capacitor, enabling the filter capacitor to charge quickly, thereby reducing the overcurrent protection response time and achieving the purpose of fast overcurrent protection, protecting the device under test, test equipment, and test fixture. Moreover, by setting the low-pass filter, high-frequency interference signals can be filtered out, preventing interference signals from entering the trigger and causing the overcurrent protection circuit to malfunction, thus ensuring the accuracy of overcurrent protection judgment. By setting the latch control signal and blanking pulse signal, false triggering of overcurrent protection is avoided.
[0052] In some embodiments, a discharge resistor R2 is also connected in parallel across the filter capacitor C3. When the circuit of the overcurrent protection unit is disconnected, there may still be charge in the filter capacitor C3. At this time, a safe discharge path can be provided through the discharge resistor R2, so that the charge in the filter capacitor C3 can be released quickly, preparing for the next overcurrent protection action.
[0053] In some embodiments, depending on the specific application requirements and scenarios of the dynamic test circuit, the aforementioned Rogowski coil RC can also be replaced by a sampling resistor, a current transformer, or a Hall sensor. Among these, the sampling resistor typically has the advantages of low cost and ease of implementation, the current transformer is advantageous in scenarios requiring electrical isolation and current transformation, while the Hall sensor is more suitable for non-contact measurement and high accuracy scenarios.
[0054] Figure 2 The timing diagram of the operation of the above-mentioned overcurrent protection unit is shown. (Refer to...) Figure 2 As shown, before time t0, the electronic switch K in the dynamic test circuit is in the open state. At this time, no current flows through the dynamic test circuit, and the test voltage VRC collected and output to comparator U1 by the Rogowski coil RC in the overcurrent protection unit is less than the reference voltage VREF. At this time, comparator U1 outputs a low level. Before time t0, the electronic switch K is closed, the dynamic test circuit is turned on, and the circuit operates normally. If an overcurrent condition occurs at time t0, the Rogowski coil RC collects the overcurrent in the dynamic test circuit and converts it into a test voltage VRC, which is then output to comparator U1. This test voltage VRC is greater than the reference voltage VREF. During the time interval t0-t1, comparator U1 outputs a high-level first-level signal to AND gate U2 based on the comparison result. AND gate U2 outputs a high-level second-level signal to signal driver U3 based on the logical operation result of the high-level first-level signal and the high-level blanking pulse signal BI. After quickly passing through signal driver U3 and a low-pass filter, the signal reaches flip-flop U4 at time t1. Flip-flop U4 outputs a low-level latch control signal Q to the latch terminal of comparator U1 and a high-level overcurrent protection signal based on the high-level second-level signal. At the other input terminal of the switch driver U5, the latch control signal Q latches the first level signal output by the comparator U1, that is, the comparator U1 continuously outputs a high-level first level signal, which is the overcurrent protection signal. This keeps the switch driver U5 outputting a turn-off signal to the electronic switch K. At this time, the dynamic test circuit is disconnected to facilitate component replacement. When the test circuit returns to normal at time t3, a high-level reset signal can be applied to the reset terminal of the flip-flop U4. The flip-flop resets and outputs a high-level latch control signal Q to the latch terminal of the comparator U1 and a low-level overcurrent protection signal, respectively. The signal is transferred to the other input terminal of the switch driver U5. At this time, the output of comparator U1 is unlocked, and the switch driver U5 returns to normal operation. It can control the electronic switch K to close or close according to its control signal DI. At time t4, the comparator U1 outputs a low-level first-level signal. The AND gate device U2 outputs a low-level second-level signal based on the logical operation result of the low-level first-level signal and the high-level blanking pulse signal BI (in actual applications, the AND gate device U2 does not immediately output a low-level second-level signal at time t4, but delays for a short period of time. This short period of time is ignored here for the sake of description). At this time, the overcurrent protection unit is reset and waits for the next overcurrent condition of the dynamic test circuit to occur.
[0055] In some embodiments, to reduce the impact of parasitic inductance on the test, a snubber capacitor C2 is typically placed between the electronic switch K and the load unit RL of the dynamic test circuit, such as... Figure 3As shown, one end of the absorption capacitor C2 is connected between the electronic switch K and the load unit RL, and the other end is grounded. When the dynamic test just starts, the transient large current during the charging of the absorption capacitor C2 may cause the overcurrent protection unit of this embodiment to malfunction. That is, the transient large current during the charging of the absorption capacitor C2 will cause the test voltage VRC collected and converted by the Rogowski coil RC to be greater than the reference voltage VREF. At this time, the comparator U1 outputs a high-level first-level signal. If the blanking pulse signal BI at the input of the AND gate device U2 is high at this time, the AND gate device U2 will output a high-level second-level signal according to the logic operation result, which will cause the trigger U4 to output an overcurrent protection signal, triggering the malfunction of the overcurrent protection unit and cutting off the dynamic test circuit. Therefore, in the existing structure, the overcurrent protection unit of this application embodiment only needs to perform timing design on the blanking pulse signal BI output by the FPGA chip to the AND gate device U2. According to the charging duration of the absorption capacitor C2, a low-level blanking pulse signal BI of a first duration is provided first, so that the first duration can completely cover the charging duration of the absorption capacitor C2. When the absorption capacitor C2 is fully charged, it is switched to a high-level blanking pulse signal BI to prevent the transient large current during the charging of the absorption capacitor C2 from causing the overcurrent protection unit to malfunction.
[0056] Figure 4 It shows Figure 3 The timing diagram of the overcurrent protection unit shown is for reference. Figure 4As shown, before time t0, the electronic switch K in the dynamic test circuit is in the open state. At this time, no current flows through the dynamic test circuit. The Rogowski coil RC in the overcurrent protection unit collects and outputs the test voltage VRC to comparator U1, which is less than the reference voltage VREF. At this time, comparator U1 outputs a low level. At time t0, the electronic switch K closes, and the dynamic test circuit is turned on. During the time period t0-t1, the transient large current when the absorption capacitor C2 is charging makes the test voltage VRC of comparator U1 greater than the reference voltage VREF. Based on the comparison result, comparator U1 outputs a high-level first-level signal to AND gate device U2. During the time period t0-t2, the blanking pulse signal BI output by the external FPGA chip to AND gate device U2 is low. That is, during time t0-t2, AND gate device U2 outputs a low-level second-level signal. In this embodiment, the overcurrent protection unit is shielded and does not output an overcurrent protection signal. At time t2, the absorption capacitor C2 completes charging, and the dynamic test circuit starts normal testing. At this time, the blanking pulse signal BI output from the external FPGA chip to the AND gate device U2 is switched to a high level. The test voltage VRC of comparator U1 is less than the reference voltage VREF, so comparator U1 outputs a low-level signal, and the AND gate device U2 continues to output a low-level signal. At time t3, if an overcurrent occurs in the dynamic test circuit, the test voltage VRC of comparator U1 will be greater than the reference voltage VREF, and comparator U1 will output a high-level first-level signal. The AND gate device U2 outputs a high-level second-level signal based on the logical operation result of the high-level first-level signal and the high-level blanking pulse signal BI, which is sent to the signal driver U3. After quickly passing through the signal driver U3 and the low-pass filter, it reaches the flip-flop U4 at time t4. The flip-flop U4 outputs a low-level latch control signal Q to the latch terminal of comparator U1 and a high-level overcurrent protection signal based on the high-level second-level signal. The signal is directed to the other input of the switch driver U5 (in practical applications, the flip-flop U4 does not immediately output the latch control signal Q at time t4, which is then sent to the comparator U1 and the overcurrent protection signal). The signal propagates to the switch driver U5, but for a short period of time (this short period is omitted for simplicity). The latch control signal Q latches the first level signal output by comparator U1, meaning comparator U1 continuously outputs a high-level first level signal. This overcurrent protection signal... This keeps the switch driver U5 outputting a turn-off signal to the electronic switch K, at which point the dynamic test circuit is disconnected to facilitate component replacement. When the test circuit returns to normal at time t6, a high-level reset signal can be applied to the reset terminal of the flip-flop U4. The flip-flop resets and outputs a high-level latch control signal Q to the latch terminal of comparator U1 and a low-level overcurrent protection signal. The signal is transferred to the other input terminal of the switch driver U5. At this time, the output of comparator U1 is unlocked, and the switch driver U5 returns to normal operation. It can control the electronic switch K to close or close according to its control signal DI. At time t7, the comparator U1 outputs a low-level first-level signal. The AND gate device U2 outputs a low-level second-level signal based on the logical operation result of the low-level first-level signal and the high-level blanking pulse signal BI. At this time, the overcurrent protection unit is reset and waits for the next overcurrent condition of the dynamic test circuit to occur.
[0057] In some embodiments, for applications with low signal interference or low requirements for signal noise, the overcurrent protection unit may not require a low-pass filter to simplify the circuit, as shown in the example below. Figure 5 As shown, the dynamic test circuit includes a high-voltage source E, an energy storage capacitor C1, an electronic switch K, a load unit RL, and an overcurrent protection unit. One end of the energy storage capacitor C1 is connected to the positive output terminal of the high-voltage source E, and the other end is grounded. The input terminal of the electronic switch K is connected to the positive output terminal of the high-voltage source E, and the output terminal of the electronic switch K is connected to the input terminal of the load unit RL. The control terminal of the electronic switch K is connected to and controlled by a switch driver U5. The switch driver U5 has two input terminals, receiving the overcurrent protection signal output from the overcurrent protection unit and an external control signal DI, respectively. The overcurrent protection unit includes a Rogowski coil RC, a comparator U1, an AND gate device U2, a signal driver U3, and a trigger U4 connected in sequence. The input terminal of the Rogowski coil RC is connected to the output terminal of the electronic switch K. The second output terminal of the Rogowski coil RC is connected to the load unit RL. The first input terminal of the comparator U1 is connected to the first output terminal of the Rogowski coil RC. The second input terminal receives an externally input reference voltage. The output terminal is connected to the first input terminal of the AND gate device U2. The second input terminal of the AND gate device U2 receives an externally input blanking pulse signal. The output terminal is connected to the input terminal of the signal driver U3. The output terminal of the signal driver U3 is connected to the CLK (clock) input terminal of the flip-flop U4. The flip-flop U4 has two output terminals. The first output terminal is connected to the latch terminal of the comparator U1, and the second output terminal is connected to the input terminal of the switch driver U5.
[0058] It should be understood that the circuit working principle in the embodiments of this application can be referred to Figures 1-2 The descriptions of the embodiments and related extended embodiments shown will not be repeated in this application.
[0059] In summary, this embodiment of the application designs an overcurrent protection unit between the electronic switch and the load unit of the dynamic test circuit, and collects the test current of the dynamic test circuit through the current detection circuit in the overcurrent protection unit. When an overcurrent occurs in the dynamic test circuit, the current detection circuit can quickly collect the abnormal test current and convert it into a test voltage. The comparator can immediately identify the overcurrent state by comparing the test voltage with a preset reference voltage, and quickly transmit the signal to the trigger through AND gate devices and signal drivers, so that the trigger outputs an overcurrent protection signal to the switch driver, thereby quickly turning off the electronic switch of the dynamic test circuit, cutting off the current path of the dynamic test circuit, and preventing circuit damage. In addition, the trigger also outputs a latching control signal to the comparator to lock the output state of the comparator. That is, when an overcurrent signal is detected, the output of the comparator will be latched, thereby causing the trigger to continuously output an overcurrent protection signal to the switch driver to maintain the overcurrent protection state and prevent repeated changes in the protection state due to subsequent current fluctuations. In addition, when an absorption capacitor is added to the dynamic test circuit, by changing the high and low levels of the blanking pulse signal, the malfunction of the AND gate device caused by the instantaneous high current charging of the absorption capacitor during dynamic testing can be prevented. This application's embodiments provide comprehensive and reliable overcurrent protection for the dynamic test circuit through measures such as fast response, accurate detection, the application of blanking pulse signals, the introduction of latching control signals, and effective switching control.
[0060] It should be noted that the embodiments described in this application are merely some embodiments, not all embodiments. The components of the embodiments of this application typically described and shown in the accompanying drawings can be arranged and designed in various different configurations. Therefore, the above detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.
[0061] The terms "first, second, third, etc." or similar terms such as module A, module B, module C, etc., used in the specification and claims are only used to distinguish similar objects and do not represent a specific ordering of objects. It is understood that a specific order or sequence may be interchanged where permitted so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.
[0062] In the above description, the labels indicating the steps do not necessarily mean that the steps will be executed. They may include intermediate steps or be replaced by other steps. Where permissible, the order of the steps may be interchanged or executed simultaneously.
[0063] The term "comprising" as used in the specification and claims should not be construed as limiting itself to what follows; it does not exclude other elements or steps. Therefore, it should be interpreted as specifying the presence of the mentioned feature, integral, step, or component, but does not exclude the presence or addition of one or more other features, integrals, steps, or components, or groups thereof. Thus, the statement "device comprising means A and B" should not be limited to a device consisting solely of components A and B.
[0064] The terms "an embodiment" or "an embodiment" as used in this specification mean that a particular feature, structure, or characteristic described in conjunction with that embodiment is included in at least one embodiment of this application. Therefore, the terms "in one embodiment" or "in an embodiment" appearing throughout this specification do not necessarily refer to the same embodiment, but may refer to the same embodiment. Furthermore, in the various embodiments of this application, unless otherwise specified or in case of logical conflict, the terminology and / or descriptions between different embodiments are consistent and can be mutually referenced. Technical features in different embodiments can be combined to form new embodiments based on their inherent logical relationships.
[0065] Note that the above are merely preferred embodiments and the technical principles employed in this application. Those skilled in the art will understand that this application is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of this application. Therefore, although this application has been described in detail through the above embodiments, this application is not limited to the above embodiments. Many other equivalent embodiments may be included without departing from the concept of this application, all of which fall within the scope of protection of this application.
Claims
1. A dynamic test circuit, comprising a high-voltage source, an energy storage capacitor, an electronic switch, and a load unit connected in sequence, wherein the control terminal of the electronic switch is connected to a switch driving unit, characterized in that, It also includes an overcurrent protection unit, which comprises a current detection module, a comparison module, an AND gate module, and a trigger module; The input terminal of the current detection module is connected to the output terminal of the electronic switch, and is used to collect the test current of the dynamic test circuit and convert it into a test voltage, which is then output to the comparison module through the first output terminal. The second output terminal of the current detection module is connected to the input terminal of the load unit. The first input terminal of the comparison module is connected to the first output terminal of the current detection module, and is used to compare the test voltage with the reference voltage input at the second input terminal to obtain a first level signal; The first input terminal of the AND gate module is connected to the output terminal of the comparison module. Based on the logical operation result of the first level signal and the blanking pulse signal input from the second input terminal, the second level signal is output to the input terminal of the trigger module through its output terminal. The second output terminal of the trigger module is connected to the input terminal of the switch drive unit and is used to output an overcurrent protection signal to the switch drive unit.
2. The dynamic test circuit according to claim 1, characterized in that, It also includes a signal driving module connected between the AND gate module and the trigger module. The signal driving module includes a signal driver, the input of which is connected to the output of the AND gate module and the output of which is connected to the input of the trigger module, for driving the second level signal to transmit rapidly.
3. The dynamic test circuit according to claim 2, characterized in that, It also includes a low-pass filter connected between the signal driving module and the triggering module; The low-pass filter includes a filter resistor and a filter capacitor. The filter resistor is connected in series between the output terminal of the signal driving module and the input terminal of the trigger module. One end of the filter capacitor is connected to the output terminal of the filter resistor, and the other end is grounded.
4. The dynamic test circuit according to claim 3, characterized in that, The low-pass filter also includes a discharge resistor connected in parallel across the filter capacitor.
5. The dynamic test circuit according to claim 1, characterized in that, It also includes a blanking pulse signal generation module, the output of which is connected to the second input of the AND gate module, and is used to output a high-level blanking pulse signal to the AND gate module.
6. The dynamic test circuit according to claim 5, characterized in that, It also includes an absorption capacitor connected between the electronic switch and the load unit, with one end of the absorption capacitor connected between the electronic switch and the load unit and the other end grounded; The blanking pulse signal generation module is used to output a low-level blanking pulse signal of a first duration and a high-level blanking pulse signal of a second duration to the AND gate module.
7. The dynamic test circuit according to claim 1, characterized in that, The first output terminal of the trigger module is connected to the latch terminal of the comparison module, and is used to output a latch control signal to the comparison module.
8. The dynamic test circuit according to claim 1, characterized in that, The triggering module includes a trigger; The first output terminal of the trigger is connected to the latch terminal of the comparison module, the second output terminal is connected to the input terminal of the switch driving unit, and the reset terminal is connected to a reset module, which is used to apply a reset signal to the trigger.
9. The dynamic test circuit according to claim 1, characterized in that, The switch driving unit includes a first input terminal and a second input terminal. The first input terminal is connected to the second output terminal of the trigger module and is used to receive the overcurrent protection signal output by the second output terminal of the trigger module. The second input terminal receives an external control signal. The output terminal of the switch driving unit is connected to the control terminal of the electronic switch and outputs a continuous shutdown signal to the electronic switch according to the valid overcurrent protection signal.
10. The dynamic test circuit according to claim 1, characterized in that, The comparison module includes a voltage comparator. The first input terminal of the voltage comparator is connected to the output terminal of the current detection module, the second input terminal receives an external reference voltage, and the output terminal is connected to the first input terminal of the AND gate module.