High-speed SPI communication circuit based on digital isolator

Abstract

The utility model discloses a high -speed SPI communication circuit based on digital isolator, including SPI host equipment, SPI slave equipment and digital isolator U1, digital isolator U1 is connected between SPI host equipment and SPI slave equipment, A1 end of digital isolator U1 is electrically connected with the SCK signal end of SPI host equipment through resistance R1 and inductance L1, the common terminal of resistance R1 with inductance L1 is grounded through capacitor C2 and the common terminal of resistance R1 and A1 end is grounded through capacitor C5. The utility model discloses a high -speed SPI communication circuit based on digital isolator, solves the problem, such as radiation emission overproof, signal integrity is poor, timing synchronization is difficult, and the anti -interference ability is insufficient in the prior art, realizes the reliable SPI communication of high isolation voltage, high data rate.

Description

Technical Field

[0001] This utility model belongs to the field of SPI communication technology, specifically relating to a high-speed SPI communication circuit based on a digital isolator. Background Technology

[0002] SPI (Serial Peripheral Interface) is a widely used synchronous serial communication interface with advantages such as full-duplex operation, high speed, and low latency, and is widely used in embedded systems. However, in applications with high electrical isolation requirements, such as power meters, industrial control, and medical equipment, traditional optocoupler isolation solutions suffer from limitations in speed, high power consumption, and short lifespan. While existing magnetic coupling isolation (such as transformer coupling) offers higher speed, it is also more expensive and susceptible to electromagnetic interference.

[0003] In summary, traditional isolation methods have the following problems:

[0004] 1. Optical isolation: limited speed (typically <10MHz), high power consumption, and issues such as optical decay;

[0005] 2. Transformer coupling: large size, high cost, and susceptible to electromagnetic interference;

[0006] 3. Capacitive isolation: Requires additional impedance matching circuit design, and high-frequency characteristics are greatly affected by PCB layout.

[0007] Although capacitively coupled isolation (CLI) technology has advantages such as high speed, low power consumption, and long lifespan, current CLI solutions for SPI communication still have the following problems:

[0008] 1. Poor signal integrity: High-speed SPI signals (such as those above 50MHz) are prone to signal reflection and distortion due to impedance mismatch after being isolated by capacitive coupling.

[0009] 2. Timing synchronization difficulties: The propagation delay of the capacitive isolator may cause the clock phase of the SPI master and slave devices to deviate, affecting the reliability of communication.

[0010] 3. Insufficient common-mode noise suppression: In high-frequency noise environments, capacitive isolation may lead to data errors due to common-mode interference.

[0011] While existing digital isolators offer high data transmission rates, they still present a problem when applied to SPI communication: long-distance SPI bus traces on the PCB can lead to excessive radiated emission frequencies in overall EMI testing. Therefore, there is an urgent need for an optimized high-speed isolated SPI communication circuit to reduce overall radiated emission characteristics, improve communication signal integrity, reduce latency, and enhance anti-interference capabilities.

[0012] Therefore, further improvements will be made to address the aforementioned issues. Utility Model Content

[0013] The main objective of this invention is to provide a high-speed SPI communication circuit based on a digital isolator. By optimizing the isolator configuration, signal conditioning, and power supply design, it achieves: overall radiated emission characteristics controlled within the standard range; support for SPI clock frequencies ≥100MHz; and tolerance to isolation voltages of 5KV / 1min. It is suitable for applications requiring high electrical isolation and high data rates, such as power meters, industrial control, medical equipment, and power systems. It solves problems in existing technologies such as excessive radiated emission, poor signal integrity, difficulty in timing synchronization, and insufficient anti-interference capabilities, achieving reliable SPI communication with high isolation voltage (e.g., 5kV) and high data rates (≥100MHz).

[0014] To achieve the above objectives, this utility model provides a high-speed SPI communication circuit based on a digital isolator, including an SPI master device, an SPI slave device, and a digital isolator U1, wherein the digital isolator U1 is connected between the SPI master device and the SPI slave device, wherein:

[0015] The A1 terminal of the digital isolator U1 is electrically connected to the SCK signal terminal of the SPI master device through resistor R1 and inductor L1. The common terminal of resistor R1 and inductor L1 is grounded through capacitor C2, and the common terminal of resistor R1 and A1 is grounded through capacitor C5.

[0016] The A2 terminal of the digital isolator U1 is electrically connected to the MOSI signal terminal of the SPI master device through resistor R2 and inductor L2. The common terminal of resistor R2 and inductor L2 is grounded through capacitor C3, and the common terminal of resistor R2 and A2 is grounded through capacitor C6.

[0017] The A3 terminal of the digital isolator U1 is electrically connected to the SS signal terminal of the SPI master device through resistor R3 and inductor L3. The common terminal of resistor R3 and inductor L3 is grounded through capacitor C4, and the common terminal of resistor R3 and A3 is grounded through capacitor C7.

[0018] The A4 terminal of the digital isolator U1 is electrically connected to the MISO signal terminal of the SPI master device through resistor R4, and the end of resistor R4 away from the A4 terminal is grounded through capacitor C1.

[0019] The B1 terminal of the digital isolator U1 is electrically connected to the SCK signal terminal of the SPI slave device through a resistor R6, and the end of the resistor R6 away from the B1 terminal is grounded through a capacitor C14.

[0020] The B2 terminal of the digital isolator U1 is electrically connected to the MOSI signal terminal of the SPI slave device through a resistor R7, and the end of the resistor R7 away from the B2 terminal is grounded through a capacitor C15.

[0021] The B3 terminal of the digital isolator U1 is electrically connected to the SS signal terminal of the SPI slave device through a resistor R8, and the end of the resistor R8 away from the B3 terminal is grounded through a capacitor C16.

[0022] The resistor R9 and inductor L4 at the B4 terminal of the digital isolator U1 are electrically connected to the MISO signal terminal of the SPI slave device. The common terminal of the resistor R9 and the inductor L4 is grounded through capacitor C8, and the common terminal of the resistor R9 and the B4 terminal is grounded through capacitor C13.

[0023] As a further preferred embodiment of the above technical solution, the power supply voltage on side A of the digital isolator U1 is MVCC, wherein:

[0024] A capacitor C10 is connected between pin 1 and pin 2 of the digital isolator U1, and a capacitor C9 is connected in parallel across the two ends of the capacitor C10. One end of the capacitor C9 is connected to MVCC.

[0025] As a further preferred embodiment of the above technical solution, the power supply voltage on the B side of the digital isolator U1 is SVCC, wherein:

[0026] A capacitor C11 is connected between pins 15 and 16 of the digital isolator U1, and a capacitor C12 is connected in parallel across the two ends of the capacitor C11. One end of the capacitor C12 is connected to SVCC.

[0027] As a further preferred technical solution to the above technical solution, pin 7 of the digital isolator U1 is connected to MVCC through resistor R5.

[0028] As a further preferred technical solution to the above technical solution, pin 10 of the digital isolator U1 is connected to SVCC through resistor R10.

[0029] The beneficial effects of this utility model are as follows:

[0030] By implementing electrical isolation through digital isolators, combined with impedance matching, clock compensation, and common-mode noise suppression technologies, this solution addresses the issue of excessive radiated emissions in EMI testing of three-phase energy meters when the SPI bus on the PCB has to be routed over long distances. It also resolves the integrity and timing synchronization issues of high-speed SPI signals during isolated transmission. This solution is suitable for applications requiring high isolation and high data rates, such as power meters, industrial control systems, and medical equipment, and offers advantages such as high speed (≥100MHz), high reliability, and low cost.

[0031] 1. High-speed communication: Supports SPI clock frequencies of 100MHz and above, suitable for high-speed data acquisition and industrial control;

[0032] 2. High reliability: By using impedance matching and clock compensation, signal distortion and timing offset are reduced, improving communication stability.

[0033] 3. Strong anti-interference capability: The common-mode choke and low-pass filter design effectively suppresses electromagnetic interference (EMI) in industrial environments.

[0034] 4. Low cost and long lifespan: Compared with optocoupler and magnetic coupling isolation, digital isolator isolation solutions have no optical decay and magnetic saturation problems and have a longer lifespan.

[0035] In practical applications, this circuit simultaneously solves problems such as voltage level mismatch between the master MCU in a 3.3V system and the slave device in a 5V system. In actual use, the SPI communication rate can reach 100MHz and above. Because a digital isolator is used, the signals on both sides of the master and slave devices are also isolated, preventing damage to the master MCU from problems on the slave side. Attached Figure Description

[0036] Figure 1 This is a schematic diagram of the principle of this utility model.

[0037] Figure 2 This is the circuit schematic diagram of this utility model. Detailed Implementation

[0038] The following description is intended to disclose the present invention so that those skilled in the art can implement it. The preferred embodiments described below are merely examples, and other obvious variations will occur to those skilled in the art. The basic principles of the present invention defined in the following description can be applied to other embodiments, modifications, improvements, equivalents, and other technical solutions that do not depart from the spirit and scope of the present invention.

[0039] This utility model discloses a high-speed SPI communication circuit based on a digital isolator. The specific embodiments of the utility model are further described below with reference to preferred embodiments.

[0040] In the embodiments of this utility model, those skilled in the art will note that SPI and the like involved in this utility model can be considered as prior art.

[0041] Preferred embodiment.

[0042] This utility model discloses a high-speed SPI communication circuit based on a digital isolator, including an SPI master device, an SPI slave device, and a digital isolator U1, wherein the digital isolator U1 is connected between the SPI master device and the SPI slave device, wherein:

[0043] The A1 terminal of the digital isolator U1 is electrically connected to the SCK signal terminal of the SPI master device through resistor R1 and inductor L1. The common terminal of resistor R1 and inductor L1 is grounded through capacitor C2, and the common terminal of resistor R1 and A1 is grounded through capacitor C5.

[0044] The A2 terminal of the digital isolator U1 is electrically connected to the MOSI signal terminal of the SPI master device through resistor R2 and inductor L2. The common terminal of resistor R2 and inductor L2 is grounded through capacitor C3, and the common terminal of resistor R2 and A2 is grounded through capacitor C6.

[0045] The A3 terminal of the digital isolator U1 is electrically connected to the SS signal terminal of the SPI master device through resistor R3 and inductor L3. The common terminal of resistor R3 and inductor L3 is grounded through capacitor C4, and the common terminal of resistor R3 and A3 is grounded through capacitor C7.

[0046] The A4 terminal of the digital isolator U1 is electrically connected to the MISO signal terminal of the SPI master device through resistor R4, and the end of resistor R4 away from the A4 terminal is grounded through capacitor C1.

[0047] The B1 terminal of the digital isolator U1 is electrically connected to the SCK signal terminal of the SPI slave device through a resistor R6, and the end of the resistor R6 away from the B1 terminal is grounded through a capacitor C14.

[0048] The B2 terminal of the digital isolator U1 is electrically connected to the MOSI signal terminal of the SPI slave device through a resistor R7, and the end of the resistor R7 away from the B2 terminal is grounded through a capacitor C15.

[0049] The B3 terminal of the digital isolator U1 is electrically connected to the SS signal terminal of the SPI slave device through a resistor R8, and the end of the resistor R8 away from the B3 terminal is grounded through a capacitor C16.

[0050] The resistor R9 and inductor L4 at the B4 terminal of the digital isolator U1 are electrically connected to the MISO signal terminal of the SPI slave device. The common terminal of the resistor R9 and the inductor L4 is grounded through capacitor C8, and the common terminal of the resistor R9 and the B4 terminal is grounded through capacitor C13.

[0051] Specifically, the power supply voltage on side A of the digital isolator U1 is MVCC, where:

[0052] A capacitor C10 is connected between pin 1 and pin 2 of the digital isolator U1, and a capacitor C9 is connected in parallel across the two ends of the capacitor C10. One end of the capacitor C9 is connected to MVCC.

[0053] More specifically, the power supply voltage on side B of the digital isolator U1 is SVCC, where:

[0054] A capacitor C11 is connected between pins 15 and 16 of the digital isolator U1, and a capacitor C12 is connected in parallel across the two ends of the capacitor C11. One end of the capacitor C12 is connected to SVCC.

[0055] Furthermore, pin 7 of the digital isolator U1 is connected to MVCC via resistor R5.

[0056] Furthermore, pin 10 of the digital isolator U1 is connected to SVCC via resistor R10.

[0057] Regarding this utility model:

[0058] This utility model includes:

[0059] 1. Master control end (MCU side): includes SPI master device (such as MCU) and its driving circuit.

[0060] 2. Isolation Terminal (Isolation Module): A multi-channel digital isolator (such as NSI8141W1 from Suzhou Nanochip Microelectronics Co., Ltd., or π141E61 from Rongpai Semiconductor (Shanghai) Co., Ltd.) is used to achieve isolated transmission of SCK, MOSI, MISO, and SS signals.

[0061] 3. Peripheral side (Slave side): SPI slave device (such as sensor, expansion module, etc.).

[0062] 4. Optimize circuit design:

[0063] Power supply noise suppression:

[0064] Independent LDO power supplies are used on both sides of the isolation, namely MVCC and SVCC (such as MD5333).

[0065] Each power supply circuit is equipped with a π-type filter (10μF + 0.1μF + 1μF).

[0066] Impedance matching network: A 22Ω~100Ω resistor is connected in series on the SPI signal line to reduce signal reflection.

[0067] Low-pass filtering: Add RC filtering (such as 50Ω resistor + 10pF capacitor) to the input / output signal terminals of the isolator to suppress high-frequency noise.

[0068] Noise suppression: Add LC filtering (such as 33nH inductor + 10pF capacitor) to the input / output signal terminals of the isolator to suppress ultra-high frequency noise.

[0069] Common-mode choke: Add a common-mode inductor (such as the DLW21HN series) to the power line to suppress common-mode noise.

[0070] 5. PCB layout optimization:

[0071] Maintain a creepage distance of ≥8mm on both sides of the isolation zone (compliant with IEC 60664 standard).

[0072] Differential routing (such as LVDS) is used to optimize high-speed SCK and MOSI / MISO signals.

[0073] The area below the isolation zone is hollowed out to reduce parasitic capacitive coupling.

[0074] In embedded systems or microcontroller programming, SPI is a widely used serial communication protocol for high-speed, full-duplex data transmission between microcontrollers (such as ARM and PIC) and other peripheral devices (such as sensors and memory). The SPI communication protocol typically consists of four main signal lines:

[0075] 1. SCK: Serial Clock Line. This is a clock signal controlled by the master device, used for synchronizing data transmission. All devices share this clock line. In this design, this line is further filtered by an LC filter consisting of inductor L1 and capacitor C2, and by an RC filter consisting of resistor R1 and capacitor C5.

[0076] 2. MOSI: Master output, slave input. The master device sends data to the slave device through this line. In this design, the line is further filtered by an LC filter consisting of inductor L2 and capacitor C3, and by an RC filter consisting of resistor R2 and capacitor C6.

[0077] 3. MISO: Master input, slave output. The slave device sends data to the master device through this line. In this design, a primary RC filter with resistor R4 and capacitor C1 is added to this line.

[0078] 4. SS: Slave Select Line. Multiple slave devices can be connected to the bus, and different SS lines are used to select which slave device to communicate with. In some designs, multiple SS lines may be used to select different slave devices. This design provides LC primary filtering with inductor L3 and capacitor C4, and RC secondary filtering with resistor R3 and capacitor C7.

[0079] The improved circuit block diagram is as follows: Figure 1 As shown: A high-speed four-channel digital isolator is added between the SPI master and slave devices to ensure level matching of SPI communication between the master and slave devices.

[0080] The principle of this utility model is as follows:

[0081] The SCK signal from the SPI master device is filtered through two stages: LC (L1+C2) filtering and RC (R1+C5) filtering, before being connected to pin A1 of the digital isolator. The MOSI signal is filtered through two stages: LC (L2+C3) filtering and RC (R2+C6) filtering, before being connected to pin A2 of the digital isolator. The SS signal is filtered through two stages: LC (L3+C4) filtering and RC (R3+C7) filtering, before being connected to pin A3 of the digital isolator. The MISO signal is the signal output from the SPI slave device by the master device, isolated by digital isolator U1, filtered through an RC filter composed of (R4+C1) at pin A4, and then returned. The power supply voltage on side A of the digital isolator is MVCC. In summary, the logic inputs and logic outputs (SPI signals) of the SPI master device are connected to the A1~A4 signal pins of digital isolator U1 after being filtered through LC and RC stages.

[0082] The SCK signal from the SPI master device is isolated by digital isolator U1, output from terminal B1, filtered by RC (R6+C14), and then connected to the SCK3 signal port of the slave device. The MOSI signal is isolated by digital isolator U1, output from terminal B2, filtered by RC (R7+C15), and then connected to the MOSI3 signal port of the slave device. The SS signal is isolated by digital isolator U1, output from terminal B3, filtered by RC (R8+C16), and then connected to the SS3 signal port of the slave device. The MISO3 signal output from the SPI slave device is filtered by LC (L4+C8) and RC (R9+C13) filters before being connected to terminal B4 of digital isolator U1. The power supply voltage on side B of the digital isolator is SVCC. In summary, the logic inputs and logic outputs (SPI signals) of the SPI slave device are connected to the B1~B4 signal terminals of digital isolator U1 after RC filtering.

[0083] The data sending and receiving process is described below:

[0084] 1. Initialization: Before data transmission begins, the parameters of the SPI interface need to be configured, such as clock frequency and data bit width (usually 8 bits or more).

[0085] 2. Select Slave Device: Select one or more slave devices for communication via the SS line. Normally, the SS line is active high, meaning that by default, all slave devices are inactive. The selected slave device is activated by pulling the corresponding SS line low.

[0086] 3. Data Transmission: The master device outputs data bits to the MOSI line on the rising edge of SCK. On the falling edge of SCK, the slave device outputs data bits to the MISO line (if the slave device is the sender). Data is typically transmitted in frames, each containing a certain number of data bits, and frames are separated by the idle state of SCK.

[0087] 4. End communication: After communication is complete, you can end communication with the selected slave device by pulling the SS line high.

[0088] In this scheme, since the input and output levels of the high-speed four-channel digital isolator AB are only related to the power supply voltage on their respective sides, it plays a role in electrical isolation, ensuring the safety and reliability of the circuit.

[0089] It is worth mentioning that the technical features such as SPI involved in this utility model patent application should be regarded as prior art. The specific structure, working principle and possible control method and spatial arrangement of these technical features can be adopted by conventional choices in the field, and should not be regarded as the inventive point of this utility model patent. This utility model patent will not be further elaborated in detail.

[0090] For those skilled in the art, modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this utility model should be included within the protection scope of this utility model.

Claims

1. A high-speed SPI communication circuit based on a digital isolator, characterized in that, It includes an SPI master device, an SPI slave device, and a digital isolator U1, which is connected between the SPI master device and the SPI slave device. The A1 terminal of the digital isolator U1 is electrically connected to the SCK signal terminal of the SPI master device through resistor R1 and inductor L1. The common terminal of resistor R1 and inductor L1 is grounded through capacitor C2, and the common terminal of resistor R1 and A1 is grounded through capacitor C5. The A2 terminal of the digital isolator U1 is electrically connected to the MOSI signal terminal of the SPI master device through resistor R2 and inductor L2. The common terminal of resistor R2 and inductor L2 is grounded through capacitor C3, and the common terminal of resistor R2 and A2 is grounded through capacitor C6. The A3 terminal of the digital isolator U1 is electrically connected to the SS signal terminal of the SPI master device through resistor R3 and inductor L3. The common terminal of resistor R3 and inductor L3 is grounded through capacitor C4, and the common terminal of resistor R3 and A3 is grounded through capacitor C7. The A4 terminal of the digital isolator U1 is electrically connected to the MISO signal terminal of the SPI master device through resistor R4, and the end of resistor R4 away from the A4 terminal is grounded through capacitor C1. The B1 terminal of the digital isolator U1 is electrically connected to the SCK signal terminal of the SPI slave device through a resistor R6, and the end of the resistor R6 away from the B1 terminal is grounded through a capacitor C14. The B2 terminal of the digital isolator U1 is electrically connected to the MOSI signal terminal of the SPI slave device through a resistor R7, and the end of the resistor R7 away from the B2 terminal is grounded through a capacitor C15. The B3 terminal of the digital isolator U1 is electrically connected to the SS signal terminal of the SPI slave device through a resistor R8, and the end of the resistor R8 away from the B3 terminal is grounded through a capacitor C16. The resistor R9 and inductor L4 at the B4 terminal of the digital isolator U1 are electrically connected to the MISO signal terminal of the SPI slave device. The common terminal of the resistor R9 and the inductor L4 is grounded through capacitor C8, and the common terminal of the resistor R9 and the B4 terminal is grounded through capacitor C13.

2. The high-speed SPI communication circuit based on a digital isolator according to claim 1, characterized in that, The power supply voltage on side A of the digital isolator U1 is MVCC, where: A capacitor C10 is connected between pin 1 and pin 2 of the digital isolator U1, and a capacitor C9 is connected in parallel across the two ends of the capacitor C10. One end of the capacitor C9 is connected to MVCC.

3. The high-speed SPI communication circuit based on a digital isolator according to claim 1, characterized in that, The power supply voltage on side B of the digital isolator U1 is SVCC, where: A capacitor C11 is connected between pins 15 and 16 of the digital isolator U1, and a capacitor C12 is connected in parallel across the two ends of the capacitor C11. One end of the capacitor C12 is connected to SVCC.

4. The high-speed SPI communication circuit based on a digital isolator according to claim 2, characterized in that, Pin 7 of the digital isolator U1 is connected to MVCC via resistor R5.

5. The high-speed SPI communication circuit based on a digital isolator according to claim 3, characterized in that, Pin 10 of the digital isolator U1 is connected to SVCC via resistor R10.

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