Power converter circuit and control circuit therefor
By introducing proportional-integral circuits, ramp generation circuits, and comparator circuits into the power converter circuit, trigger pulse signals are generated to adjust the frequency of the power stage circuit, solving the problem of unstable output voltage of multiphase power converters under load transients, and achieving fast response and improved stability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- POWERX SEMICONDUCTOR CORPORATION
- Filing Date
- 2025-05-29
- Publication Date
- 2026-06-26
Smart Images
Figure CN224418673U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to a control circuit, and more particularly to a control circuit suitable for power converter circuits. Background Technology
[0002] With the development of semiconductor technology, the response capability of multiphase power converter circuits to load transients has become increasingly important. Some related technologies use proportional-integral (PI) controllers to generate signals and compare these signals with signals of specific waveforms such as ramps, ripples, and sawtooth waves to stabilize the output voltage of the multiphase power converter circuit under load transients. However, the PPI controllers used in these technologies are usually simple in architecture and difficult to achieve optimal settings. Therefore, it is necessary to propose new methods to solve the above problems. Utility Model Content
[0003] One embodiment of this invention is a control circuit suitable for a power converter circuit. The control circuit includes a proportional-integral (PI) circuit, a ramp generation circuit, and a comparator circuit. The PI circuit is coupled to the voltage output terminal of the power converter circuit and outputs a proportional compensation signal and an integral compensation signal based on a reference signal and a feedback signal associated with the voltage output terminal. The ramp generation circuit outputs a reference ramp signal and a ramp signal based on the reference signal. The comparator circuit is coupled to the PI circuit and the ramp generation circuit and receives the proportional compensation signal, the integral compensation signal, the reference ramp signal, and the ramp signal to output a trigger pulse signal. It generates a pulse in the trigger pulse signal when a first sum of the integral compensation signal and the ramp signal is greater than a second sum of the proportional compensation signal and the reference ramp signal.
[0004] In some embodiments, the proportional-integral circuit includes a proportional circuit and an integral circuit. The proportional circuit receives the reference signal and the feedback signal, and scales a first difference between the feedback signal and the reference signal to output the proportional compensation signal. The integral circuit receives the reference signal and the feedback signal, and integrates a second difference between the reference signal and the feedback signal to output the integral compensation signal.
[0005] In some embodiments, the proportional circuit includes an amplifier circuit, a first resistor, and a second resistor. The non-inverting input of the amplifier circuit receives the feedback signal. A first terminal of the first resistor receives the reference signal, and a second terminal of the first resistor is coupled to the inverting input of the amplifier circuit. A first terminal of the second resistor is coupled to the second terminal of the first resistor and the inverting input of the amplifier circuit, and a second terminal of the second resistor is coupled to the output of the amplifier circuit. The output of the amplifier circuit outputs the proportional compensation signal.
[0006] In some embodiments, the integrating circuit includes a transconductance amplifier circuit and a capacitor. The non-inverting input of the transconductance amplifier circuit receives the reference signal, while the inverting input receives the feedback signal. A first terminal of the capacitor is coupled to the output of the transconductance amplifier circuit, and a second terminal is coupled to ground. The output of the transconductance amplifier circuit outputs the integration compensation signal.
[0007] In some embodiments, the proportional-integral circuit includes an arithmetic circuit, an inverting circuit, an integrating circuit, and a proportional circuit. The arithmetic circuit receives the reference signal and the feedback signal, and outputs a first error signal indicating the difference between the reference signal and the feedback signal. The inverting circuit is coupled to the arithmetic circuit and performs an inverse operation on the first error signal to output a second error signal. The integrating circuit is coupled to the arithmetic circuit and performs an integral operation on the first error signal to output an integral compensation signal. The proportional circuit is coupled to the inverting circuit and scales the second error signal to output a proportional compensation signal.
[0008] In some embodiments, the ramp generation circuit includes a capacitor, a transconductance amplifier circuit, and a reset circuit. The capacitor is coupled to a first node and a ground terminal, wherein the ramp signal is output from the first node. The transconductance amplifier circuit is coupled to the first node to receive the reference signal and convert the reference signal into a reference current to charge the capacitor, causing the voltage level of the ramp signal to rise according to a preset slope. The reset circuit is coupled to the first node and the ground terminal to generate a discharge path between the first node and the ground terminal in response to a pulse in the trigger pulse signal, causing the voltage level of the ramp signal to drop to the ground voltage of the ground terminal.
[0009] In some embodiments, the transconductance amplifier circuit includes a current generation circuit and a current mirror circuit. The current generation circuit generates a first current flowing through the second node and the third node based on the reference signal, and generates the reference ramp signal at the third node based on the first current. The current mirror circuit is coupled to the second node and the first node, and generates the reference current to the first node based on the first current.
[0010] In some embodiments, the comparison circuit includes a comparator and a pulse generation circuit. The comparator compares the proportional compensation signal, the integral compensation signal, the reference ramp signal, and the ramp signal to output a comparison signal. The first inverting input of the comparator receives the reference ramp signal, the second inverting input receives the proportional compensation signal, the first non-inverting input receives the integral compensation signal, and the second non-inverting input receives the ramp signal. The pulse generation circuit is coupled to the output of the comparator and generates a trigger pulse signal based on the voltage level of the comparison signal.
[0011] In some embodiments, the comparison circuit includes a first operational circuit, a second operational circuit, a comparator, and a pulse generation circuit. The first operational circuit is coupled to the proportional-integral circuit and receives the proportional compensation signal and the reference ramp signal, and generates a first operational signal indicating the second sum associated with the proportional compensation signal and the reference ramp signal. The second operational circuit is coupled to the proportional-integral circuit and receives the integral compensation signal and the ramp signal, and generates a second operational signal indicating the first sum associated with the integral compensation signal and the ramp signal. The comparator compares the first operational signal and the second operational signal to output a comparison signal, wherein the inverting input of the comparator receives the first operational signal, and the non-inverting input of the comparator receives the second operational signal. The pulse generation circuit is coupled to the output of the comparator and generates a trigger pulse signal based on the voltage level of the comparison signal.
[0012] Another aspect of this utility model is a power converter circuit. This power converter circuit receives an input voltage at a voltage input terminal and outputs an output voltage at a voltage output terminal. The power converter circuit includes a power stage circuit and a control circuit. The power stage circuit is coupled to the voltage input terminal and connected to the voltage output terminal via an inductor. The control circuit is coupled to the power stage circuit and the voltage output terminal, and generates a proportional compensation signal, an integral compensation signal, a reference ramp signal, and a ramp signal based on a reference signal and a feedback signal associated with the output voltage. When the first sum of the integral compensation signal and the ramp signal is greater than the second sum of the proportional compensation signal and the reference ramp signal, the control circuit adjusts the operating frequency of the power stage circuit to increase the output voltage.
[0013] In summary, by using a proportional compensation signal that responds similarly to changes in output voltage, the control circuit allows the power stage circuit to adjust its operating frequency in a timely manner to quickly stabilize the output voltage. Furthermore, the integral compensation signal, ramp signal, and reference ramp signal also contribute to the operational stability of the control circuit. Therefore, the control circuit and power converter circuit of this invention offer advantages such as superior load transient response capability. Attached Figure Description
[0014] Figure 1 This is a circuit diagram illustrating a power converter circuit according to some embodiments of the present invention.
[0015] Figure 2 This is a circuit diagram illustrating a control circuit based on some embodiments of the present invention.
[0016] Figure 3 This is a circuit diagram illustrating a proportional-integral circuit according to some embodiments of the present invention.
[0017] Figure 4 This is a circuit diagram illustrating a ramp generation circuit based on some embodiments of the present invention.
[0018] Figure 5 The following is a timing diagram of some signals in a power converter circuit illustrated according to some embodiments of the present invention.
[0019] Figure 6 Illustrations based on some embodiments of the present utility model Figure 5 A magnified view of a certain time period.
[0020] Figure 7 Illustrations based on some embodiments of the present utility model Figure 5 A magnified view of another time period.
[0021] Figure 8 The circuit diagrams for the proportional-integral circuit, the ramp generation circuit, and the comparator circuit are illustrated according to some embodiments of the present invention.
[0022] Figure 9 This is a circuit diagram illustrating a ramp generation circuit based on some embodiments of the present invention. Detailed Implementation
[0023] The following detailed description of embodiments, in conjunction with the accompanying drawings, is provided. However, the specific embodiments described are only for explaining this case and are not intended to limit this case. The description of the structural operations is not intended to limit the order of their execution. Any structure resulting from the recombination of elements and producing a device with equivalent functionality is within the scope of this utility model.
[0024] Unless otherwise specified, the terms used throughout the specification and claims generally have their ordinary meaning in the context of the art, the content disclosed herein, and the specific content.
[0025] The terms "coupled" or "connected" as used in this article can refer to two or more components making direct physical or electrical contact with each other, or making indirect physical or electrical contact with each other, or to two or more components operating or moving together.
[0026] Please see Figure 1 , Figure 1 This is a circuit diagram illustrating a power converter circuit 100 according to some embodiments of the present invention. In some embodiments, the power converter circuit 100 is used to receive an input voltage VIN at the voltage input terminal NIN and to output an output voltage VOUT at the voltage output terminal NOUT according to the input voltage VIN, so as to supply power to loads such as central processing units (CPUs) (not shown in the figure). Specifically, the power converter circuit 100 can be implemented by a DC / DC converter such as a buck converter.
[0027] At Figure 1 In this embodiment, the power converter circuit 100 includes a power stage circuit 10, a control circuit 20, and a conduction time generation circuit 30. The power stage circuit 10 is electrically coupled to the voltage input terminal NIN and the ground terminal GND to receive the input voltage VIN and the ground voltage (not shown) from the voltage input terminal NIN and the ground terminal GND, respectively. The power stage circuit 10 is also coupled to the voltage output terminal NOUT via an inductor L.
[0028] In some embodiments, the power stage circuit 10 includes a drive circuit 11, a high-side switch 12, and a low-side switch 13. The high-side switch 12 is coupled between the voltage input terminal NIN (or input voltage VIN) and the inductor L, while the low-side switch 13 is coupled between the inductor L and the ground terminal GND (or ground voltage). The drive circuit 11 controls the generation of a high-side drive signal VGH and a low-side drive signal VGL via a control signal CS (e.g., a pulse width modulation signal) to alternately turn on the high-side switch 12 and the low-side switch 13, respectively, so that phase current (not shown) flows through the inductor L. For example, the phase current may flow from the voltage input terminal NIN into the inductor L during the enable period of the control signal CS (e.g., during the conduction period of the high-side switch 12), or it may flow from the inductor L into the ground terminal GND during the disable period of the control signal CS (e.g., during the conduction period of the low-side switch 13). It should be understood that the frequency at which the high-side switch 12 and the low-side switch 13 alternately conduct can be determined according to the duty cycle of the control signal CS. Specifically, the high-side switch 12 and the low-side switch 13 can each be implemented by a transistor, but this invention is not limited thereto.
[0029] For example Figure 1 As shown, one end of the decoupling capacitor CO is connected to the inductor L and the voltage output terminal NOUT, while the other end of the decoupling capacitor CO is connected to the ground terminal GND, thereby optimizing the response capability of the power converter circuit 100 to load transients. For example, in some practical applications, the load may require a larger operating current due to temporary changes in the task (e.g., running a specific application and / or software). Therefore, the power converter circuit 100 needs to increase the magnitude of the phase current. Due to some non-ideal factors, the phase current cannot immediately increase to the operating current value required by the load. At this time, the decoupling capacitor CO, which is electrically coupled to the voltage output terminal NOUT, will discharge to compensate for the insufficient phase current. However, the discharge of the decoupling capacitor CO causes the output voltage VOUT to undershoot.
[0030] In view of this, in some embodiments, the control circuit 20 and the conduction time generation circuit 30 are coupled between the voltage output terminal NOUT and the power stage circuit 10 to form a feedback loop. Through this feedback loop, the power converter circuit 100 can improve the undershoot phenomenon of the output voltage VOUT, the principle of which will be further explained in later paragraphs.
[0031] In some embodiments, the control circuit 20 is coupled to the voltage output terminal NOUT to obtain a feedback signal VFB. For example, the control circuit 20 may be directly connected to the voltage output terminal NOUT and receive the output voltage VOUT from the voltage output terminal NOUT as the feedback signal VFB. In another example, the control circuit 20 may be connected to the voltage output terminal NOUT via a feedback circuit (not shown) and receive a signal (not shown) that is proportional to the output voltage VOUT as the feedback signal VFB. In short, the feedback signal VFB is associated with the voltage output terminal NOUT and / or the output voltage VOUT and can reflect changes in the output voltage VOUT.
[0032] As stated above, Figure 1 As shown, the control circuit 20 includes a proportional-integral circuit 21, a ramp generation circuit 23, and a comparator circuit 25. The proportional-integral circuit 21 is coupled to the voltage output terminal NOUT and is used to receive the reference signal VDAC and the feedback signal VFB, and to output a proportional compensation signal PCOMP and an integral compensation signal ICOMP based on the reference signal VDAC and the feedback signal VFB. The ramp generation circuit 23 receives the reference signal VDAC and outputs a reference ramp signal RREF and a ramp signal RAMP based on the reference signal VDAC. Furthermore, the comparator circuit 25 is coupled to the proportional-integral circuit 21 and the ramp generation circuit 23, and is used to receive the proportional compensation signal PCOMP, the integral compensation signal ICOMP, the reference ramp signal RREF, and the ramp signal RAMP, and to generate and output a trigger pulse signal DTY based on the proportional compensation signal PCOMP, the integral compensation signal ICOMP, the reference ramp signal RREF, and the ramp signal RAMP. In this embodiment, the trigger pulse signal DTY includes multiple pulses.
[0033] In some embodiments, the on-time generation circuit 30 is coupled to the comparator circuit 25 in the control circuit 20 to receive the trigger pulse signal DTY from the comparator circuit 25, and is coupled to the drive circuit 11 in the power stage circuit 10 to output a control signal CS to the drive circuit 11. Specifically, in response to multiple pulses in the trigger pulse signal DTY, the on-time generation circuit 30 controls the power stage circuit 10 to increase the frequency at which the high-side switch 12 and the low-side switch 13 alternately turn on by adjusting (e.g., increasing) the duty cycle of the control signal CS, so that the output voltage VOUT increases and stabilizes. In other words, multiple pulses in the trigger pulse signal DTY are used to trigger the on-time generation circuit 30 to increase the operating frequency of the power stage circuit 10.
[0034] Following the description of the aforementioned practical application, the output voltage VOUT decreases significantly due to load variations (i.e., the output voltage VOUT experiences undershoot). In some embodiments, this primarily affects the proportional compensation signal PCOMP, which is output based on the reference signal VDAC and the feedback signal VFB. For example, the value of the proportional compensation signal PCOMP (e.g., voltage level) may decrease significantly. In response to the decrease in the proportional compensation signal PCOMP, the comparator circuit 25 increases the pulse generation frequency of the trigger pulse signal DTY (i.e., increases the occurrence frequency of the multiple pulses contained in the trigger pulse signal DTY), thereby causing the output voltage VOUT to increase rapidly (i.e., the undershoot of the output voltage VOUT is improved).
[0035] As described in the above embodiments, the value of the proportional compensation signal PCOMP increases as the output voltage VOUT increases. In response to the increase in the proportional compensation signal PCOMP, the comparator circuit 25 reduces the pulse generation frequency of the trigger pulse signal DTY, or stops generating multiple pulses in the trigger pulse signal DTY until the conduction time generation circuit 30 resumes operation, thereby allowing the output voltage VOUT to return to a steady state. For example, the output voltage VOUT in the steady state may have a voltage level close to or the same as the reference signal VDAC. That is, the reference signal VDAC may be a preset voltage value, and the preset voltage value may serve as the target for the output voltage VOUT.
[0036] As can be seen from the above description of the embodiments, the control circuit 20 is used to generate a proportional compensation signal PCOMP, an integral compensation signal ICOMP, a reference ramp signal RREF, and a ramp signal RAMP based on the reference signal VDAC and the feedback signal VFB, and is used to trigger the on-time generation circuit 30 to increase or decrease the operating frequency of the power stage circuit 10 based on the proportional compensation signal PCOMP, the integral compensation signal ICOMP, the reference ramp signal RREF, and the ramp signal RAMP.
[0037] Next, the pairing Figure 2 Further explanation is provided regarding the proportional-integral circuit 21, the ramp generation circuit 23, and the comparator circuit 25 within the control circuit 20. Please refer to [link / reference needed]. Figure 2 , Figure 2 The circuit diagram of the control circuit 20 is shown according to some embodiments of the present invention.
[0038] At Figure 2 In this embodiment, the proportional-integral circuit 21 includes a proportional circuit 211 and an integral circuit 213. Please refer to... Figure 3 , Figure 3The diagram illustrates a proportional-integral circuit 21 according to some embodiments of the present invention. In some embodiments, the proportional circuit 211 includes an amplifier circuit AOPP and multiple resistors R1 and R2. The amplifier circuit AOPP can be implemented using an operational amplifier. The non-inverting input terminal of the amplifier circuit AOPP (in...) Figure 3 The resistor R1 (represented by the symbol "+") is used to receive the feedback signal VFB. The first terminal of resistor R1 receives the reference signal VDAC, while the second terminal of resistor R1 is coupled to the inverting input of the amplifier circuit AOPP (in...). Figure 3 (The symbol "-" is used to indicate this). The first end of resistor R2 is coupled to the second end of resistor R1 and the inverting input of amplifier circuit AOPP, while the second end of resistor R2 is coupled to the output of amplifier circuit AOPP. With this configuration, the value of the proportional compensation signal PCOMP can be calculated using the following formula (1).
[0039]
[0040] As described above, the proportional circuit 211 receives the reference signal VDAC and the feedback signal VFB, and scales the difference between the feedback signal VFB and the reference signal VDAC to output a proportional compensation signal PCOMP. In this embodiment, the resistor R2 is implemented as a variable resistor to adjust the gain of the proportional circuit 211.
[0041] In some embodiments, the integrator circuit 213 includes a transconductance amplifier circuit AGMI and a capacitor C1. The transconductance amplifier circuit AGMI can be implemented using a transconductance amplifier. The non-inverting input of the transconductance amplifier circuit AGMI is used to receive a reference signal VDAC, and its inverting input is used to receive a feedback signal VFB. The first end of the capacitor C1 is coupled to the output of the transconductance amplifier circuit AGMI, and the second end of the capacitor C1 is coupled to ground GND. With this configuration, the transconductance amplifier circuit AGMI can perform voltage-to-current conversion based on the reference signal VDAC and the feedback signal VFB to generate a current signal (not shown) corresponding to the reference signal VDAC minus the feedback signal VFB. Furthermore, the capacitor C1 is charged by this current signal, causing the integration compensation signal ICOMP to be generated at the output of the transconductance amplifier circuit AGMI.
[0042] As can be seen from the above description of the integrator circuit 213, the integrator circuit 213 is used to receive the reference signal VDAC and the feedback signal VFB, and to perform an integration operation on the difference between the reference signal VDAC and the feedback signal VFB, so as to output the integration compensation signal ICOMP.
[0043] For example Figure 2As shown, in some embodiments, the ramp generation circuit 23 includes a transconductance amplifier circuit 231, a capacitor 233, and a reset circuit 235. The transconductance amplifier circuit 231, capacitor 233, and reset circuit 235 are all coupled to node NR. Next, the matching... Figure 4 Further explanation of the ramp generation circuit 23.
[0044] Please see Figure 4 , Figure 4 This is a circuit diagram illustrating a ramp generation circuit 23 according to some embodiments of the present invention. In some embodiments, the transconductance amplifier circuit 231 includes an amplifier circuit AOPR, a resistor R3, and multiple transistors M1 to M3. The amplifier circuit AOPR can be implemented using an operational amplifier, transistor M1 can be implemented using an N-type metal-oxide-semiconductor transistor, and transistors M2 and M3 can each be implemented using P-type metal-oxide-semiconductor transistors. The non-inverting input of the amplifier circuit AOPR is used to receive a reference signal VDAC, and its inverting input is coupled to node NP. The first terminal (e.g., the source terminal) of transistor M1 is coupled to node NP. Resistor R3 is coupled to node NP and ground GND. The output terminal of the amplifier circuit AOPR is coupled to the control terminal (e.g., the gate terminal) of transistor M1. The second terminal (e.g., the drain terminal) of transistor M1 is coupled to node NQ. The second terminal of transistor M2, the control terminal of transistor M2, and the control terminal of transistor M3 are all coupled to node NQ. The first terminals of transistors M2 and M3 are used to receive a suitable power supply voltage VCC. The second terminal of transistor M3 is coupled to node NR.
[0045] In the above configuration, the amplifier circuit AOPR controls the transistor M1 to turn on based on the reference signal VDAC at its non-inverting input. When transistor M1 is turned on, current I1 is generated and flows sequentially through transistor M2, node NQ, transistor M1, node NP, and resistor R3, thereby generating a first voltage signal (not shown in the figure) at node NP (or at the inverting input of the amplifier circuit AOPR) as a reference ramp signal RREF. A negative feedback path is formed between the output and inverting input of the amplifier circuit AOPR through transistor M1, ultimately making the reference ramp signal RREF substantially the same as the reference signal VDAC. That is, the voltage level of the reference ramp signal RREF is substantially the same as the voltage value of the reference signal VDAC. Simultaneously, the current level of current I1 is the voltage value of the reference signal VDAC divided by the resistance value of resistor R3. Furthermore, based on current I1, the transconductance amplifier circuit 231 generates a current I2 flowing through transistor M3 that is substantially the same as current I1.
[0046] As described above regarding the transconductance amplifier circuit 231, the amplifier circuit AOPR, transistor M1, and resistor R3 can form a current generation circuit. This current generation circuit generates a current I1 sequentially flowing through transistor M2, transistor M1, and resistor R3 based on the reference signal VDAC, and generates a reference ramp signal RREF at node NP based on the current I1 and the resistance value of resistor R3. Furthermore, transistors M2 and M3 can form a current mirror circuit. This current mirror circuit is coupled to nodes NQ and NR and is used to replicate current I1 to generate current I2 as a reference current to node NR. It should be understood that the current level of the reference current (or current I2) is also related to the voltage value of the reference signal VDAC divided by the resistance value of resistor R3. For example, the current level of the reference current may be substantially the same as the voltage value of the reference signal VDAC divided by the resistance value of resistor R3, or it may be proportional to the voltage value of the reference signal VDAC divided by the resistance value of resistor R3.
[0047] like Figure 2 and Figure 4 As shown, capacitor 233 is coupled to node NR and ground GND. The reset circuit 235 can be implemented using an N-type metal-oxide-semiconductor transistor. Accordingly, the first terminal of the reset circuit 235 (e.g., the source terminal of the transistor) is coupled to ground GND, the second terminal of the reset circuit 235 (e.g., the drain terminal of the transistor) is coupled to node NR, and the control terminal of the reset circuit 235 (e.g., the gate terminal of the transistor) can be coupled to comparator circuit 25 to receive the trigger pulse signal DTY.
[0048] In the above configuration, when the reset circuit 235 does not receive any pulse in the trigger pulse signal DTY (that is, when no pulse occurs on the trigger pulse signal DTY), the transistor in the reset circuit 235 will switch to the off state. In this case, the capacitor 233 is charged via the reference current (or current I2) to generate a second voltage signal (not shown) as a ramp signal RAMP at node NR. Specifically, during the charging of the capacitor 233, the voltage level of the ramp signal RAMP may rise according to a preset slope (which is determined by the reference current and the capacitance value of the capacitor 233). Furthermore, when the reset circuit 235 receives a pulse of the trigger pulse signal DTY (that is, when a pulse occurs on the trigger pulse signal DTY), the transistor in the reset circuit 235 will switch to the on state. In this case, the capacitor 233 discharges towards the ground terminal GND through the on transistor. During the discharge of the capacitor 233, the voltage level of the ramp signal RAMP will drop to the ground voltage of the ground terminal GND.
[0049] Depend on Figure 4As described in the embodiments, in some embodiments, the transconductance amplifier circuit 231 is used to receive the reference signal VDAC and convert the reference signal VDAC into a reference current to charge the capacitor 233 through the reference current, so that the voltage level of the ramp signal RAMP rises according to a preset slope. The reset circuit 235 is used to generate a discharge path between node NR and ground terminal GND in response to the pulse in the trigger pulse signal DTY, so that the voltage level of the ramp signal RAMP drops to the ground voltage of ground terminal GND. According to the above, the resistance value of resistor R3 is related to the generation of the ramp signal RAMP. In this embodiment, resistor R3 is implemented as a variable resistor. By changing the resistance value of resistor R3, the pulse generation frequency of the ramp signal RAMP (e.g., the occurrence frequency of multiple ramp pulses of the ramp signal RAMP) can be adjusted so that it can match the frequency of the core voltage (Vcore) of the system including the power converter circuit 100.
[0050] For example Figure 2 As shown, in some embodiments, the comparison circuit 25 includes a comparator 251, a latching circuit 253, and a delay circuit 255. The first inverting input of the comparator 251 can be coupled to node NP in the ramp generation circuit 23 to receive a reference ramp signal RREF. The second inverting input of the comparator 251 can be coupled to the proportional circuit 211 in the proportional-integral circuit 21 to receive a proportional compensation signal PCOMP. The first non-inverting input of the comparator 251 can be coupled to the integrating circuit 213 in the proportional-integral circuit 21 to receive an integral compensation signal ICOMP. The second non-inverting input of the comparator 251 can be coupled to node NR in the ramp generation circuit 23 to receive a ramp signal RAMP. The output of the comparator 251 is coupled to the setting terminal S of the latching circuit 253. The output Q of the latching circuit 253 can be coupled to... Figure 1 The on-time generation circuit 30 is connected to the input terminal of the delay circuit 255. The reset terminal R of the latch circuit 253 is coupled to the output terminal of the delay circuit 255.
[0051] In the above configuration, the comparator circuit 25 compares the proportional compensation signal PCOMP, the integral compensation signal ICOMP, the reference ramp signal RREF, and the ramp signal RAMP to output a comparator signal COM1. Specifically, when the sum of the integral compensation signal ICOMP and the ramp signal RAMP minus the sum of the proportional compensation signal PCOMP and the reference ramp signal RREF is greater than 0, the comparator signal COM1 has an enable level (e.g., a voltage level corresponding to logic "1"). When the sum of the integral compensation signal ICOMP and the ramp signal RAMP minus the sum of the proportional compensation signal PCOMP and the reference ramp signal RREF is not greater than 0, the comparator signal COM1 has a disable level (e.g., a voltage level corresponding to logic "0").
[0052] The latching circuit 253 determines the voltage level of its output terminal Q based on the voltage levels of its setting terminal S and reset terminal R. For example, when the comparator signal COM1 is at the enable level and the reset terminal R is at the disable level, the latching circuit 253 controls the output terminal Q to become the enable level, thereby generating one pulse in the trigger pulse signal DTY. When the output terminal Q becomes the enable level, the delay circuit 255 times a preset time, and after the preset time has elapsed, it enables the reset terminal R, causing the latching circuit 253 to control the output terminal Q to become the disable level. Therefore, the width of each pulse in the trigger pulse signal DTY is the preset time length. After generating one pulse in the trigger pulse signal DTY, the delay circuit 255 disables the reset terminal R. Next, the latching circuit 253 can control the output terminal Q to remain at the disabled level when the setting terminal S (or the comparison signal COM1) is at the disabled level, or it can control the output terminal Q to become the enabled level again when the setting terminal S (or the comparison signal COM1) is at the enabled level, so as to generate the next pulse in the trigger pulse signal DTY.
[0053] As can be seen from the description of latch circuit 253 and delay circuit 255, latch circuit 253 and delay circuit 255 can form a pulse generation circuit 257. This pulse generation circuit 257 can generate a trigger pulse signal DTY based on the voltage level of comparison signal COM1.
[0054] Furthermore, as can be seen from the description of comparator 251, latch circuit 253, and delay circuit 255, in some embodiments, comparator circuit 25 is used to generate at least one pulse of trigger pulse signal DTY when the sum of integral compensation signal ICOMP and ramp signal RAMP is greater than the sum of proportional compensation signal PCOMP and reference ramp signal RREF. In other cases, comparator circuit 25 does not generate any pulse on trigger pulse signal DTY (i.e., no pulse occurs on trigger pulse signal DTY).
[0055] Next, pair Figure 5 , Figure 6 and Figure 7 Further explanation of the relationship between the output voltage VOUT, the proportional compensation signal PCOMP, the integral compensation signal ICOMP, the reference ramp signal RREF, and the ramp signal RAMP. Figure 5 The following is a timing diagram of some signals in a power converter circuit 100 according to some embodiments of the present invention. Figure 6 and Figure 7 They are respectively Figure 5 Enlarged view of SN1 and SN2 in the mid-time period.
[0056] In some embodiments, such as Figure 5As shown, during time period SN1, the voltage level of the output voltage VOUT is lower than its steady-state voltage level (e.g., the voltage value of the reference signal VDAC) due to load variations. From the aforementioned equation (1), it can be seen that the voltage level of the output voltage VOUT significantly affects the voltage level of the proportional compensation signal PCOMP. Therefore, as... Figure 5 , Figure 6 As shown, the voltage level of the proportional compensation signal PCOMP is significantly lower than the voltage level of the integral compensation signal ICOMP, which further causes the sum of the integral compensation signal ICOMP and the ramp signal RAMP to be greater than the sum of the proportional compensation signal PCOMP and the reference ramp signal RREF. According to the above description of the comparator circuit 25, in this case, the comparator circuit 25 increases the pulse generation frequency of the trigger pulse signal DTY, and the pulse generation frequency of the trigger pulse signal DTY is determined by the operation of the latch circuit 253 and the delay circuit 255. Furthermore, the generation of any pulse in the trigger pulse signal DTY also triggers the reset circuit 235 in the ramp generation circuit 23 to reset the voltage level of the ramp signal RAMP to the ground voltage of the ground terminal GND. During time period SN1, due to the increased pulse generation frequency of the trigger pulse signal DTY, the voltage level of the ramp signal RAMP only increases slightly before decreasing back to the ground voltage (i.e., the maximum amplitude that the ramp signal RAMP can actually achieve is reduced), and therefore does not exceed the voltage level of the reference ramp signal RREF.
[0057] like Figure 1 In the embodiment, the conduction time generation circuit 30 also increases the operating frequency of the power stage circuit 10 because the pulse generation frequency of the trigger pulse signal DTY is increased. Therefore, as... Figure 5 As shown, the output voltage VOUT increases during time period SN1, and during the subsequent time period SN1, it recovers to its steady-state voltage level through the operation of the power stage circuit 10, control circuit 20 and conduction time generation circuit 30 in the aforementioned power converter circuit 100.
[0058] In some embodiments, such as Figure 5 As shown, during time period SN2, the voltage level of the output voltage VOUT remains at its steady-state voltage level (e.g., the voltage value of the reference signal VDAC). Therefore, there is no significant difference between the voltage level of the proportional compensation signal PCOMP and the voltage level of the integral compensation signal ICOMP. In this case, as... Figure 7 As shown, the sum of the integral compensation signal ICOMP and the ramp signal RAMP will only be greater than the sum of the proportional compensation signal PCOMP and the reference ramp signal RREF when the ramp signal RAMP rises to a level exceeding the reference ramp signal RREF according to a preset slope. In other words, the comparator circuit 25 keeps the pulse generation frequency of the trigger pulse signal DTY stable without increasing it.
[0059] It should be understood that the proportional-integral circuit 21, the ramp generation circuit 23, and / or the comparator circuit 25 of this utility model are not limited to... Figure 2 The circuit architecture is shown. For example, please refer to [link to example circuit architecture]. Figure 8 , Figure 8 The diagram illustrates the proportional-integral circuit 21, the ramp generation circuit 23, and the comparator circuit 25 according to some embodiments of the present invention. Figure 8 In one embodiment, the proportional-integral circuit 21 includes a proportional circuit 811, an integral circuit 813, an inverting circuit 815, and an arithmetic circuit 817.
[0060] In some embodiments, the arithmetic circuit 817 can be implemented using circuit elements such as adders and subtractors, while the inverting circuit 815 can be implemented using an inverter. The arithmetic circuit 817 receives a reference signal VDAC and a feedback signal VFB, and performs a subtraction operation on the reference signal VDAC using the feedback signal VFB to output an error signal ER1. The inverting circuit 815 is coupled to the arithmetic circuit 817 and is used to perform an inverse (NOT) operation on the error signal ER1 to output an error signal ER2. It should be understood that the error signal ER1 may indicate the difference associated with the reference signal VDAC minus the feedback signal VFB, while the error signal ER2 may indicate the difference associated with the feedback signal VFB minus the reference signal VDAC.
[0061] In some embodiments, the integrator circuit 813 can be implemented using circuit elements such as a transconductance amplifier and a capacitor, while the proportional circuit 811 can be implemented using circuit elements such as an operational amplifier and a resistor. The integrator circuit 813 is coupled to the operational circuit 817 to receive the error signal ER1 from the operational circuit 817 and to perform integration on the error signal ER1 to output the integral compensation signal ICOMP. The proportional circuit 811 is coupled to the inverting circuit 815 to receive the error signal ER2 from the inverting circuit 815 and to perform proportional scaling on the error signal ER2 to output the proportional compensation signal PCOMP.
[0062] Also, at Figure 8In some embodiments, the comparator circuit 25 includes an arithmetic circuit 851, an arithmetic circuit 853, a comparator 855, and a pulse generation circuit 857. In some embodiments, the arithmetic circuits 851 and 853 can be implemented using circuit elements such as adders and subtractors. The arithmetic circuit 851 is coupled to the proportional circuit 811 in the proportional-integral circuit 21 to receive the proportional compensation signal PCOMP, and is coupled to the ramp generation circuit 23 to receive the reference ramp signal RREF. The arithmetic circuit 851 adds the proportional compensation signal PCOMP to the reference ramp signal RREF to generate the arithmetic signal SUM1. The arithmetic circuit 853 is coupled to the integral circuit 813 in the proportional-integral circuit 21 to receive the integral compensation signal ICOMP, and is coupled to the ramp generation circuit 23 to receive the ramp signal RAMP. The arithmetic circuit 853 adds the integral compensation signal ICOMP to the ramp signal RAMP to generate the arithmetic signal SUM2. Therefore, the operation signal SUM1 can indicate the sum associated with the reference ramp signal RREF plus the proportional compensation signal PCOMP, while the operation signal SUM2 can indicate the sum associated with the ramp signal RAMP plus the integral compensation signal ICOMP.
[0063] In some embodiments, the inverting input of comparator 855 is coupled to arithmetic circuit 851 to receive the arithmetic signal SUM1, while the non-inverting input of comparator 855 is coupled to arithmetic circuit 853 to receive the arithmetic signal SUM2. The pulse generation circuit 857 can utilize circuit elements such as latch-up circuits and delay circuits (e.g.,...). Figure 2 This is achieved using a latching circuit 253 and a delay circuit 255. The pulse generation circuit 857 is coupled to the output of the comparator 855 and can also be coupled to... Figure 1 The on-time generation circuit 30 is used in this configuration. In this configuration, the comparator 855 compares the operational signals SUM1 and SUM2 to output a comparison signal COM2. Specifically, when the voltage level of the operational signal SUM2 is greater than the voltage level of the operational signal SUM1 (i.e., the sum of the integral compensation signal ICOMP and the ramp signal RAMP minus the sum of the proportional compensation signal PCOMP and the reference ramp signal RREF is greater than 0), the comparison signal COM2 is enabled. When the voltage level of the operational signal SUM2 is not greater than the voltage level of the operational signal SUM1 (i.e., the sum of the integral compensation signal ICOMP and the ramp signal RAMP minus the sum of the proportional compensation signal PCOMP and the reference ramp signal RREF is not greater than 0), the comparison signal COM2 is disabled.
[0064] like Figure 2 The description of the latch circuit 253 and the delay circuit 255 is as follows: Figure 8 In this embodiment, the pulse generation circuit 857 receives the comparison signal COM2 and can generate a trigger pulse signal DTY based on the voltage level of the comparison signal COM2.
[0065] In some embodiments, the power converter circuit 100 may be implemented using a multiphase buck converter. Assuming... Figure 1 The power stage circuit 10 and inductor L in the figure correspond to one phase of the power converter circuit 100. The power converter circuit 100 may also include multiple sets of power stage circuits 10 and inductors L corresponding to the other phases of the power converter circuit 100. In an embodiment where the power converter circuit 100 has multiple phases, the conduction time generation circuit 30 may also include a phase management circuit (not shown in the figure), which can generate multiple control signals CS to control multiple power stage circuits 10.
[0066] In addition, please see Figure 9 , Figure 9 This is a circuit diagram illustrating a ramp generation circuit 93 according to some embodiments of the present invention. The ramp generation circuit 93 is also applicable to the control circuit 20. Compared to... Figure 4 The ramp generation circuit 23 of the embodiment further includes a selector 937, and the transconductance amplifier circuit 231 includes a plurality of transistors M3 connected in parallel. The selector 937 includes a plurality of switches corresponding to the plurality of transistors M3 respectively. In detail, any switch in the selector 937 is coupled to the second terminal of the corresponding transistor M3 and node NR. That is, the selector 937 can be controlled by a circuit (e.g., control circuit 20 or phase management circuit) to switch each switch to an on or off state.
[0067] The description of the multi-phase power converter circuit 100 is as follows: because each phase power stage circuit 10 can generate a phase current, the output voltage VOUT responds more drastically to load transients. Figure 9 In the circuit configuration, by controlling at least two of the multiple phase selectors 937 to switch to the on state, the ramp signal RAMP output by the ramp generation circuit 93 can rise according to another slope greater than the aforementioned preset slope, so that the pulse generation frequency of the ramp signal RAMP matches the requirements of the multi-phase configuration (e.g., increase the pulse generation frequency of the ramp signal RAMP), and matches the output voltage VOUT which reacts more violently under load transients.
[0068] As can be seen from the above embodiments of this utility model, by using the proportional compensation signal PCOMP, which responds to changes in the output voltage VOUT, the control circuit 20 can control the on-time generation circuit 30 to appropriately increase or decrease the operating frequency of the power stage circuit 10, thereby quickly stabilizing the output voltage VOUT. Furthermore, the integral compensation signal ICOMP, the ramp signal RAMP, and the reference ramp signal RREF also contribute to the operational stability of the control circuit 20. In summary, compared to related technologies, the control circuit 20 and the power converter circuit 100 of this utility model have advantages such as better load transient response capability.
[0069] Although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the present invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.
[0070] [Symbol Explanation]
[0071] 10: Power stage circuit
[0072] 11: Drive Circuit
[0073] 12: High-side switch
[0074] 13: Low-side switch
[0075] 20: Control Circuit
[0076] 21: Proportional-integral circuit
[0077] 23,93: Ramp Generation Circuit
[0078] 25: Comparator Circuit
[0079] 30: On-time generation circuit
[0080] 100: Power converter circuit
[0081] 211,811: Proportional circuits
[0082] 213,813: Integrating circuit
[0083] 231, AGMI: Transconductance Amplifier Circuit
[0084] 233, C1: Capacitor
[0085] 235: Reset Circuit
[0086] 251,855: Comparator
[0087] 253: Latch circuit
[0088] 255: Delay Circuit
[0089] 257: Pulse Generation Circuit
[0090] 815: Inverting circuit
[0091] 817, 851, 853: Operational circuits
[0092] 857: Pulse Generation Circuit
[0093] 937: Selector
[0094] AOPP, AOPR: Amplifier circuit
[0095] CO: Decoupling capacitor
[0096] COM1, COM2: Comparison signals
[0097] CS: Control signal
[0098] DTY: Trigger pulse signal
[0099] ER1, ER2: Error signals
[0100] GND: Ground terminal
[0101] I1, I2: Current
[0102] ICOMP: Integral Compensation Signal
[0103] L: Inductance
[0104] M1, M2, M3: Transistors
[0105] NIN: Voltage input terminal
[0106] NOUT: Voltage output terminal
[0107] NP, NQ, NR: Nodes
[0108] PCOMP: Proportional Compensation Signal
[0109] Q: Output terminal
[0110] R: Reset terminal
[0111] R1, R2, R3: Resistors
[0112] RAMP: Ramp Signal
[0113] RREF: Reference ramp signal
[0114] S: Setting end
[0115] SN1, SN2: Time periods
[0116] SUM1, SUM2: Operation signals
[0117] VCC: Power supply voltage
[0118] VDAC: Reference signal
[0119] VFB: Feedback signal
[0120] VGH: High-side drive signal
[0121] VGL: Low-side drive signal
[0122] VIN: Input voltage
[0123] VOUT: Output voltage.
Claims
1. A control circuit, characterized in that, Suitable for power converter circuits and includes: A proportional-integral circuit is coupled to the voltage output terminal of the power converter circuit and is used to output a proportional compensation signal and an integral compensation signal based on a reference signal and a feedback signal associated with the voltage output terminal. The ramp generation circuit, based on the reference signal, outputs a reference ramp signal and a ramp signal: and A comparator circuit, coupled to the proportional-integral circuit and the ramp generation circuit, is used to receive the proportional compensation signal, the integral compensation signal, the reference ramp signal, and the ramp signal to output a trigger pulse signal, and to generate a pulse in the trigger pulse signal when the first sum of the integral compensation signal and the ramp signal is greater than the second sum of the proportional compensation signal and the reference ramp signal.
2. The control circuit according to claim 1, characterized in that, This proportional-integral circuit includes: A scaling circuit is used to receive the reference signal and the feedback signal, and to scale the first difference associated with the feedback signal minus the reference signal to output the scaling compensation signal. as well as An integrating circuit is used to receive the reference signal and the feedback signal, and to perform an integration operation on a second difference associated with the reference signal minus the feedback signal, so as to output the integrated compensation signal.
3. The control circuit according to claim 2, characterized in that, This proportional circuit includes: An amplifier circuit, wherein the non-inverting input of the amplifier circuit is used to receive the feedback signal; A first resistor, wherein a first end of the first resistor is used to receive the reference signal, and a second end of the first resistor is coupled to the inverting input of the amplifier circuit; as well as The second resistor has a first end coupled to the second end of the first resistor and the inverting input of the amplifier circuit, and the second end of the second resistor is coupled to the output of the amplifier circuit, wherein the output of the amplifier circuit outputs the proportional compensation signal.
4. The control circuit according to claim 2, characterized in that, The integrating circuit includes: A transconducting amplifier circuit, wherein the non-inverting input terminal of the transconducting amplifier circuit is used to receive the reference signal, and the inverting input terminal of the transconducting amplifier circuit is used to receive the feedback signal; as well as A capacitor, wherein a first end of the capacitor is coupled to the output of the transconductance amplifier circuit, and a second end of the capacitor is coupled to ground, and wherein the output of the transconductance amplifier circuit outputs the integral compensation signal.
5. The control circuit according to claim 1, characterized in that, This proportional-integral circuit includes: The arithmetic circuit is used to receive the reference signal and the feedback signal, and to output a first error signal, wherein the first error signal indicates the difference associated with the reference signal minus the feedback signal; An inverting circuit is coupled to the operational circuit and is used to invert the first error signal and output the second error signal. An integrating circuit, coupled to the operational circuit, is used to integrate the first error signal to output the integrated compensation signal. as well as A proportional circuit, coupled to the inverting circuit, is used to proportionally scale the second error signal to output the proportional compensation signal.
6. The control circuit according to claim 1, characterized in that, The ramp generation circuit includes: A capacitor is coupled to the first node and the ground terminal, wherein the ramp signal is output from the first node; A transconductance amplifier circuit, coupled to the first node, is used to receive the reference signal and convert the reference signal into a reference current so as to charge the capacitor through the reference current, thereby causing the voltage level of the ramp signal to rise according to a preset slope. as well as A reset circuit, coupled to the first node and the ground terminal, is used to generate a discharge path between the first node and the ground terminal in response to the pulse in the trigger pulse signal, so that the voltage level of the ramp signal is reduced to the ground voltage of the ground terminal.
7. The control circuit according to claim 6, characterized in that, This transconducting amplifier circuit includes: A current generating circuit is used to generate a first current flowing through the second node and the third node based on the reference signal, and to generate the reference ramp signal at the third node based on the first current. as well as A current mirror circuit is coupled to the second node and the first node, and is used to generate the reference current to the first node based on the first current.
8. The control circuit according to claim 1, characterized in that, The comparator circuit includes: A comparator is used to compare the proportional compensation signal, the integral compensation signal, the reference ramp signal, and the ramp signal to output a comparison signal. The first inverting input of the comparator is used to receive the reference ramp signal, the second inverting input of the comparator is used to receive the proportional compensation signal, the first non-inverting input of the comparator is used to receive the integral compensation signal, and the second non-inverting input of the comparator is used to receive the ramp signal. as well as A pulse generation circuit is coupled to the output of the comparator and is used to generate the trigger pulse signal based on the voltage level of the comparison signal.
9. The control circuit according to claim 1, characterized in that, The comparator circuit includes: A first operational circuit, coupled to the proportional-integral circuit, is used to receive the proportional compensation signal and the reference ramp signal, and to generate a first operational signal, wherein the first operational signal indicates the second sum associated with the proportional compensation signal and the reference ramp signal; A second operational circuit, coupled to the proportional-integral circuit, is used to receive the integral compensation signal and the ramp signal, and to generate a second operational signal, wherein the second operational signal indicates the first sum associated with the integral compensation signal and the ramp signal; A comparator is used to compare the first operational signal and the second operational signal to output a comparison signal, wherein the inverting input of the comparator is used to receive the first operational signal, and the non-inverting input of the comparator is used to receive the second operational signal. as well as A pulse generation circuit is coupled to the output of the comparator and is used to generate the trigger pulse signal based on the voltage level of the comparison signal.
10. A power converter circuit, characterized in that, Used to receive input voltage at the voltage input terminal and to output output voltage at the voltage output terminal, and includes: The power stage circuit is coupled to the voltage input terminal and coupled to the voltage output terminal via an inductor; as well as A control circuit, coupled to the power stage circuit and the voltage output terminal, is used to generate a proportional compensation signal, an integral compensation signal, a reference ramp signal, and a ramp signal based on a reference signal and a feedback signal associated with the output voltage. When the first sum of the integral compensation signal and the ramp signal is greater than the second sum of the proportional compensation signal and the reference ramp signal, the control circuit adjusts the operating frequency of the power stage circuit to increase the output voltage.