Pixel structure, display panel and display device

Abstract

The application discloses a pixel structure, a display panel and a display device, and relates to the technical field of display, which can avoid crosstalk between adjacent pixels and improve the display effect of a display picture. The pixel structure comprises a substrate layer, a driving transistor, a first gate, a second gate, a first electrode, a second electrode, a third electrode, a first semiconductor structure and a second semiconductor structure; the first gate and the second gate are connected with a gate line; a data signal line is connected with one end of the first electrode; the other end of the first electrode and one end of the second electrode are connected with the first semiconductor structure; the other end of the second electrode and one end of the third electrode are connected with the second semiconductor structure; a pixel electrode is connected with the other end of the third electrode; the orthogonal projection of the pixel electrode on the substrate layer does not overlap with the orthogonal projection of the first electrode on the substrate layer, and the orthogonal projection of the pixel electrode on the substrate layer does not overlap with the orthogonal projection of the data signal line on the substrate layer.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a pixel structure, display panel, and display device. Background Technology

[0002] Currently, display devices with advantages such as high-generation production capacity and low cost are widely used in televisions, computers, mobile phones, and other fields. With the rise of display technology, the demand for display devices continues to increase. However, in existing technologies, pixel electrodes are positioned above the driving transistors used to drive the pixel electrodes. Because the pixel electrodes and driving transistor electrodes overlap through projection, capacitance is easily formed. This capacitance can cause the driving signal to affect the potential on the pixel electrodes during transmission in the signal lines, leading to crosstalk between pixels and affecting the display effect. Utility Model Content

[0003] This application provides a pixel structure, a display panel, and a display device that can avoid crosstalk between pixels and improve the display effect of the display screen.

[0004] A first aspect of this application provides a pixel structure, including:

[0005] Substrate layer;

[0006] A driving transistor includes a first gate, a second gate, a first electrode, a second electrode, a third electrode, a first semiconductor structure, and a second semiconductor structure. The orthographic projection of the first gate on the substrate overlaps with the orthographic projection of the first semiconductor structure on the substrate, and the orthographic projection of the second gate on the substrate overlaps with the orthographic projection of the second semiconductor structure on the substrate.

[0007] A gate line, wherein both the first gate and the second gate are connected to the gate line;

[0008] A data signal line is connected to one end of the first electrode, the other end of the first electrode and one end of the second electrode are both connected to the first semiconductor structure, and the other end of the second electrode and one end of the third electrode are both connected to the second semiconductor structure.

[0009] A pixel electrode is connected to the other end of the third electrode;

[0010] The orthographic projection of the pixel electrode on the substrate layer does not overlap with the orthographic projection of the first electrode on the substrate layer, and the orthographic projection of the pixel electrode on the substrate layer does not overlap with the orthographic projection of the data signal line on the substrate layer.

[0011] In some embodiments, the first semiconductor structure includes a first channel region, and the second semiconductor structure includes a second channel region;

[0012] The length direction of the first channel region is different from that of the second channel region.

[0013] In some embodiments, the length direction of the first channel region is the same as the length extension direction of the gate line;

[0014] The length direction of the second channel region is the same as the length extension direction of the data signal line.

[0015] In some embodiments, the first gate and the second gate are respectively connected to different sides of the gate line.

[0016] In some embodiments, the second electrode includes a first structural portion and a second structural portion, wherein the first structural portion is connected to the first semiconductor structure and the second structural portion is connected to the second semiconductor structure.

[0017] Both the first structural part and the second structural part are strip-shaped structures, and the length extension direction of the first structural part is different from that of the second structural part;

[0018] The orthographic projection of the first structural portion on the substrate layer partially overlaps with the orthographic projections of the gate line and the first gate electrode on the substrate layer;

[0019] The orthographic projection of the second structural portion on the substrate layer does not overlap with the orthographic projection of the gate line on the substrate layer;

[0020] The orthographic projection of the second structural portion on the substrate layer and the orthographic projection of the second gate on the substrate layer partially overlap.

[0021] In some embodiments, the orthographic projection of the first structural portion onto the substrate layer overlaps with or does not overlap with the orthographic projection of the pixel electrode onto the substrate layer; and / or,

[0022] The orthographic projection of the second structural part on the substrate layer does not overlap with the orthographic projection of the pixel electrode on the substrate layer.

[0023] In some embodiments, the connection end between the first structural portion and the first semiconductor structure is a first end, and the connection end between the second structural portion and the second semiconductor structure is a second end, with the first end and the second end located on different sides of the gate line.

[0024] In some embodiments, the first gate is located on different sides of the gate line at both ends in the length direction of the data signal line, and the second gate is located on different sides of the gate line at both ends in the length direction of the data signal line.

[0025] In some embodiments, the first gate has a third end and a fourth end at its two ends in the length direction of the data signal line, and the second gate has a fifth end and a sixth end at its two ends in the length direction of the data signal line, wherein the third end and the fifth end are located on the same side of the gate line, and the fourth end and the sixth end are located on the same side of the gate line.

[0026] Along the length of the data signal line, the end face of the third end extends beyond the end face of the fifth end, and the end face of the fourth end extends beyond the end face of the sixth end.

[0027] In some embodiments, the second electrode includes a first structural portion, a second structural portion, a third structural portion, and a fourth structural portion. The first structural portion is connected to the first semiconductor structure, the second structural portion is connected to the second semiconductor structure, the third structural portion is connected between the first structural portion and the fourth structural portion, and the fourth structural portion is connected between the third structural portion and the second structural portion. The length extension direction of the third structural portion is different from the length extension direction of the fourth structural portion.

[0028] The orthographic projection of the first structural portion on the substrate falls within the orthographic projection of the first gate on the substrate, and the orthographic projection of the second structural portion on the substrate falls within the orthographic projection of the second gate on the substrate;

[0029] The orthographic projection of the third structural portion on the substrate layer does not overlap with the orthographic projections of the first gate and the second gate on the substrate layer;

[0030] The orthographic projection of the fourth structural portion on the substrate layer does not overlap with the orthographic projections of the first gate and the second gate on the substrate layer.

[0031] In some embodiments, the orthogonal projection of the pixel electrode on the substrate completely covers the orthogonal projection of the first structure on the substrate;

[0032] The orthographic projection of the pixel electrode on the substrate layer does not overlap with the orthographic projections of the second, third, and fourth structural portions on the substrate layer.

[0033] In some embodiments, the first gate and the second gate are connected to the same side of the gate line, and a notch is formed between the first gate and the second gate and the gate line, respectively. The orthogonal projection of the notch on the substrate layer overlaps with the orthogonal projection of the second electrode on the substrate layer.

[0034] In some embodiments, the data signal line is connected to the first semiconductor structure via a first via, the orthographic projection of the first via on the substrate falling onto the orthographic projection of the data signal line on the substrate.

[0035] In some implementations, the pixel structure further includes:

[0036] A storage capacitor, the storage capacitor comprising a first electrode plate and a second electrode plate that are insulated from each other;

[0037] The first electrode plate is connected to the pixel electrode through a second via, the second electrode plate is connected to a common signal line, and the orthogonal projection of the first electrode plate on the substrate layer covers the orthogonal projection of the second electrode plate on the substrate layer.

[0038] The orthogonal projection of the pixel electrode on the substrate layer overlaps the orthogonal projections of the first electrode plate and the second electrode plate on the substrate layer.

[0039] In some embodiments, the length extension direction of the common signal line is the same as the length extension direction of the gate line, wherein the second electrode is located between the gate line and the common signal line.

[0040] A second aspect of this application provides a display panel, including:

[0041] Multiple pixel structures as described in the first aspect, and an array of the multiple pixel structures arranged together.

[0042] A third aspect of this application provides a display device, including a display panel as described in the second aspect.

[0043] The pixel structure provided in this application embodiment, in the dual-gate driving transistor, connects the first electrode of the first thin-film transistor to the data signal line, and the third electrode of the second thin-film transistor to the pixel electrode. The first and second thin-film transistors share a second electrode, and the orthographic projections of the first electrode and the data signal line on the substrate do not overlap with the orthographic projections of the pixel electrode on the substrate. The data signal line is connected to the first electrode of the first thin-film transistor for data signal transmission. When the first thin-film transistor is not turned on, the data signal only passes through the first electrode of the first thin-film transistor and is not transmitted to the pixel electrode through the second and third electrodes of the first and second thin-film transistors. Therefore, even if the data signal passes through the first electrode, or if the orthographic projections of the second and third electrodes overlap with the orthographic projection of the pixel electrode, the potential of the pixel electrode will not fluctuate due to voltage changes in the first electrode, thus preventing fluctuations in the capacitance formed between the pixel electrode and the electrodes in the driving transistor. During the illumination process of pixels in adjacent rows or columns, the data signal will not pull the voltage of the pixel electrode where the gate signal has not been transmitted to the pixel, thereby avoiding crosstalk between adjacent pixels and improving the display effect. Attached Figure Description

[0044] Figure 1 A schematic partial top view of a pixel structure provided in an embodiment of this application;

[0045] Figure 2 A schematic partial top view of another pixel structure provided in an embodiment of this application;

[0046] Figure 3 for Figure 2 A schematic partial cross-sectional view of the provided pixel structure along AA′ and BB′;

[0047] Figure 4 This application provides an embodiment of a schematic local equivalent circuit for a pixel structure;

[0048] Figure 5 A schematic partial top view of yet another pixel structure provided in an embodiment of this application;

[0049] Figure 6 for Figure 5 A schematic partial cross-sectional view of the provided pixel structure along AA′ and BB′;

[0050] Figure 7 A schematic partial top view of another pixel structure provided in an embodiment of this application;

[0051] Figure 8 for Figure 7A schematic partial cross-sectional view of the provided pixel structure along AA′ and BB′;

[0052] Figure 9 A schematic partial top view of a pixel structure provided in an embodiment of this application;

[0053] Figure 10 A schematic partial top view of another pixel structure provided in an embodiment of this application;

[0054] Figure 11 A schematic partial top view of a display panel provided in an embodiment of this application;

[0055] Figure 12 This is a schematic structural diagram of a display device provided in an embodiment of this application. Detailed Implementation

[0056] To better understand the technical solutions provided in the embodiments of this specification, the technical solutions of the embodiments of this specification will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the embodiments of this specification and the specific features in the embodiments are detailed descriptions of the technical solutions of the embodiments of this specification, rather than limitations on the technical solutions of this specification. In the absence of conflict, the embodiments of this specification and the technical features in the embodiments can be combined with each other.

[0057] In this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, without necessarily requiring or implying any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. The term "two or more" includes two or more cases.

[0058] Currently, display devices with advantages such as high-generation production capacity and low cost are widely used in televisions, computers, mobile phones, and other fields. With the rise of display technology, the demand for display devices continues to increase. However, in existing technologies, pixel electrodes are positioned above the driving transistors used to drive the pixel electrodes. Because the pixel electrodes and driving transistor electrodes overlap through projection, capacitance is easily formed. This capacitance can cause the driving signal to affect the potential on the pixel electrodes during transmission in the signal lines, leading to crosstalk between pixels and affecting the display effect.

[0059] Figure 1 This is a schematic partial top view of a pixel structure provided in an embodiment of this application. (Reference) Figure 1 The driving transistor includes a first gate 110, a second gate 120, a first electrode 130, a second electrode 140, and a third electrode 150. The first electrode 130 can be either a source or a drain, one end of the second electrode serves as either a source or a drain, and the other end of the second electrode serves as either a source or a drain. The third electrode 150 is the other of the source and drain. The second electrode 140 is a common electrode of the dual-gate driving transistor. The first electrode 130 is electrically connected to the data signal line 100, and the third electrode 150 is electrically connected to the pixel electrode 400, which is used to drive sub-pixels to emit light. Because the pixel electrode 400 and the first electrode 130 in the driving transistor have an orthographic overlap, forming a capacitor, the formed capacitor will affect the potential fluctuation of the second electrode 140 during the transmission of the data signal in the signal line, regardless of whether the driving transistor is turned on or not. The second electrode 140 affects the potential fluctuation of the third electrode 150, and the third electrode 150 affects the potential fluctuation of the pixel electrode 400, thereby causing crosstalk between adjacent pixels and affecting the display effect of the display screen.

[0060] A first aspect of this application provides a pixel structure. Figure 2 This is a schematic partial top view of another pixel structure provided in an embodiment of this application. Figure 3 for Figure 2 A schematic partial cross-sectional view of the provided pixel structure along AA′ and BB′. For example, refer to... Figures 2 to 3The pixel structure includes a substrate layer 101, a driving transistor, a gate line 200, a data signal line 100, and a pixel electrode 400. The driving transistor includes a first gate 110, a second gate 120, a first electrode 130, a second electrode 140, a third electrode 150, a first semiconductor structure 160, and a second semiconductor structure 170. The first gate 110 and the second gate 120 can both be disposed on a first conductive layer 700. The first electrode 130, the second electrode 140, and the third electrode 150 can all be disposed on a second conductive layer 800, wherein the data signal line 100 is disposed on the same layer as the first electrode 130. The first semiconductor structure 160 and the second semiconductor structure 170 are disposed on a semiconductor layer, and the first semiconductor structure 160 and the second semiconductor structure 170 can be connected or disconnected. The pixel electrode 400 can be disposed on a third conductive layer 900. A first conductive layer 700 is disposed on one side of the substrate layer 101, a second conductive layer 800 is disposed on the side of the first conductive layer 700 away from the substrate layer 101, and a third conductive layer 900 is disposed on the side of the second conductive layer 800 away from the substrate layer 101. A first insulating layer 213 is disposed between the second conductive layer 200 and the third conductive layer 900. A gate insulating layer 113 is disposed between the first conductive layer 700 and the semiconductor layer. The first gate 110 and the second gate 120 are both connected to the gate line 200, which is used to transmit gate signals. A data signal line 100 is used to transmit data signals. The data signal line 100 is connected to one end of the first electrode 130, the other end of the first electrode 130 and one end of the second electrode 140 are both connected to the first semiconductor structure 160, and the other end of the second electrode 140 and one end of the third electrode 150 are both connected to the second semiconductor structure 170. The pixel electrode 400 is connected to the other end of the third electrode 150. The orthographic projection of the first gate 110 on the substrate 101 overlaps with the orthographic projection of the first semiconductor structure 160 on the substrate 101, and the orthographic projection of the second gate 120 on the substrate 101 overlaps with the orthographic projection of the second semiconductor structure 170 on the substrate 101. One end of the first gate 110, the first electrode 130, and the second electrode 140, along with the first semiconductor structure 160, can form a first thin-film transistor. The data signal line 100 is integral with the first electrode 130, serving both as a data signal line for transmitting data signals and directly as the first electrode of the first thin-film transistor; that is, the data signal line 100 can be multiplexed or shared with the first electrode of the driving transistor. The other end of the second gate 120 and the second electrode 140, the third electrode 150, and the second semiconductor structure 170 can form a second thin-film transistor. The first semiconductor structure 160 includes a first channel region 180, which is the region where the orthographic projection of the first gate 110 on the first semiconductor structure 160 overlaps with the first semiconductor structure 160.The second semiconductor structure 170 includes a second channel region 190, which is the region where the orthographic projection of the second gate 120 onto the second semiconductor structure 170 overlaps with the second semiconductor structure 170. The second electrode 140 can serve as a common electrode for the first thin-film transistor and the second thin-film transistor. The orthographic projection of the pixel electrode 400 onto the substrate 101 does not overlap with the orthographic projection of the first electrode 130 onto the substrate, and the orthographic projection of the pixel electrode 400 onto the substrate 101 does not overlap with the orthographic projection of the data signal line 100 onto the substrate 101.

[0061] It should be noted that the reference Figure 3 No insulating layer is provided between the semiconductor layer and the second conductive layer 800. Both the first semiconductor structure 160 and the second semiconductor structure 170 can be made of a-Si material with low electron mobility. This avoids the first electrode 130 and the second electrode 140 from conducting, reduces one film preparation process, and lowers processing costs.

[0062] For example, Figure 4 This application provides an embodiment of a schematic local equivalent circuit for a pixel structure. For example, refer to... Figure 4 The pixel structure includes a first gate 110, a second gate 120, a first electrode 130, a second electrode 140, a third electrode 150, a pixel electrode 400, and a storage capacitor 410. The first gate 110 and the second gate 120 control the writing of data signals into the storage capacitor 410. A first thin-film transistor T1 and a second thin-film transistor T2 are connected in series. The first gate 110 and the second gate 120 are controlled by a gate line 200. When both the first thin-film transistor T1 and the second thin-film transistor T2 are turned on, data signals are transmitted to the pixel electrode via the data signal line 100. The data signals can be stored in the storage capacitor 410, and a common signal line can provide a common signal voltage Vcom to the storage capacitor 410. When neither the first thin-film transistor T1 nor the second thin-film transistor T2 is turned on, the data signal only reaches the first electrode 130 of the first thin-film transistor T1; the data signal is not transmitted to the pixel electrode 400 via the second electrode 140 of the first thin-film transistor T1 or the third electrode 150 of the second thin-film transistor T2. Therefore, even if the data signal passes through the first electrode 130, the potential of the pixel electrode 400 will not fluctuate due to voltage changes in the first electrode 130, thus preventing fluctuations in the capacitance formed between the pixel electrode 400 and the electrode in the driving transistor. During the lighting process of pixels in adjacent rows or columns, the data signal will not pull the voltage of the pixel electrode of pixels whose gate signals have not been transmitted, thereby avoiding crosstalk between adjacent pixels and improving the display effect.

[0063] For example, refer to Figures 2 to 4The orthographic projection of the first electrode 130 on the substrate 101 overlaps with the orthographic projection of the data signal line 100 on the substrate 101. When the driving transistor is turned on, the data signal transmitted by the data signal line 100 sequentially passes through the first electrode 130, the first semiconductor structure 160, the second electrode 140, and the third electrode 150 to the pixel electrode 400. When the driving transistor is not turned on, the data signal transmitted by the data signal line 100 only reaches the first electrode 130. The transmission of data signals between adjacent pixels does not affect the voltage of the second electrode 140 or the voltage of the third electrode 150. When the voltage of the third electrode 150 remains unchanged, the voltage of the pixel electrode 400 connected to the third electrode 150 also remains unchanged. Even if the orthographic projections of the second and third electrodes overlap with the orthographic projection of the pixel electrode, the potential of the pixel electrode will not fluctuate due to changes in the voltage of the first electrode, thus preventing fluctuations in the capacitance formed between the pixel electrode and the electrode in the driving transistor. During the lighting process of pixels in adjacent rows or columns, the data signal will not pull the voltage of the pixel electrode of the pixel whose gate signal has not been transmitted, thereby avoiding crosstalk between adjacent pixels and improving the display effect of the display screen.

[0064] For example, refer to Figures 2 to 4 The first electrode 130 can be the drain, one end of the second electrode 140 can be the source, and the other end of the second electrode 140 can also be the source. The third electrode 150 can be the drain. The first thin-film transistor T1 and the second thin-film transistor T2 share the second electrode 140. The first electrode 130 can be the drain of the first thin-film transistor T1, and the third electrode 150 can be the drain of the second thin-film transistor T2. The data signal line 100 is electrically connected to the drain of the first thin-film transistor T1, and the data signal is transmitted in the data signal line 100. The first gate 110 and the second gate 120 are both connected to the gate line 200, and the gate signal is transmitted in the gate line 200. Furthermore, when the gate signal is not transmitted to the current row pixel, that is, when the source and drain electrodes of the first thin film transistor T1 are not turned on, the data signal only reaches the drain of the first thin film transistor T1, and will not pass through the source of the first thin film transistor T1, nor will it be transmitted to the pixel electrode 400 through the source of the first thin film transistor T1 and the drain of the second thin film transistor T2. This can prevent the data signal from pulling the voltage of the pixel electrode 400 of the currently unconverted pixel during the lighting process of adjacent pixels, and avoid crosstalk between adjacent pixels.

[0065] The pixel structure provided in this application embodiment, in the dual-gate driving transistor, connects the first electrode of the first thin-film transistor to the data signal line, and the third electrode of the second thin-film transistor to the pixel electrode. The first and second thin-film transistors share a second electrode, and the orthographic projections of the first electrode and the data signal line on the substrate do not overlap with the orthographic projections of the pixel electrode on the substrate. The data signal line is connected to the first electrode of the first thin-film transistor for data signal transmission. When the first thin-film transistor is not turned on, the data signal only passes through the first electrode of the first thin-film transistor and is not transmitted to the pixel electrode through the second and third electrodes of the first and second thin-film transistors. Therefore, even if the data signal passes through the first electrode, or if the orthographic projections of the second and third electrodes overlap with the orthographic projection of the pixel electrode, the potential of the pixel electrode will not fluctuate due to voltage changes in the first electrode, thus preventing fluctuations in the capacitance formed between the pixel electrode and the electrodes in the driving transistor. During the illumination process of pixels in adjacent rows or columns, the data signal will not pull the voltage of the pixel electrode where the gate signal has not been transmitted to the pixel, thereby avoiding crosstalk between adjacent pixels and improving the display effect.

[0066] In some embodiments, the length direction of the first channel region is different from that of the second channel region. The length direction of the channel region is the direction from the first electrode to the second electrode, that is, the direction of carrier flow, and the width direction of the channel region is perpendicular to the direction of carrier flow.

[0067] For example, refer to Figures 2 to 4The length direction of the first channel region 180 is the same as the length extension direction of the gate line 200, and the length direction of the second channel region 190 is the same as the length extension direction of the data signal line 100. The length extension direction of the gate line 200 is the row direction X, and the length extension direction of the data signal line 100 is the column direction Y. The length extension direction of the first gate 110 is the same as the length extension direction of the data signal line 100, and the length extension direction of the first gate 110 is parallel to the length extension direction of the data signal line 100. The length extension direction of the second gate 120 is the same as the length extension direction of the gate line 200, and the length extension direction of the second gate 120 is parallel to the length extension direction of the gate line 200. The extension lines of the first gate 110 and the second gate 120 are perpendicular to each other. By setting the first gate 110 and the second gate 120 in the dual-gate driving transistor to be perpendicular to each other, the first thin-film transistor T1 and the second thin-film transistor T2 of the dual-gate driving transistor form a vertically arranged structure with one horizontal and one vertical orientation. By vertically arranging the first thin-film transistors in the gap between the data signal line and the pixel electrode, the area occupied by the driving transistor in the pixel aperture region can be reduced, thereby reducing the occupancy of the pixel aperture region by the driving transistor and improving the pixel aperture ratio. Simultaneously, the orthographic projection of the first electrode 130 of the driving transistor with a dual-gate structure on the substrate 101 does not overlap with the orthographic projection of the pixel electrode 400 above the driving transistor on the substrate 101. The orthographic projection of the first electrode 130 on the substrate 101 falls within the orthographic projection of the data signal line 100 on the substrate 101, thus preventing the formation of capacitance between the pixel electrode 400 and the first electrode 130 of the driving transistor, and thus preventing voltage changes in the first electrode 130 from pulling voltage changes in the pixel electrode. This improves the pixel aperture ratio while avoiding crosstalk between adjacent pixels, thereby enhancing the brightness and display effect of the displayed image.

[0068] In some implementations, reference Figures 2 to 4The first gate 110 and the second gate 120 are respectively connected to different sides of the gate line 200. The first gate 110 and the second gate 120 cooperate to control the switching. When the first gate 110 and the second gate 120 are simultaneously energized, the first channel region 180 and the second channel region 190 are turned on. The data signal is transmitted to the pixel electrode 400 after passing through the first thin-film transistor T1 and the second thin-film transistor T2, and the switching speed of the driving transistor is significantly improved. In addition, when neither the first gate 110 nor the second gate 120 reaches the threshold voltage, the first thin-film transistor T1 and the second thin-film transistor T2 are not turned on. The data signal only reaches the drain of the first thin-film transistor T1 and will not pass through the source of the first thin-film transistor T1, nor will it pass through the source and drain of the second thin-film transistor T2 to be transmitted to the pixel electrode. This can reduce the interference between the drain and the source, reduce the leakage current in the closed state of the driving transistor, improve the performance of the driving transistor, and make the display panel display the image stably.

[0069] Figure 5 This is a schematic partial top view of yet another pixel structure provided in an embodiment of this application. Figure 6 for Figure 5 The provided pixel structure is a schematic partial cross-sectional view along AA′ and BB′. (Reference) Figures 5 to 6The second electrode 140 includes a first structural portion 141 and a second structural portion 142. When both the first electrode 130 and the third electrode are drains, both the first structural portion 141 and the second structural portion 142 can serve as sources. The first structural portion 141 is connected to the first semiconductor structure 160, and the second structural portion 142 is connected to the second semiconductor structure 170. The first gate 110, the first structural portion 141, the first electrode 130, and the first semiconductor structure 160 form a first thin-film transistor. The data signal line 100 is integral with the first electrode 130, and can serve both as a data signal line for transmitting data signals and as the first electrode of the first thin-film transistor. The second gate 120, the second structural portion 142, the third electrode 150, and the second semiconductor structure 170 form a second thin-film transistor. Both the first structural portion 141 and the second structural portion 142 are strip-shaped structures, and the length extension direction of the first structural portion 141 is different from that of the second structural portion 142. The first structural portion 141 extends in the same direction as the gate line 200, and the second structural portion 142 extends in the same direction as the data signal line. The first structural portion 141 and the second structural portion 142 are perpendicularly connected to each other. The orthographic projection of the first structural portion 141 on the substrate 101 partially overlaps with the orthographic projections of the gate line 200 and the first gate 110 on the substrate 101. The orthographic projection of the second structural part 142 on the substrate 101 does not overlap with the orthographic projection of the gate line 200 on the substrate 101. However, the orthographic projection of the second structural part 142 on the substrate 101 partially overlaps with the orthographic projection of the second gate 120 on the substrate 101. By dividing the shared second electrode 140 of the first thin-film transistor and the second thin-film transistor into two structural parts, the first thin-film transistor and the second thin-film transistor of the dual-gate driving transistor can form a horizontal and vertical vertical structure. The vertically arranged first thin-film transistor T1 is placed in the gap between the data signal line 100 and the pixel electrode to achieve a reasonable layout of the dual-gate structure driving transistor, reduce the area occupied by the driving transistor in the pixel opening area, thereby reducing the occupancy of the driving transistor in the pixel opening area and improving the pixel aperture ratio.

[0070] In some embodiments, the orthographic projection of the first structure on the substrate layer partially overlaps or does not overlap with the orthographic projection of the pixel electrode on the substrate layer, and the orthographic projection of the second structure on the substrate layer does not overlap with the orthographic projection of the pixel electrode on the substrate layer.

[0071] For example, refer to Figures 5 to 6The orthographic projection of the first structural portion 141 on the substrate 101 overlaps with the orthographic projection of the pixel electrode 400 on the substrate 101. The orthographic projection of the pixel electrode 400 on the substrate 101 covers the orthographic projection of the first structural portion 141 on the substrate 101, and the orthographic projection of the pixel electrode 400 on the substrate 101 covers the orthographic projection of the third electrode 150 on the substrate 101. At this time, when the first thin-film transistor is not turned on, the data signal only reaches the first electrode 130 of the first thin-film transistor and will not pass through the first structural portion 141 and the second structural portion 142. When the data signal passes through the first electrode 130, only the voltage of the first electrode 130 changes. Even if the orthographic projection of the pixel electrode 400 on the substrate 101 overlaps with the orthographic projections of the second electrode 140 and the third electrode 150 on the substrate 101, the voltage of the first structural portion 141 and the second structural portion 142 will still not change, and will not pull the voltage of the pixel electrode 400. Therefore, provided that the orthographic projection of the first electrode 130 on the substrate 101 does not overlap with the orthographic projection of the pixel electrode 400 on the substrate 101, the overlapping area of ​​the orthographic projections of the pixel electrode 400 with the second electrode 140 and the third electrode 150 can be reasonably adjusted according to the actual drive transistor structure layout to meet the display requirements of different aperture ratios and improve the diversity of display products.

[0072] For example, the orthographic projection of the first structure on the substrate does not overlap with the orthographic projection of the pixel electrode on the substrate, and the orthographic projections of both the first and second structures on the substrate do not overlap with the orthographic projection of the pixel electrode on the substrate. This ensures that only the orthographic projection of the third electrode on the substrate overlaps with the orthographic projection of the pixel electrode on the substrate in the dual-gate structure driving transistor. This completely avoids the formation of capacitance between the first and second electrodes and the pixel electrode. During the transmission of data signals, the signal transmission path is cut off, and crosstalk between adjacent pixels is avoided.

[0073] In some implementations, reference Figures 5 to 6 The connection point between the first structural portion 141 and the first semiconductor structure 160 is designated as the first terminal 143, and the connection point between the second structural portion 142 and the second semiconductor structure 170 is designated as the second terminal 144. The first terminal 143 and the second terminal 144 are located on different sides of the gate line 200. The first semiconductor structure 160 and the second semiconductor structure 170 can be disposed on the same layer. By disposing the first terminal 143 and the second terminal 144 on different sides of the gate line 200, the overlap area of ​​the orthogonal projection of the driving transistor and the pixel electrode on the substrate can be reduced, thereby reducing the capacitance generated between the electrode in the driving transistor and the pixel electrode, avoiding voltage fluctuations in the pixel electrode caused by the signal from the first electrode of the driving transistor, and preventing crosstalk between adjacent pixels.

[0074] For example, refer to Figure 5 The first gate 110 has its two ends located on different sides of the gate line 200 along the length of the data signal line 100, and the second gate 120 has its two ends located on different sides of the gate line 200 along the length of the data signal line 100. The first gate 110 and the second gate 120 cross the gate line 200 along the length of the data signal line 100. The length of the first gate 110 along the length of the data signal line 100 is greater than the width of the second gate along the length of the gate line 200. Specifically, the two ends of the first gate 110 along the length of the data signal line 100 are the third end 111 and the fourth end 112, respectively, and the two ends of the second gate 120 along the length of the data signal line 100 are the fifth end 121 and the sixth end 122, respectively. The third end 111 and the fifth end 121 are located on the same side of the gate line 200, and the fourth end 112 and the sixth end 122 are located on the same side of the gate line 200. Along the length of the data signal line 100, the end face of the third terminal 111 extends beyond the end face of the fifth terminal 121, and the end face of the fourth terminal 112 extends beyond the end face of the sixth terminal 122. This connects the first gate 110 and the second gate 120 to different sides of the gate line, thus rationally arranging the positions of the first gate 110 and the second gate 120 in the pixel structure. This ensures that the voltage of the first electrode 130 of the driving transistor does not pull the voltage of the pixel electrode. Compared to dual-gate driving transistors arranged in a row or column, dual-gate driving transistors arranged horizontally and vertically reduce crosstalk between adjacent pixels without increasing or affecting the aperture ratio.

[0075] Figure 7 This is a schematic partial top view of another pixel structure provided in an embodiment of this application. Figure 8 for Figure 7 A schematic partial cross-sectional view of the provided pixel structure along AA′ and BB′. For example, refer to... Figures 7 to 8The second electrode 140 includes a first structural portion 141, a second structural portion 142, a third structural portion 145, and a fourth structural portion 146. The first structural portion 141 is connected to the first semiconductor structure 160, the second structural portion 142 is connected to the second semiconductor structure 170, the third structural portion 145 is connected between the first structural portion 141 and the fourth structural portion 146, and the fourth structural portion 146 is connected between the third structural portion 145 and the second structural portion 142. The orthogonal projection of the first structural portion 141 on the substrate 101 falls within the orthogonal projection of the first gate 110 on the substrate 101, and the orthogonal projection of the second structural portion 142 on the substrate 101 falls within the orthogonal projection of the second gate 120 on the substrate 101. The length extension directions of the first gate 110, the third structural portion 145, and the second structural portion 142 are all the same as the length extension direction of the gate line 200, and the length extension directions of the second gate 120, the fourth structural portion 146, and the first structural portion 141 are all the same as the length extension direction of the data signal line 100. When the driving transistor is turned on, the data signal transmitted by the data signal line 100 is output to the first structure of the second electrode via the first electrode 130, and then transmitted to the third electrode 150 via the third structure, the fourth structure, and the second structure. The third electrode 150 then transmits the signal to the pixel electrode 400. When the driving transistor is not turned on, the data signal transmitted by the data signal line 100 only reaches the first electrode 130. The transmission of data signals between adjacent pixels does not affect the voltage of the second electrode 140 or the voltage of the third electrode 150. With the voltage of the third electrode 150 unchanged, the voltage of the pixel electrode 400 connected to the third electrode 150 also remains unchanged, and the capacitance between the pixel electrode 400 and the third electrode 150 does not change. This avoids the data signal pulling the voltage of the pixel electrode 400 of the pixel whose driving transistor is not turned on during the lighting process of adjacent pixels, thereby preventing crosstalk between adjacent pixels.

[0076] Example, reference Figures 7 to 8The first structural portion 141 and the second structural portion 142 are both strip-shaped structures. The length extension direction of the third structural portion 145 is different from that of the fourth structural portion 146. The orthographic projection of the third structural portion 145 on the substrate 101 does not overlap with the orthographic projections of the first gate 110 and the second gate 120 on the substrate 101. Similarly, the orthographic projection of the fourth structural portion 146 on the substrate 101 does not overlap with the orthographic projections of the first gate 110 and the second gate 120 on the substrate 101. By ensuring that the orthographic projections of the third structural portion 145 and the fourth structural portion 146 on the substrate do not overlap with the orthographic projections of the first gate 110 and the second gate 120 on the substrate, the parasitic capacitance generated between the first gate 110 and the second gate 120 and the second electrode 140 can be reduced, thereby improving the switching speed of the driving transistor. When the second electrode includes a drain, the electric field coupling between the gate and the drain can be reduced, the leakage current generated in the closed state of the driving transistor can be reduced, the power consumption of the display panel can be reduced, and the stability of the pixel voltage can be improved, thereby improving the display effect of the display panel.

[0077] For example, refer to Figure 7 The first gate 110 and the second gate 120 are respectively connected to different sides of the gate line 200. The first gate 110 is located above the gate line 200, meaning that the orthographic projection of the first gate 110 on the substrate falls on the side of the gate line 200 away from the first electrode 130. The orthographic projection of the second gate 120 on the substrate 101 overlaps with the orthographic projection of the gate line 200 on the substrate 101. The orthographic projections of both the first gate 110 and the second gate 120 on the substrate do not overlap with the orthographic projections of adjacent pixels on the substrate. Changes in gate voltage do not affect the voltage of pixels in adjacent rows or columns, resulting in better display performance.

[0078] In some implementations, reference Figures 7 to 8The orthographic projection of the pixel electrode 400 on the substrate 101 completely covers the orthographic projection of the first structural portion 141 on the substrate 101. The orthographic projection of the pixel electrode 400 on the substrate 101 does not overlap with the orthographic projections of the second structural portion 142, the third structural portion 145, and the fourth structural portion 146 on the substrate 101. At this time, when the first electrode 130 and the second electrode 140 of the first thin-film transistor are not conducting, the data signal only passes through the first electrode 130 of the first thin-film transistor and does not pass through the first structural portion 141 and the second structural portion 142. When the data signal passes through the first electrode 130, only the voltage of the first electrode 130 changes. Even if the orthographic projection of the pixel electrode 400 on the substrate completely covers the first structural portion 141, the voltages of the first structural portion 141, the third structural portion 145, the fourth structural portion 146, and the second structural portion 142 will not change, and the voltage of the pixel electrode 400 will not be affected. This avoids crosstalk between adjacent pixels and improves the display effect.

[0079] For example, refer to Figures 7 to 8 The data signal line 100 is connected to the first semiconductor structure 160 through a first via 124, which is disposed in the second insulating layer 710. The first electrode 130 is disposed within the first via 124. The orthogonal projection of the first via 124 onto the substrate 101 falls onto the orthogonal projection of the data signal line 100 onto the substrate 101. The data signal line 100 and the first electrode 130 are integral structures, but the first electrode 130 and the data signal line 100 are not disposed on the same layer. The data signal line 100 can serve as the first electrode of the driving transistor. When the data signal line 100, the second electrode 140, and the third electrode 150 are interconnected, the data signal can be directly transmitted through the first semiconductor structure 160 to the second electrode 140, and the second electrode 140 then transmits the data signal through the second semiconductor structure 170 to the pixel electrode 400. When the data signal line 100, the second electrode 140, and the third electrode 150 are interconnected, the data signal line 100 only serves as a carrier for data signal transmission. The data signal is transmitted only within the data signal line 100 and will not affect the voltage of the second electrode 140 or the voltage of the third electrode 150 due to the transmission of data signals between adjacent pixels. When the voltage of the third electrode 150 remains unchanged, the voltage of the pixel electrode 400 connected to the third electrode 150 also remains unchanged, and the capacitance between the pixel electrode 400 and the third electrode 150 will not change. This can prevent the data signal from pulling the voltage of the pixel electrode 400 of the pixel whose driving transistor is not currently turned on during the lighting process of adjacent pixels, thereby avoiding crosstalk between adjacent pixels.

[0080] It should be noted that the second insulating layer 710 is disposed between the second conductive layer 800 and the semiconductor layer, and the second insulating layer 710 is used to prevent short circuits in the electrodes of the semiconductor structure driving the transistor. Both the first semiconductor structure 160 and the second semiconductor structure 170 can be made of polysilicon. The second insulating layer 710 improves the film quality on the surface of the semiconductor layer in the channel region. When the display panel has a dual-gate structure, the high surface quality of the semiconductor layer reduces carrier scattering, and the dual-gate structure further optimizes the carrier transport path through dual electric field modulation, significantly improving mobility and device response speed.

[0081] Figure 9 This is a schematic partial top view of a pixel structure provided for an embodiment of this application. For example, refer to... Figure 9 The first gate 110 and the second gate 120 are connected to the same side of the gate line 200. The data signal line 100 can be multiplexed or shared with the first electrode of the driving transistor. The orthographic projection of the data signal line 100 on the substrate and the orthographic projection of the first electrode 130 on the substrate do not overlap with the orthographic projection of the pixel electrode 400 on the substrate. The orthographic projection of the first electrode 130 on the substrate falls within the orthographic projection of the first gate 110 on the substrate, and the orthographic projection of the second electrode 140 on the substrate is partially within the orthographic projections of the first gate and the second gate 120 on the substrate. The first gate 110, the second gate 120, the first electrode 130, and the second electrode 140 are all disposed on the same side of the gate line 200. When the driving transistor is not turned on, the data signal only reaches the first electrode 130 and is not transmitted to the second electrode 140 of the driving transistor. The potential of the pixel electrode will not fluctuate due to the signal transmission in the data signal line, and thus the capacitance formed between the pixel electrode and the electrode in the driving transistor will not fluctuate. When the driving transistor is turned on, the data signal is transmitted through the first electrode 130 to the second electrode 140 of the driving transistor. Since the orthographic projection of the first electrode 130 on the substrate layer does not overlap with the orthographic projection of the pixel electrode 400 on the substrate layer, the potential of the pixel electrode 400 will not fluctuate due to voltage changes in the first electrode 130 after the data signal passes through the first electrode 130. Consequently, the capacitance formed between the pixel electrode and the electrode in the driving transistor will not fluctuate. During the lighting process of adjacent rows or columns of pixels, regardless of whether the driving transistor is turned on or off, the data signal will not pull the voltage of the pixel electrode whose gate signal has not been transmitted to the pixel, thereby avoiding crosstalk between adjacent pixels and improving the display effect.

[0082] For example, refer to Figure 9A notch 123 is formed between the first gate 110 and the second gate 120 and the gate line, respectively. The orthographic projection of the notch 123 on the substrate overlaps with the orthographic projection of the second electrode 140 on the substrate. The orthographic projection of the second electrode 140 between the first gate 110 and the second gate 120 on the substrate does not overlap with the orthographic projections of the first gate 110 and the second gate 120 on the substrate. This reduces the parasitic capacitance between the first gate 110 and the second gate 120 and the second electrode 140, thereby improving the switching speed of the driving transistor.

[0083] Figure 10 A schematic partial top view of another pixel structure provided in an embodiment of this application. For example, refer to... Figure 10 The pixel structure also includes a storage capacitor for storing charge and discharging it to the pixel electrode. The storage capacitor includes a first electrode 300 and a second electrode 500 that are insulated from each other. The first electrode 300 is connected to the pixel electrode 400 via a second via 301, and the second electrode 500 is connected to a common signal line 600. The common signal line 600 provides a common signal voltage to the second electrode 500 to reduce pixel voltage drift caused by leakage or noise. The orthographic projection of the first electrode 300 onto the substrate 101 covers the orthographic projection of the second electrode 500 onto the substrate 101, achieving a higher capacitance value within a limited area and saving layout space in the pixel structure. The orthographic projection of the pixel electrode 400 onto the substrate 101 covers the orthographic projections of the first electrode 300 and the second electrode 500 onto the substrate 101, resulting in a more uniform electric field distribution, avoiding leakage or uneven brightness at pixel edges, and improving the display effect of the display panel.

[0084] For example, refer to Figure 9 The common signal line 600 extends in the same direction as the gate line. The first gate 110 and the second gate 120 are connected to the same side of the gate line 200. The second plate 500 is located between the common signal line 600 and the gate line 200.

[0085] For example, refer to Figure 10 The common signal line 600 extends in the same direction as the gate line. The first gate 110 and the second gate 120 are connected to different sides of the gate line 200. The first electrode 300 and the second electrode 500 are both located between the common signal line 600 and the gate line 200.

[0086] According to the arrangement direction of the first gate and the second gate in the driving transistor, the position of the plate of the storage capacitor is set accordingly to reasonably arrange the structure of the driving transistor and save the layout space of the pixel structure.

[0087] A second aspect of this application provides a display panel. The display panel includes a plurality of pixel structures as described in the first aspect, and the plurality of pixel structures are arranged in an array.

[0088] Figure 11 This is a schematic partial top view of a display panel provided in an embodiment of this application. For example, refer to... Figure 11 The display panel includes multiple arrayed pixel structures 1000, multiple gate lines, and multiple data signal lines. The gate lines are arranged along the row direction, and the data signal lines are arranged along the column direction. Each pixel structure 1000 is connected to one gate line and one data signal line. The gate line provides a gate signal, and the data signal line provides a data signal. Each row of pixels is connected to one gate line, and each column of pixels is connected to one data signal line. The multiple gate lines include G0, G1, G2…Gm-3, Gm-2, Gm-1, Gm-3, where m represents the total number of gate lines. The multiple data signal lines include S1, S2, S2…S… n-3 S n-2 S n-1 S n Here, n represents the total number of data signal lines. Each data signal line is electrically connected to one end of a driver chip IC, and the other end of the driver chip IC is electrically connected to the control motherboard. One end of the flexible circuit board is electrically connected to the display panel, and the other end is connected to the control motherboard.

[0089] The pixel structure provided in this application embodiment, in the dual-gate driving transistor, connects the first electrode of the first thin-film transistor to the data signal line, and the third electrode of the second thin-film transistor to the pixel electrode. The first and second thin-film transistors share a second electrode, and the orthographic projections of the first electrode and the data signal line on the substrate do not overlap with the orthographic projections of the pixel electrode on the substrate. The data signal line is connected to the first electrode of the first thin-film transistor for data signal transmission. When the first thin-film transistor is not turned on, the data signal only passes through the first electrode of the first thin-film transistor and is not transmitted to the pixel electrode through the second and third electrodes of the first and second thin-film transistors. Therefore, even if the data signal passes through the first electrode, or if the orthographic projections of the second and third electrodes overlap with the orthographic projection of the pixel electrode, the potential of the pixel electrode will not fluctuate due to voltage changes in the first electrode, thus preventing fluctuations in the capacitance formed between the pixel electrode and the electrodes in the driving transistor. During the illumination process of pixels in adjacent rows or columns, the data signal will not pull the voltage of the pixel electrode where the gate signal has not been transmitted to the pixel, thereby avoiding crosstalk between adjacent pixels and improving the display effect.

[0090] A third aspect of the embodiments of this application provides a display device. Figure 12This is a schematic structural diagram of a display device provided in an embodiment of this application. For example, refer to... Figure 12 The display device 3000 includes a second aspect display panel 2000.

[0091] The pixel structure provided in this application embodiment, in the dual-gate driving transistor, connects the first electrode of the first thin-film transistor to the data signal line, and the third electrode of the second thin-film transistor to the pixel electrode. The first and second thin-film transistors share a second electrode, and the orthographic projections of the first electrode and the data signal line on the substrate do not overlap with the orthographic projections of the pixel electrode on the substrate. The data signal line is connected to the first electrode of the first thin-film transistor for data signal transmission. When the first thin-film transistor is not turned on, the data signal only passes through the first electrode of the first thin-film transistor and is not transmitted to the pixel electrode through the second and third electrodes of the first and second thin-film transistors. Therefore, even if the data signal passes through the first electrode, or if the orthographic projections of the second and third electrodes overlap with the orthographic projection of the pixel electrode, the potential of the pixel electrode will not fluctuate due to voltage changes in the first electrode, thus preventing fluctuations in the capacitance formed between the pixel electrode and the electrodes in the driving transistor. During the illumination process of pixels in adjacent rows or columns, the data signal will not pull the voltage of the pixel electrode where the gate signal has not been transmitted to the pixel, thereby avoiding crosstalk between adjacent pixels and improving the display effect.

[0092] The display devices provided in this application embodiment may include televisions, computers, smartphones, smart wearable devices, laptops, and tablets, etc. Smart wearable devices may include smartwatches, AR (augmented reality) devices, and VR (virtual reality) devices, etc.

[0093] It should be noted that the descriptions of each embodiment in the above embodiments have different focuses. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0094] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

[0095] Although preferred embodiments have been described in this specification, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this specification.

[0096] Obviously, those skilled in the art can make various modifications and variations to this specification without departing from its spirit and scope. Therefore, if such modifications and variations fall within the scope of the claims and their equivalents, this specification is also intended to include such modifications and variations.

Claims

1. A pixel structure, characterized in that, include: Substrate layer; A driving transistor includes a first gate, a second gate, a first electrode, a second electrode, a third electrode, a first semiconductor structure, and a second semiconductor structure. The orthographic projection of the first gate on the substrate overlaps with the orthographic projection of the first semiconductor structure on the substrate, and the orthographic projection of the second gate on the substrate overlaps with the orthographic projection of the second semiconductor structure on the substrate. A gate line, wherein both the first gate and the second gate are connected to the gate line; A data signal line is connected to one end of the first electrode, the other end of the first electrode and one end of the second electrode are both connected to the first semiconductor structure, and the other end of the second electrode and one end of the third electrode are both connected to the second semiconductor structure. A pixel electrode is connected to the other end of the third electrode; The orthographic projection of the pixel electrode on the substrate layer does not overlap with the orthographic projection of the first electrode on the substrate layer, and the orthographic projection of the pixel electrode on the substrate layer does not overlap with the orthographic projection of the data signal line on the substrate layer.

2. The pixel structure according to claim 1, characterized in that, The first semiconductor structure includes a first channel region, and the second semiconductor structure includes a second channel region; The length direction of the first channel region is different from that of the second channel region.

3. The pixel structure according to claim 2, characterized in that, The length direction of the first channel region is the same as the length extension direction of the grid line; The length direction of the second channel region is the same as the length extension direction of the data signal line.

4. The pixel structure according to claim 2, characterized in that, The first gate and the second gate are respectively connected to different sides of the gate line.

5. The pixel structure according to claim 1, characterized in that, The second electrode includes a first structural portion and a second structural portion, wherein the first structural portion is connected to the first semiconductor structure, and the second structural portion is connected to the second semiconductor structure portion; Both the first structural part and the second structural part are strip-shaped structures, and the length extension direction of the first structural part is different from that of the second structural part; The orthographic projection of the first structural portion on the substrate layer partially overlaps with the orthographic projections of the gate line and the first gate electrode on the substrate layer; The orthographic projection of the second structural portion on the substrate layer does not overlap with the orthographic projection of the gate line on the substrate layer; The orthographic projection of the second structural portion on the substrate layer and the orthographic projection of the second gate on the substrate layer partially overlap.

6. The pixel structure according to claim 5, characterized in that, The orthographic projection of the first structural portion on the substrate layer overlaps or does not overlap with the orthographic projection of the pixel electrode on the substrate layer; And / or, The orthographic projection of the second structural part on the substrate layer does not overlap with the orthographic projection of the pixel electrode on the substrate layer.

7. The pixel structure according to claim 6, characterized in that, The connection point between the first structural portion and the first semiconductor structure is the first end, and the connection point between the second structural portion and the second semiconductor structure is the second end. The first end and the second end are located on different sides of the gate line, respectively.

8. The pixel structure according to claim 7, characterized in that, The first gate is located on different sides of the gate line at both ends along the length of the data signal line, and the second gate is located on different sides of the gate line at both ends along the length of the data signal line.

9. The pixel structure according to claim 8, characterized in that, The first gate has a third end and a fourth end at its two ends in the length direction of the data signal line, and the second gate has a fifth end and a sixth end at its two ends in the length direction of the data signal line. The third end and the fifth end are located on the same side of the gate line, and the fourth end and the sixth end are located on the same side of the gate line. Along the length of the data signal line, the end face of the third end extends beyond the end face of the fifth end, and the end face of the fourth end extends beyond the end face of the sixth end.

10. The pixel structure according to claim 1, characterized in that, The second electrode includes a first structural portion, a second structural portion, a third structural portion, and a fourth structural portion. The first structural portion is connected to the first semiconductor structure, the second structural portion is connected to the second semiconductor structure, the third structural portion is connected between the first structural portion and the fourth structural portion, and the fourth structural portion is connected between the third structural portion and the second structural portion. The length extension direction of the third structural portion is different from the length extension direction of the fourth structural portion. The orthographic projection of the first structural portion on the substrate falls within the orthographic projection of the first gate on the substrate, and the orthographic projection of the second structural portion on the substrate falls within the orthographic projection of the second gate on the substrate; The orthographic projection of the third structural portion on the substrate layer does not overlap with the orthographic projections of the first gate and the second gate on the substrate layer; The orthographic projection of the fourth structural portion on the substrate layer does not overlap with the orthographic projections of the first gate and the second gate on the substrate layer.

11. The pixel structure according to claim 10, characterized in that, The orthogonal projection of the pixel electrode on the substrate completely covers the orthogonal projection of the first structural part on the substrate; The orthographic projection of the pixel electrode on the substrate layer does not overlap with the orthographic projections of the second, third, and fourth structural portions on the substrate layer.

12. The pixel structure according to claim 1, characterized in that, The first gate and the second gate are connected to the same side of the gate line. The first gate and the second gate are respectively connected to the gate line with a gap. The orthogonal projection of the gap on the substrate overlaps with the orthogonal projection of the second electrode on the substrate.

13. The pixel structure according to claim 1, characterized in that, The data signal line is connected to the first semiconductor structure through a first via, and the orthogonal projection of the first via on the substrate falls on the orthogonal projection of the data signal line on the substrate.

14. The pixel structure according to any one of claims 2 to 13, characterized in that, Also includes: A storage capacitor, the storage capacitor comprising a first electrode plate and a second electrode plate that are insulated from each other; The first electrode plate is connected to the pixel electrode through a second via, the second electrode plate is connected to a common signal line, and the orthogonal projection of the first electrode plate on the substrate layer covers the orthogonal projection of the second electrode plate on the substrate layer. The orthogonal projection of the pixel electrode on the substrate layer overlaps the orthogonal projections of the first electrode plate and the second electrode plate on the substrate layer.

15. The pixel structure according to claim 14, characterized in that, The common signal line extends in the same direction as the gate line, wherein the second electrode is located between the gate line and the common signal line.

16. A display panel, characterized in that, include: A plurality of pixel structures as described in any one of claims 1 to 15, wherein the plurality of pixel structures are arranged in an array.

17. A display device, characterized in that, include: The display panel as described in claim 16.

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