Electronic circuits and electronic systems

Abstract

This application relates to electronic circuits and electronic systems. An electronic circuit includes: a first transistor having a first terminal, a second terminal, and a control terminal; a first resistor having a first terminal coupled to the control terminal of the first transistor and a second terminal coupled to a power supply terminal; a bandgap reference circuit having a first terminal coupled to the first terminal of the first transistor and configured to generate a bandgap voltage; an adjustment circuit having an input terminal coupled to the bandgap reference circuit, a first output terminal coupled to the control terminal of the first transistor and the first terminal of the first resistor, and a second output terminal, and configured to adjust the bandgap voltage via the first transistor; and an output stage coupled to the bandgap reference circuit and the second output terminal of the adjustment circuit, and configured to generate a power-on reset (POR) signal based on the difference between a first current determined by the first resistor and a second current based on the bandgap voltage.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit and priority of Indian Provisional Application No. 202441035687, filed on 6 May 2024, which is incorporated herein by reference in its entirety. Technical Field

[0003] This article deals with electronic circuits and electronic systems. Background Technology

[0004] When power is applied to a system (e.g., a chip), the power-on reset (POR) circuit monitors the supply voltage level. If the supply voltage level rises above a certain threshold (which may be called the POR threshold), it generates a reset signal (which may be called the POR signal) to ensure the system starts from a clean state. POR generation is an important part of the timing control of all modules in the system, where deterministic signals are required to ensure that downstream modules operate reliably. Utility Model Content

[0005] In one aspect, an electronic circuit is provided, comprising: a first transistor having a first terminal, a second terminal, and a control terminal; a first resistor having a first terminal coupled to the control terminal of the first transistor and a second terminal coupled to a power supply terminal; a bandgap reference circuit having a first terminal coupled to the first terminal of the first transistor and configured to generate a bandgap voltage; an adjustment circuit having an input terminal coupled to the bandgap reference circuit, a first output terminal coupled to the control terminal of the first transistor and the first terminal of the first resistor, and a second output terminal, and configured to adjust the bandgap voltage via the first transistor; and an output stage coupled to the bandgap reference circuit and the second output terminal of the adjustment circuit, and configured to generate a power-on reset (POR) signal based on the difference between a first current determined by the first resistor and a second current based on the bandgap voltage.

[0006] In some examples, a second terminal of the first transistor is coupled to a power supply terminal, and the bandgap reference circuit includes: a first branch coupled between a first terminal and a ground terminal of the bandgap reference circuit, and the first branch includes a second transistor; and a second branch coupled between a first terminal and a ground terminal of the bandgap reference circuit, and the second branch includes a third transistor and a second resistor between the first terminal and the third transistor of the bandgap reference circuit, wherein the bandgap reference circuit has a second terminal coupled to a control terminal of the second transistor and a control terminal of the third transistor, and wherein a bandgap voltage is provided between the second terminal and the first terminal of the bandgap reference circuit.

[0007] In some examples, the second transistor and the third transistor each include a bipolar transistor, and the second resistor can be configured such that the voltage drop across the second resistor corresponds to the difference between the base-emitter voltage of the second transistor and the base-emitter voltage of the third transistor.

[0008] In some examples, the bandgap reference circuit further includes: a third resistor coupled between a second terminal of the bandgap reference circuit and a ground terminal; a fourth resistor coupled in a first branch of the bandgap reference circuit between a second transistor and a first terminal of the bandgap reference circuit; and a fifth resistor coupled in a second branch of the bandgap reference circuit between the second resistor and a first terminal of the bandgap reference circuit.

[0009] In some examples, the bandgap reference circuit further includes a resistor divider circuit coupled between a first terminal and a second terminal of the bandgap reference circuit, wherein the resistor divider circuit can be configured to form one or more tap points.

[0010] In some examples, for each of the one or more taps, the bandgap reference circuit also includes a corresponding filter circuit coupled to that tap.

[0011] In some examples, the output stage includes a fourth transistor and a sixth resistor. The fourth transistor has a control terminal coupled to any one of a first terminal of a bandgap reference circuit, a second terminal of a bandgap reference circuit, or a first output terminal of a regulation circuit. The fourth transistor also has a first terminal coupled to a ground terminal via the sixth resistor, wherein a second current is also determined by the sixth resistor.

[0012] In some examples, at least one of the resistance values ​​of the first resistor and the sixth resistor is adjustable.

[0013] In some examples, the output stage includes: a mirror branch of a first current mirror circuit, which can be configured to mirror a first current and includes a fifth transistor in its mirror branch; a second current mirror circuit, which can be configured to mirror a second current and includes a sixth transistor in its mirror branch; and a seventh transistor and a seventh resistor, the seventh transistor including a control terminal coupled to a third terminal, a first terminal coupled to a power supply terminal, and a second terminal coupled to a ground terminal via the seventh resistor, the third terminal being between the fifth and sixth transistors, wherein the output stage can be configured to generate a power-on reset signal based on a voltage at a fourth terminal, the fourth terminal being between the second terminal of the seventh transistor and the seventh resistor.

[0014] In some examples, the mirror branch of the second current mirror circuit also includes an eighth transistor between the sixth transistor and the third terminal.

[0015] In some examples, the adjustment circuit includes a first input terminal and a second input terminal, the first input terminal being coupled between a second transistor and a first terminal of a bandgap reference circuit, and the second input terminal being coupled between a second resistor and a first terminal of a bandgap reference circuit.

[0016] In some examples, the regulating circuit also includes a ninth transistor having a first terminal coupled to a ground terminal and a second terminal coupled to a power supply terminal via a first resistor, and the ninth transistor can be configured to turn off when the voltage at the first input terminal of the regulating circuit is greater than the voltage at the second input terminal of the regulating circuit, or to turn on when the voltage at the first input terminal of the regulating circuit is less than the voltage at the second input terminal of the regulating circuit.

[0017] In some examples, the regulation circuit further includes: a differential input stage including a first branch and a second branch, each branch of the differential input stage including one or more transistors, each of the one or more transistors having a control terminal coupled to a corresponding one of the first input terminal and the second input terminal of the regulation circuit; a third current mirror circuit configured to mirror a third current output from the first branch of the differential input stage to the control terminal of the ninth transistor; and a fourth current mirror circuit configured to mirror a fourth current output from the second branch of the differential input stage to the control terminal of the ninth transistor.

[0018] In some examples, the electronic circuit also includes a bias current generation circuit comprising: a fifth current mirror circuit including a reference branch having a tenth transistor and a mirror branch having an eleventh transistor, both the first terminals of the tenth and eleventh transistors being coupled to a power supply terminal; and a twelfth transistor and an eighth resistor, the twelfth transistor including a first terminal coupled to a ground terminal via the eighth resistor, a second terminal coupled to a second terminal of the tenth transistor, and a control terminal coupled to any one of a first terminal of a bandgap reference circuit, a second terminal of the bandgap reference circuit, or a first output terminal of a regulation circuit, wherein the bias current generation circuit can be configured to generate a bias current at a fifth terminal coupled to a second terminal of the eleventh transistor.

[0019] In some examples, the resistance value of the eighth resistor is adjustable.

[0020] In some examples, the reference branch of the fifth current mirror circuit also includes a diode-connected thirteenth transistor, which lies between the tenth and twelfth transistors.

[0021] In some examples, the electronic circuit also includes at least one of the following: a fourteenth transistor in a mirror branch of a third current mirror circuit, the control terminal of the fourteenth transistor being coupled to the control terminal of a thirteenth transistor; or a fifteenth transistor in a mirror branch of a fourth current mirror circuit, the control terminal of the fifteenth transistor being coupled to the control terminal of a thirteenth transistor; or a sixteenth transistor in a mirror branch of a fifth current mirror circuit, the control terminal of the sixteenth transistor being coupled to the control terminal of a thirteenth transistor.

[0022] In some examples, the regulation circuit further includes a seventeenth transistor and a ninth resistor, wherein the differential input stage is coupled to a ground terminal via the seventeenth transistor and the ninth resistor, wherein the seventeenth transistor includes a first terminal coupled to a ground terminal via the ninth resistor, a second terminal coupled to the differential input stage, and a control terminal coupled to any one of the first terminal of the bandgap reference circuit, the second terminal of the bandgap reference circuit, or the first output terminal of the regulation circuit.

[0023] In some examples, the electronic circuit also includes an additional supply voltage generation circuit, which includes an eighteenth transistor and a tenth resistor. The eighteenth transistor includes a control terminal coupled to a control terminal of a first transistor, a first terminal coupled to a ground terminal via the tenth resistor, and a second terminal coupled to a power supply terminal. The additional supply voltage generation circuit can be configured to generate an additional supply voltage based on a voltage at a sixth terminal located between the first terminal of the eighteenth transistor and the tenth resistor.

[0024] In some examples, the additional supply voltage generation circuit also includes a filter circuit between the control terminal of the eighteenth transistor and the control terminal of the first transistor.

[0025] In some examples, the first transistor includes a metal-oxide-semiconductor transistor.

[0026] In some examples, the first transistor and the fourth transistor each include a low-voltage threshold transistor.

[0027] In another aspect, an electronic system is provided, comprising: electronic circuitry according to any example of the foregoing aspects; and circuitry coupled to an output stage, the circuitry being configurable to operate based on a power-on reset signal. Attached Figure Description

[0028] Figure 1 These are schematic block diagrams of electronic circuits in some examples.

[0029] Figure 2 These are circuit diagrams of electronic circuits in some examples.

[0030] Figure 3 These are circuit diagrams of electronic circuits in some examples.

[0031] Figure 4 These are circuit diagrams of electronic circuits in some examples.

[0032] Figure 5 These are circuit diagrams of electronic circuits in some examples.

[0033] Figure 6 These are circuit diagrams of electronic circuits in some examples.

[0034] Note that in the embodiments described below, the same reference numerals are sometimes shared in different figures to denote the same parts or parts having the same function, and repeated descriptions of them will be omitted. In this specification, similar reference numerals and letters are used to refer to similar items; therefore, once an item is defined in one figure, it is not necessary to describe it further in subsequent figures.

[0035] For ease of understanding, the positions, dimensions, and extents of structures shown in the accompanying drawings and other materials do not necessarily represent their actual positions, dimensions, and extents. Therefore, this description is not limited to the positions, dimensions, and extents described in the accompanying drawings and other materials. Furthermore, the drawings are not necessarily drawn to scale, and some features may be enlarged to show details of specific components. Detailed Implementation

[0036] Various illustrative embodiments will now be described in detail with reference to the accompanying drawings. It should be noted that the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of this application, unless otherwise stated.

[0037] The following description of at least one example is merely illustrative in nature and in no way limiting. Those skilled in the art will recognize that they are intended only to illustrate exemplary implementations, not exhaustive ones.

[0038] Techniques, methods, and equipment known to those skilled in the art need not be described in detail, but may be considered part of the instruction manual where appropriate.

[0039] It should be understood that although the accompanying drawings primarily illustrate metal-oxide-semiconductor (MOS) transistors or bipolar transistors as examples of transistors, this description is not limited to these and any other suitable transistor may be used.

[0040] It should also be understood that, as used herein, a transistor's control terminal can refer to the terminal used to control the current flow and on / off state of the transistor, and a transistor's terminals other than the control terminal can refer to the terminals through which current or signals are input to / output from the transistor. For example, for a MOS transistor, its control terminal is the gate, and its other terminals are the source and drain, while for a bipolar transistor, its control terminal is the base, and its other terminals are the emitter and collector.

[0041] It should also be understood that, as used herein, a first conductivity type can be defined as causing the transistor to conduct when its control terminal is low, and a second conductivity type can be defined as causing the transistor to conduct when its control terminal is high. For example, for a MOS transistor, the first conductivity type is P-type and the second conductivity type is N-type, while for a bipolar transistor, the first conductivity type is PNP-type and the second conductivity type is NPN-type.

[0042] It should also be understood that, as used herein, power and ground are relative concepts; they exist relative to each other and are used to describe the polarity and direction of voltage in a circuit. For example, power represents a high level, and ground represents a low level.

[0043] It should also be understood that, as used herein, when an element is described as “capable of being configured to” do something, this can mean that the element is configured to do something, for example, when the circuit is energized.

[0044] As the supply voltage for integrated circuit (IC) design decreases, the voltage margin available for analog intellectual property (IP) also decreases. Inaccurate voltage ratings (PORs) reduce the minimum usable margin of IP, making all downstream IP designs more challenging than they might otherwise require.

[0045] This description provides an electronic circuit capable of generating an accurate POR signal. This relaxes the voltage margin, thus benefiting downstream IP design. Various examples of this electronic circuit are described in detail below with reference to the accompanying drawings. Actual circuits may have some additional components. However, in order not to obscure the main points of this document, these additional components are not described herein and are not shown in the accompanying drawings.

[0046] Figure 1 These are schematic block diagrams of electronic circuits 100 in some examples. For example... Figure 1 As shown, the electronic circuit 100 includes a bandgap reference circuit 102, an adjustment circuit 104, an output stage 106, a first transistor 108, and a first resistor 110.

[0047] The bandgap reference circuit 102 can be configured to generate a bandgap voltage. The bandgap voltage can be provided between the first terminal F of the bandgap reference circuit 102 and the second terminal of the bandgap reference circuit 102.

[0048] like Figure 1 As shown, a first terminal F of the bandgap reference circuit 102 is coupled to a first transistor 108, which has a control terminal coupled to a power supply VDD via a first resistor 110. Specifically, the first transistor 108 may include a first terminal coupled to the first terminal F of the bandgap reference circuit 102 and a second terminal coupled to the power supply VDD. In some examples, the first transistor 108 may include a low-voltage-threshold (LVT) transistor. As the power supply VDD rises from 0 volts (V), due to the presence of the first resistor 110, the voltage at the control terminal of the first transistor 108 may be equal to the power supply VDD, and the first transistor 108 may cause the voltage at the first terminal F of the bandgap reference circuit 102 to rise with the power supply VDD.

[0049] refer to Figure 1The adjustment circuit 104 is coupled to the bandgap reference circuit 102 and can be configured to adjust the bandgap voltage. Specifically, the adjustment circuit 104 includes an output terminal coupled to the control terminal of the first transistor 108. In this way, the voltage at the output terminal of the adjustment circuit 104 determines the voltage at the control terminal of the first transistor 108, which in turn determines the voltage at the first terminal F of the bandgap reference circuit 102. The bandgap voltage generated by the bandgap reference circuit 102 can therefore be adjusted by the adjustment circuit 104.

[0050] Furthermore, the output stage 106 is coupled to the bandgap reference circuit 102 and the regulation circuit 104. The output stage 106 can be configured to generate a POR signal based on the difference between a first current determined by the first resistor 110 and a second current determined by the bandgap voltage. The bandgap reference circuit 102 and the regulation circuit 104 can operate as a closed loop with negative feedback. Due to the closed-loop effect, the generated POR signal is immune to power supply noise and is as accurate as the bandgap precision, even if the power supply noise is high.

[0051] For illustrative purposes, the following will refer to Figures 2 to 6 More details describing electronic circuit 100.

[0052] Figure 2 This is a circuit diagram illustrating a non-limiting example 200A of an electronic circuit 100 in some examples. For example... Figure 2 As shown, electronic circuit 200A includes bandgap reference circuit 202, adjustment circuit 204, output stage 206, first transistor M8, and first resistor R9, which respectively correspond to... Figure 1 The bandgap reference circuit 102, adjustment circuit 104, output stage 106, first transistor 108, and first resistor 110 are shown.

[0053] exist Figure 2In the example, a first transistor M8, such as an N-type MOS (NMOS) transistor, has a gate coupled to power supply VDD, a drain coupled to power supply VDD, and a source coupled to a first terminal F of bandgap reference circuit 202 via a first resistor R9. Bandgap reference circuit 202 includes a first branch 2022 and a second branch 2024. The first branch 2022 is coupled between the first terminal F and ground GND. The first branch 2022 includes a second transistor Q0, such as a PNP bipolar junction transistor (BJT), and a fourth resistor R4 coupled between the emitter of the second transistor Q0 and the first terminal F. The second branch 2024 is coupled between the first terminal F and ground GND. The second branch 2024 includes a third transistor Q1, such as a PNP BJT transistor, and a second resistor R6 and a fifth resistor R5 coupled between the emitter of the third transistor Q1 and the first terminal F. The bases of transistors Q0 and Q1 are both coupled to the second terminal G of the bandgap reference circuit 202. The second terminal G is also coupled to ground GND via a third resistor R3. The third resistor R3 provides a current path to the bases of transistors Q0 and Q1, preventing voltage drift due to charge buildup. In an alternative example, the third resistor R3 can be replaced with a constant current source to precisely control the base currents of transistors Q0 and Q1, or it can be removed if the base currents of transistors Q0 and Q1 are low.

[0054] Bandgap voltage (V) BG A voltage V is generated between the first terminal F and the second terminal G, which is equal to the voltage V at the first terminal F. F The voltage V at the second terminal G G The difference between them. The bandgap reference circuit 202 is based on a Brokaw cell, where transistors Q0 and Q1 are a Brokaw pair. Transistors Q0 and Q1 have an emitter area ratio of 1:N. The base-emitter voltage V of the second transistor Q0. BE0 Provides a CTAT (Complementary to absolute temperature) voltage, and the base-emitter voltage V of the second transistor Q0. BE0 The base-emitter voltage V of the third transistor Q1 BE1 The difference ΔV between BE Provides a PTAT (Proportional to absolute temperature) voltage. The voltage drop across the second resistor R6 corresponds to ΔV. BETherefore, in response to circuit energization, the CTAT current generated in the first branch 2022 and the PTAT current generated in the second branch 2024 can result in a bandgap voltage V with essentially zero temperature coefficient. BG In some examples, the second resistor R6 includes a PTAT resistor, thus enabling temperature compensation by dynamically adjusting the PTAT current in the second branch 2024. In this way, the generated bandgap voltage V... BG It can have improved temperature stability. In addition, the ratio between the resistance values ​​of the fourth resistor R4 and the fifth resistor R5 can be adjusted to control the ratio between the CTAT current in the first branch 2022 and the PTAT current in the second branch 2024 for temperature compensation.

[0055] The regulation circuit 204 includes a differential input stage 2042. In some examples, such as... Figure 2 As shown, the differential input stage 2042 includes a first branch with an NMOS transistor M0 and a second branch with an NMOS transistor M1. The gate of transistor M1 provides a first input terminal of the regulation circuit 204 and is coupled to terminal A between a fourth resistor R4 and a second transistor Q0. The gate of transistor M0 provides a second input terminal of the regulation circuit 204 and is coupled to terminal B between a fifth resistor R5 and a second resistor R6. For example, the sources of transistors M0 and M1 are both coupled to the drain of a seventeenth transistor M21, which is, for example, an NMOS transistor. For example, the source of the seventeenth transistor M21 is coupled to ground GND via a ninth resistor R7, and the gate of the seventeenth transistor M21 is coupled to a second terminal G. The seventeenth transistor M21 and the ninth resistor R7 provide a tail current source for the differential input stage 2042. In some examples, the seventeenth transistor M21 includes an LVT transistor with a threshold voltage V close to 0 V. th_M21 When transistor M21 is turned on, its gate-source voltage V GS_M21 It is also close to 0 V. Therefore, when the regulated supply voltage (in some examples, such as in...) Figure 2 In the example, V G When applied to the gate of transistor M21, it can provide a regulated tail current source.

[0056] The regulating circuit 204 also includes a third current mirror circuit 2044, which can be configured to mirror a third current output from the first branch (e.g., M0) of the differential input stage 2042 to the gate of a ninth transistor M7, such as an NMOS transistor. For example, the third current mirror circuit 2044 includes a current mirror formed by a pair of P-type MOS (PMOS) transistors M13 and M14, whose gates are coupled together. The drain of transistor M13 is coupled to the drain of transistor M0, and the source of transistor M13 is coupled to the power supply VDD. Furthermore, in some examples, the gate of transistor M13 is coupled to its drain, thus being diode-connected and self-biased. The drain of transistor M14 is coupled to terminal S and then to the gate of transistor M7, and the source of transistor M14 is coupled to the power supply VDD. Here, transistor M13 serves as the reference transistor in the current mirror, and transistor M14 serves as the mirror transistor in the current mirror.

[0057] The regulation circuit 204 also includes a fourth current mirror circuit 2046, which can be configured to mirror a fourth current output from the second branch (e.g., M1) of the differential input stage 2042 to the gate of the ninth transistor M7. For example, the fourth current mirror circuit 2046 includes a first current mirror formed by a pair of PMOS transistors M11 and M12 and a second current mirror formed by a pair of NMOS transistors M2 and M3, the gates of the PMOS transistors M11 and M12 being coupled together, and the gates of the NMOS transistors M2 and M3 being coupled together. The drain of transistor M11 is coupled to the drain of transistor M1, and the source of transistor M11 is coupled to the power supply VDD. Furthermore, in some examples, the gate of transistor M11 is coupled to its drain, thus being diode-connected and self-biased. The drain of transistor M12 is coupled to the drain of transistor M2, and the source of transistor M12 is coupled to the power supply VDD. Here, transistor M11 serves as the reference transistor in the first current mirror, and transistor M12 serves as the mirror transistor in the first current mirror. Furthermore, the source of transistor M2 is coupled to ground (GND). In some examples, the gate of transistor M2 is coupled to its drain, thus being diode-connected and self-biased. The drain of transistor M3 is coupled to terminal S and then to the gate of transistor M7, and the source of transistor M3 is coupled to ground (GND). Here, transistor M2 serves as the reference transistor in the second current mirror, and transistor M3 serves as the mirror transistor in the second current mirror. Additionally, capacitor C0 may be coupled between the gate of transistor M7 and ground (GND) to eliminate noise.

[0058] The ninth transistor M7 has a source coupled to ground GND and a drain coupled to the power supply VDD via a first resistor R9. The terminal H between the drain of the ninth transistor M7 and the first resistor R9 provides the output terminal of the regulation circuit 204 and is coupled to the gate of the first transistor M8. In some examples, the first transistor M8 includes an LVT transistor with a threshold voltage V close to 0 V. th_M8 When the first transistor M8 is turned on, its gate-source voltage V GS_M8 It is also close to 0 V, which means that the voltage V at the output terminal H is close to 0 V. H Approximately equal to V F As the power supply VDD begins to rise from 0 V, for low VDD, due to the difference in saturation current between transistors Q0 and Q1, the voltage V at the first input terminal A of the regulating circuit 204 increases. A The voltage V at the second input terminal B of the regulating circuit 204 is greater than the voltage V. B This ensures that transistor M7 is initially off. Due to the first resistor R9, V H It becomes equal to VDD, and the first transistor M8 starts to make V F The leakage of transistor M3 contributes to terminal H starting with VDD. This is a self-starting circuit where the output terminal H of regulating circuit 204 is coupled to the power supply VDD via the first resistor R9, which enables reliable startup. With V F As VDD rises further, so does V. B >V A At this time, transistor M7 turns on and begins to draw current from resistor R9, thus the loop begins to use the bandgap voltage V. BG Adjust terminal H (or F). This gives an accuracy equal to the untrimmed bandgap variation. Since the ring uses the Brokaw cell as a reference, the final voltage to which the ring is adjusted is within a tight range.

[0059] The output stage 206 includes a fourth transistor M9 and a sixth resistor R8. In some examples, such as... Figure 2 As shown, the fourth transistor M9, such as an NMOS transistor, includes a gate coupled to the second terminal G and a source coupled to ground GND via a sixth resistor R8. In some examples, transistor M9 includes an LVT transistor with a threshold voltage V close to 0 V. th_M9 When transistor M9 is turned on, its gate-source voltage V0 GS_M9 It is also close to 0 V, which means that the voltage V at the second terminal G is... G Approximately equal to the source voltage V of transistor M9 S_M9 .

[0060] Output stage 206 also includes a fifth transistor M4, such as an NMOS transistor, located in a mirror branch of the first current mirror circuit 2062. Transistor M4 forms a current mirror with transistor M7. For example, transistor M4 has a gate coupled to the gate of transistor M7, a source coupled to ground GND, and a drain coupled to the third terminal C. Here, transistor M7 serves as a reference transistor in the current mirror, and transistor M4 serves as a mirror transistor in the current mirror. Output stage 206 also includes a second current mirror circuit 2064. In the second current mirror circuit 2064, a sixth transistor M6, such as a PMOS transistor, forms a current mirror with PMOS transistor M5. The gates of transistors M5 and M6 are coupled together. The drain of transistor M5 is coupled to the drain of transistor M9, and the source of transistor M5 is coupled to the power supply VDD. Furthermore, in some examples, the gate of transistor M5 is coupled to its drain, and is therefore diode-connected and self-biased. The drain of transistor M6 is coupled to the third terminal C, and the source of transistor M6 is coupled to the power supply VDD. Here, transistor M5 is used as the reference transistor in the current mirror, and transistor M6 is used as the mirror transistor in the current mirror.

[0061] Output stage 206 also includes a seventh transistor M10 and a seventh resistor R10. In some examples, the seventh transistor M10, such as a PMOS transistor, includes a gate coupled to the third terminal C, a source coupled to the power supply VDD, and a drain coupled to ground GND via the seventh resistor R10. The fourth terminal D between the drain of transistor M10 and resistor R10 can be further coupled to the input terminal of Schmitt trigger ST0. A POR signal can then be generated at the output terminal of Schmitt trigger ST0. Specifically, when the current I through transistor M4... M4 Greater than the current I through transistor M6 M6 When I is in a certain state, transistor M10 can be configured to conduct, thereby pulling the voltage at the fourth terminal D towards VDD, or when I... M4 Less than I M6 When I is turned off, transistor M10 can be configured to turn off, thereby pulling the voltage at the fourth terminal D down toward GND. Therefore, when I M4 M6 When, the POR signal can be configured to be low, or when I M4 >I M6 At this time, the POR signal can be configured to be high. Using these current mirrors, I... M4 Corresponding to the current flowing through transistor M7, which is also the current flowing through resistor R9, VDD and V are applied across resistor R9. H (It is approximately equal to V) F The difference between ) and I M6 ​The current flowing through transistor M5 is also the current flowing through resistor R8, across which the source voltage V of transistor M9 is applied. S_M9 (It is approximately equal to V) BG Related V G The difference between I and GND. Therefore, as the power supply VDD increases further, when I M4 >I M6 At this time, the generated POR signal toggles from low to high. Similarly, during a power outage, as the power supply VDD decreases, when I... M4 M6 At that time, the generated POR signal flips from high to low.

[0062] Figure 3 This is a circuit diagram of a non-limiting example 200B of an electronic circuit 100, showing some examples.

[0063] Except for the following differences, electronic circuit 200B is the same as electronic circuit 200A. Figure 3 In the example shown, the first branch of the differential input stage 2042 includes two NMOS transistors M0a and M0b coupled in series, their gates coupled together to the second input terminal B, and the second branch of the differential input stage 2042 includes two NMOS transistors M1a and M1b coupled in series, their gates coupled together to the first input terminal A. In some cases, this helps to avoid transistor breakdown. Additionally, in some examples, the output stage 206 also includes an eighth transistor M24, such as a PMOS transistor, which is coupled in series with transistor M6 in the mirror branch of the second current mirror circuit 2064 to protect transistor M6 from breakdown. Voltage V CAS It can be applied to the gate of transistor M24 to provide it with bias.

[0064] Furthermore, in some examples, electronic circuit 200B includes a resistor divider circuit 2026 coupled between the first terminal F and the second terminal G of bandgap reference circuit 202. For example... Figure 3 As shown, the resistor divider circuit 2026 includes two resistors, R1 and R2, which are connected in series between the first terminal F and the second terminal G, with a tap point K provided between R1 and R2. Therefore, the voltage at tap point K can be expressed as V. K =(V BG / (R1+R2))·(R2+R3). Additionally, the voltage at the second terminal G can be expressed as V. G =(V BG / (R1+R2))·(R3), and the voltage at the first terminal F can be expressed as V F =(V BG / (R1+R2))·(R1+R2+R3).​

[0065] The voltage V at the first terminal F F Relative to bandgap voltage V BG It is amplified by a ratio of ((R1+R2+R3) / (R1+R2)) and is easily adjustable in response to adjustments in the values ​​of any one or more of resistors R1, R2, and R3. Similarly, V G and V K It is also easily adjustable. Due to the low threshold voltage of transistor M8, the voltage at terminal H is approximately expressed as V. H ≈V F =(V BG / (R1+R2))·(R1+R2+R3). Therefore, each of H, F, G, and K can provide a regulated supply voltage to the components within electronic circuit 200B. Figure 3 In the example shown, the gates of transistors M9 and M21 are coupled to tap point K instead of as shown. Figure 2 The second terminal G in the circuit. In addition, each of H, F, G and K provides low output impedance, so that a ready-made supply voltage can be provided for other modules after the electronic circuit 200B. This supply voltage is noise-immune due to regulation, thus providing a power supply rejection ratio (PSRR) advantage for subsequent modules.

[0066] For example, in the gate of transistor M9 coupled to Figure 3 Given tap point K, the POR threshold can be given as follows. M4 Corresponding to applying (VDD-V) across it F The current through resistor R9, and I M6 Corresponding to applying V across it K The current flowing through resistor R8. When I M4 >I M6 When the POR flips from low to high, it occurs. Assuming R1 = R3 to simplify calculations, then V... K =(V BG / (R1+R2))·(R2+R3)=V BG And V F =(V BG / (R1+R2))·(R1+R2+R3)=m·V BG Where m = ((R1+R2+R3) / (R1+R2)). In this case, I M4 >I M6 This leads to (VDD-m·V) BG ) / R9>V BG / R8, thus having VDD>m·V BG·R9·(1 / R9+1 / (m·R8)). Therefore, in this case, the response is that VDD increases beyond m·V BG ·R9·(1 / R9+1 / (m·R8)) generates a high POR signal.

[0067] Similarly, if the gate of transistor M9 is alternatively coupled to Figure 3 If the first terminal F is given, then the POR threshold is given as follows. M4 Corresponding to applying (VDD-V) across it F The current through resistor R9, and I M6 Corresponding to applying V across it F The current flowing through resistor R8. When I M4 >I M6 When POR flips from low to high. V F =(V BG / (R1+R2))·(R1+R2+R3)=m·V BG Where m = ((R1+R2+R3) / (R1+R2)). In this case, I M4 >I M6 This leads to (VDD-m·V) BG ) / R9>(m·V BG ) / R8, thus having VDD>m·V BG ·(1+R9 / R8). Therefore, in this case, the response to VDD rising above m·V BG ·(1+R9 / R8) generates a high POR signal.

[0068] The POR threshold is easily adjustable and programmable in response to adjustments in the resistance values ​​of at least one of resistors R8 and R9, and can be higher than V. BG The adjustable POR threshold provides high flexibility in circuit design because, for most analog IPs, the POR threshold varies depending on the specific circuit and actual use case. Hysteresis can also be achieved by changing these parameters (such as R3) in the above equation based on the POR signal. A high POR signal is generated only when the loop has been regulated, and it is accurate to the level of the untrimmed bandgap voltage. No external or coarse reference is required to verify the generated POR signal.

[0069] In some examples, electronic circuit 200B also includes a filter circuit 2028 coupled to tap point K. Figure 3 In the example shown, the filter circuit 2028 includes a resistor R12 and a capacitor C1, with resistor R12 coupled between terminal W and tap point K, and capacitor C1 coupled between terminal W and ground GND. Therefore, terminal W can be configured to provide a clean (meaning low-noise or noise-free) regulated supply voltage V.sr Modules supplied with a clean supply voltage are more reliable. This reduces the need for sub-regulators, alleviates sub-regulator margin issues, saves space occupied by sub-regulators, and simplifies power supply timing control. Furthermore, both F and K can serve as references, for example, for some analog-sensitive IPs or circuits.

[0070] Additionally, in some examples, the resistor divider circuit 2026 can be configured to form multiple taps, each tap providing an regulated supply voltage determined based on the bandgap voltage and the corresponding resistance ratio. For each of the multiple taps, a corresponding filter circuit can be coupled to that tap to eliminate noise.

[0071] The differential input stage 2042 is used as a comparator to compare the voltage V at the first input terminal A of the adjustment circuit 204. A The voltage V at the second input terminal B of the regulating circuit 204 B The third current mirror circuit 2044 and the fourth current mirror circuit 2046 operate to provide high gain to the loop. Utilizing the differential input stage and these current mirror circuits, the regulation circuit 204 can be used as an amplifier that regulates the supply voltage with high DC gain, making the supply voltage noise-resistant and offering advantages in terms of PSRR.

[0072] Figure 4 This is a circuit diagram of a non-limiting example 200C of an electronic circuit 100 shown in some examples.

[0073] Except for the following differences, electronic circuit 200C is the same as electronic circuit 200B. For example... Figure 4 As shown, electronic circuit 200C also includes a bias current generation circuit 2048. For example, the bias current generation circuit 2048 includes a fifth current mirror circuit comprising a tenth transistor M15 and an eleventh transistor M16. Transistors M15 and M16, such as PMOS transistors, form a current mirror; their gates are coupled together and their sources are both coupled to the power supply VDD. Furthermore, in some examples, the gate of transistor M15 is coupled to its drain, thus being diode-connected and self-biased. The drain of transistor M16 is coupled to terminal L, where a bias current I is generated. bias Here, transistor M15 is the reference transistor in the current mirror, and transistor M16 is the mirror transistor in the current mirror.

[0074] The bias current generation circuit 2048 also includes a twelfth transistor M22, such as an NMOS transistor, and an eighth resistor R0. For example, transistor M22 includes a source coupled to ground GND via resistor R0, a drain coupled to the drain of transistor M15, and a gate coupled to tap point K. In some examples, transistor M22 includes an LVT transistor with a threshold voltage V close to 0 V. th_M22 When transistor M22 is turned on, its gate-source voltage V GS_M22 It is also close to 0 V, which means that the voltage V at tap point K is... K Approximately equal to the source voltage V of transistor M22 S_M22 The voltage drop across resistor R0 is equal to the source voltage V of transistor M22. S_M22 The difference between GND and R0, therefore the current through resistor R0 is approximately equal to (V K / R0). Therefore, the bias current I bias It can be adjusted and is easily adjustable in response to changes in the resistance value of resistor R0. The adjusted bias current I... bias It can help start the rest of the timing control modules.

[0075] Because the IPs work together, dependencies may exist during startup, and the IPs may depend on each other's bias current for reliable startup. A bandgap generator can provide the initial bias current to the IPs. However, this can be unreliable at the minimum supply voltage where the POR signal transitions from low to high. Unlike a bandgap generator, which may be unreliable at low supply voltages, the bias current generation circuit 2048 is capable of providing a fully adjustable, ready bias current.

[0076] Figure 5 This is a circuit diagram of a non-limiting example 200D of an electronic circuit 100 shown in some examples.

[0077] Except for the following differences, electronic circuit 200D is the same as electronic circuit 200C. For example... Figure 5As shown, the electronic circuit 200D also includes one or more of the thirteenth to sixteenth transistors M17-M20, such as PMOS transistors. For example, transistor M17 has a source coupled to the drain of transistor M15 and a drain coupled to the drain of transistor M22. In some examples, the gate of transistor M17 is coupled to its drain, and is therefore diode-connected and self-biased. Transistor M17 is operable to protect transistor M15 from breakdown. In some examples, transistor M18 has a source coupled to the drain of transistor M12, a drain coupled to the drain of transistor M2, and a gate coupled to the gate of transistor M17. Transistor M18 is operable to protect transistor M12 from breakdown. In some examples, transistor M19 has a source coupled to the drain of transistor M14, a drain coupled to the drain of transistor M3, and a gate coupled to the gate of transistor M17. Transistor M19 is operable to protect transistor M14 from breakdown. In some examples, transistor M20 has a source coupled to the drain of transistor M16, a drain coupled to terminal L, and a gate coupled to the gate of transistor M17. Transistor M20 is operable to protect transistor M16 from breakdown.

[0078] Figure 6 This is a circuit diagram of a non-limiting example 200E of an electronic circuit 100 shown in some examples.

[0079] Except for the following differences, electronic circuit 200E is the same as electronic circuit 200D. For example... Figure 6 As shown, electronic circuit 200E also includes an additional supply voltage generation circuit 208. For example, the additional supply voltage generation circuit 208 includes an eighteenth transistor M23 and a tenth resistor R11. In some examples, transistor M23, such as an NMOS transistor, includes a gate coupled to the gate of transistor M8, a source coupled to ground GND via resistor R11, and a drain coupled to power supply VDD. In some examples, transistor M23 includes an LVT transistor with a threshold voltage V close to 0 V. th_M23 When transistor M23 is turned on, its gate-source voltage V GS_M23 It is also close to 0 V, which means that the voltage at terminal E, which is coupled to the source of transistor M23, is approximately equal to the voltage V at the gate of transistor M23. H Additionally, in some examples, the additional supply voltage generation circuit 208 includes a filter circuit 2082 to eliminate noise. Figure 6In the example shown, the filter circuit 2082 includes a resistor R13 and a capacitor C2. Resistor R13 is coupled between the gates of transistor M23 and M8, and one terminal of capacitor C2 is coupled between the gate of transistor M23 and resistor R13, while the other terminal is coupled to ground GND. An additional supply voltage generation circuit 208 can be configured to provide a clean, unregulated supply voltage V at terminal E outside the loop. snr .

[0080] although Figures 2 to 6 The diagram shows transistors M9, M21, and M22 with their gates coupled to G or K, but this description is not limited thereto. Each of the gates of transistors M9, M21, and M22 may be coupled to any of the first and second terminals of the bandgap reference circuit 202, one or more tap points (e.g., F, G, and K), and the output terminal (e.g., H) of the regulation circuit 204. Furthermore, one or both of the gates of transistors M21 and M22 may alternatively be coupled to a supply voltage external to the electronic circuits 200A-200E. However, when they are coupled to supply voltages (e.g., F, G, K, and H) within the electronic circuits 200A-200E, the circuitry is simplified and reduced in size.

[0081] In such Figure 6 The single circuit shown can generate a self-referenced, fully adjustable, and accurate (±100 μV) POR signal, a clean, regulated / unregulated, adjustable, and accurate (±100 mV) supply voltage, and a regulated and accurate (±5%) bias current. For these reasons, the power supply timing control scheme can be simplified. Tighter POR transition accuracy reduces the design complexity of downstream modules because it provides greater margin for buffers and low-dropout regulators (LDOs), resulting in greater area savings in the system (e.g., on-chip). It also eliminates the need for dedicated bandgap and bias current generators, further reducing the downstream IP area (>200 K μm). 2 The additional PSRR benefit from the generation of the regulated supply voltage helps sensitive IPs operate on a clean supply voltage, thereby improving the system's noise margin. Because the supply voltage and bias current that can be supplied to downstream modules are regulated, this circuit improves the PSRR of downstream modules (>40dB benefit) and line transient specifications. This circuit makes the system more immune to power supply noise and improves the overall system regulation accuracy.

[0082] The terms “left,” “right,” “front,” “back,” “top,” “bottom,” “upper,” “lower,” “higher,” “lower,” etc., used in the specification and claims, if applicable, are for descriptive purposes and not necessarily for describing permanent relative positions. The terms used are interchangeable where appropriate, such that the examples described herein can operate, for example, in orientations different from those shown or otherwise described herein. For example, when the device in the figures is upside down, a feature initially described as “above” other features can now be described as “below” other features. The device may also be oriented in other ways (rotated 90 degrees or other orientations), and in this case, the relative spatial relationships will be interpreted accordingly.

[0083] In the specification and claims, when an element is described as being "on" another element, "attached" to another element, "connected" to another element, "coupled" to another element, or "in contact" with another element, the element may be directly on, directly attached to, directly connected to, directly coupled to, or directly in contact with the other element, or one or more intermediate elements may be present. In contrast, when an element is described as being "directly on" another element, "directly attached" to, directly connected to, directly coupled to, or "in contact" with another element, no intermediate elements are present. In the specification and claims, a feature is arranged "adjacent" to another feature, which may mean that the feature has a portion overlapping with the adjacent feature or a portion located above or below the adjacent feature.

[0084] As used herein, the terms “exemplary,” “illustrative,” etc., mean “used as an example, instance, or illustration,” and not as a “model” to be precisely replicated. Any implementation described herein by example is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, this description is not limited to any express or implied theory presented in the technical field, background art, utility model content, or specific embodiments. As used herein, the term “substantially” means to include all minor variations caused by design or manufacturing defects, device or component tolerances, environmental influences, and / or other factors. The term “substantially” also allows for differences from perfect or ideal situations caused by parasitic effects, noise, and other practical considerations that may exist in actual implementations.

[0085] Additionally, terms such as “first,” “second,” etc., may also be used herein for illustrative purposes and are not intended to be limiting. For example, unless the context clearly indicates otherwise, the terms “first,” “second,” and other such numerical terms relating to structures or elements do not imply order or sequence. “Comprising / including,” when used herein, specifies the presence of the stated feature, integral, step, operation, unit, and / or component, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, units, components, and / or combinations thereof. In this description, the term “providing” is used broadly to cover all ways of obtaining an object; therefore, “providing an object” includes, but is not limited to, “purchasing,” “preparing / manufacturing,” “arranging / setting up,” “installing / assembling,” and / or “ordering” objects.

[0086] As used herein, the term “and / or” includes any and all combinations of one or more of the listed items in association. The terminology used herein is for the purpose of describing specific examples only and is not intended to limit the description. As used herein, the singular forms “a,” “an,” and “the” also include the plural forms unless the context clearly indicates otherwise.

[0087] The boundaries between the operations described above are merely illustrative. Multiple operations can be combined into a single operation, a single operation can be distributed among additional operations, and the execution of operations can at least partially overlap in time. Furthermore, alternative examples may include multiple instances of a particular operation, and the order of operations may be changed in various other examples. However, other modifications, variations, and substitutions are also possible. Aspects and elements of all the above examples can be combined in any way and / or combined with aspects or elements of other examples to provide multiple additional examples. Therefore, this specification and the accompanying drawings are illustrative and not restrictive.

[0088] Additionally, when used herein, words such as “here,” “above,” “below,” “this text,” “below,” “above,” and similar terms should refer to the entire description, not any particular part of it. Furthermore, unless explicitly stated otherwise, the conditional language used herein (such as “can,” “may,” “for example,” “like,” etc.) is generally used to indicate that some examples include certain features, elements, and / or states, while others do not. Therefore, such conditional language generally does not imply that one or more examples require features, elements, and / or states in any way, or whether such features, elements, and / or states are included or performed in any particular example.

[0089] Although specific embodiments have been described in detail by way of examples, the above embodiments are for illustrative purposes only and are not intended to limit the scope of this application. The embodiments described herein can be combined in any way without departing from the spirit and scope of this application. Those skilled in the art will also recognize that various modifications can be made to the embodiments without departing from the scope and spirit of this application. The scope of this application is defined by the appended claims.

Claims

1. An electronic circuit, characterized by The electronic circuit includes: A first transistor, the first transistor having a first terminal, a second terminal and a control terminal; A first resistor, the first resistor having a first terminal coupled to the control terminal of the first transistor and a second terminal coupled to the power supply terminal; A bandgap reference circuit having a first terminal coupled to a first terminal of the first transistor, and the bandgap reference circuit being configurable to generate a bandgap voltage; An adjustment circuit having an input terminal coupled to the bandgap reference circuit, a first output terminal coupled to a control terminal of the first transistor and a first terminal of the first resistor, and a second output terminal, and the adjustment circuit being configurable to adjust the bandgap voltage via the first transistor; and An output stage coupled to a second output terminal of the bandgap reference circuit and the regulation circuit, and the output stage being configurable to generate a power-on reset signal based on the difference between a first current determined by the first resistor and a second current based on the bandgap voltage.

2. An electronic circuit according to claim 1, characterized in that The second terminal of the first transistor is coupled to the power supply terminal, and the bandgap reference circuit includes: A first branch, coupled between a first terminal and a ground terminal of the bandgap reference circuit, and comprising a second transistor; and A second branch, coupled between the first terminal and the ground terminal of the bandgap reference circuit, and including a third transistor and a second resistor, the second resistor being located between the first terminal and the third transistor of the bandgap reference circuit. The bandgap reference circuit has a second terminal coupled to the control terminals of the second transistor and the third transistor, and the bandgap voltage is provided between the second terminal of the bandgap reference circuit and the first terminal of the bandgap reference circuit.

3. An electronic circuit according to claim 2, characterised in that, The second transistor and the third transistor each include a bipolar transistor, and the second resistor can be configured such that the voltage drop across the second resistor corresponds to the difference between the base-emitter voltage of the second transistor and the base-emitter voltage of the third transistor.

4. The electronic circuit according to claim 2, characterized in that, The bandgap reference circuit further includes: A third resistor is coupled between the second terminal of the bandgap reference circuit and the ground terminal; A fourth resistor, coupled in a first branch of the bandgap reference circuit between the second transistor and a first terminal of the bandgap reference circuit; and A fifth resistor is coupled in the second branch of the bandgap reference circuit between the second resistor and the first terminal of the bandgap reference circuit.

5. The electronic circuit according to claim 2, characterized in that, The bandgap reference circuit further includes: A resistive voltage divider circuit is coupled between a first terminal of the bandgap reference circuit and a second terminal of the bandgap reference circuit, wherein the resistive voltage divider circuit can be configured to form one or more tap points.

6. The electronic circuit according to claim 5, characterized in that, For each of the one or more tap points, the bandgap reference circuit further includes: The corresponding filter circuit is coupled to the tap point.

7. The electronic circuit according to claim 2, characterized in that, The output stage includes a fourth transistor and a sixth resistor. The fourth transistor has a control terminal coupled to any one of a first terminal of the bandgap reference circuit, a second terminal of the bandgap reference circuit, or a first output terminal of the adjustment circuit. The fourth transistor also has a first terminal coupled to ground via the sixth resistor. The second current is further determined by the sixth resistor.

8. The electronic circuit according to claim 7, characterized in that, At least one of the resistance values ​​of the first resistor and the sixth resistor is adjustable.

9. The electronic circuit according to claim 2, characterized in that, The output stage includes: A mirror branch of a first current mirror circuit, the first current mirror circuit being configured to mirror the first current and including a fifth transistor in its mirror branch. A second current mirror circuit, the second current mirror circuit being configurable to mirror the second current and including a sixth transistor in its mirror branch; and A seventh transistor and a seventh resistor, the seventh transistor including a control terminal coupled to a third terminal, a first terminal coupled to the power supply terminal, and a second terminal coupled to the ground terminal via the seventh resistor, the third terminal being between the fifth transistor and the sixth transistor. The output stage can be configured to generate the power-on reset signal based on the voltage at the fourth terminal, which is located between the second terminal of the seventh transistor and the seventh resistor.

10. The electronic circuit according to claim 9, characterized in that, The mirror branch of the second current mirror circuit also includes an eighth transistor between the sixth transistor and the third terminal.

11. The electronic circuit according to claim 2, characterized in that, The adjustment circuit includes a first input terminal and a second input terminal. The first input terminal is coupled between the second transistor and the first terminal of the bandgap reference circuit, and the second input terminal is coupled between the second resistor and the first terminal of the bandgap reference circuit.

12. The electronic circuit according to claim 11, characterized in that, The regulating circuit further includes a ninth transistor having a first terminal coupled to the ground terminal and a second terminal coupled to the power supply terminal via the first resistor. The ninth transistor can be configured to turn off when the voltage at the first input terminal of the regulating circuit is greater than the voltage at the second input terminal of the regulating circuit, or to turn on when the voltage at the first input terminal of the regulating circuit is less than the voltage at the second input terminal of the regulating circuit.

13. The electronic circuit according to claim 12, characterized in that, The regulating circuit also includes: A differential input stage, the differential input stage including a first branch and a second branch, each branch of the differential input stage including one or more transistors, each of the one or more transistors having a control terminal coupled to a corresponding one of the first input terminal and the second input terminal of the adjustment circuit; A third current mirror circuit, configured to mirror a third current output from the first branch of the differential input stage to the control terminal of the ninth transistor; and A fourth current mirror circuit, which can be configured to mirror a fourth current output from the second branch of the differential input stage to the control terminal of the ninth transistor.

14. The electronic circuit according to claim 13, characterized in that, The electronic circuit further includes a bias current generating circuit, which comprises: A fifth current mirror circuit, comprising a reference branch having a tenth transistor and a mirror branch having an eleventh transistor, wherein the first terminals of the tenth and eleventh transistors are both coupled to the power supply terminal; and The twelfth transistor includes a first terminal coupled to the ground terminal via the eighth resistor, a second terminal coupled to the second terminal of the tenth transistor, and a control terminal coupled to any one of the first terminal of the bandgap reference circuit, the second terminal of the bandgap reference circuit, or the first output terminal of the adjustment circuit. The bias current generation circuit can be configured to generate a bias current at a fifth terminal, which is coupled to the second terminal of the eleventh transistor.

15. The electronic circuit according to claim 14, characterized in that, The resistance value of the eighth resistor is adjustable.

16. The electronic circuit according to claim 14, characterized in that, The reference branch of the fifth current mirror circuit also includes a diode-connected thirteenth transistor, which is located between the tenth and twelfth transistors.

17. The electronic circuit according to claim 16, characterized in that, The electronic circuit also includes at least one of the following: The fourteenth transistor in the mirror branch of the third current mirror circuit, the control terminal of the fourteenth transistor being coupled to the control terminal of the thirteenth transistor; or The fifteenth transistor in the mirror branch of the fourth current mirror circuit, the control terminal of the fifteenth transistor is coupled to the control terminal of the thirteenth transistor; or The sixteenth transistor in the mirror branch of the fifth current mirror circuit, the control terminal of the sixteenth transistor is coupled to the control terminal of the thirteenth transistor.

18. The electronic circuit according to claim 13, characterized in that, The regulating circuit also includes: The seventeenth transistor and the ninth resistor, the differential input stage being coupled to the ground terminal via the seventeenth transistor and the ninth resistor, The seventeenth transistor includes a first terminal coupled to the ground terminal via the ninth resistor, a second terminal coupled to the differential input stage, and a control terminal coupled to any one of the first terminal of the bandgap reference circuit, the second terminal of the bandgap reference circuit, or the first output terminal of the adjustment circuit.

19. The electronic circuit according to claim 1, characterized in that, The electronic circuit further includes an additional supply voltage generation circuit, which includes: The eighteenth transistor includes a control terminal coupled to the control terminal of the first transistor, a first terminal coupled to a ground terminal via the tenth resistor, and a second terminal coupled to the power supply terminal. The additional supply voltage generation circuit can be configured to generate an additional supply voltage based on the voltage at a sixth terminal, which is located between the first terminal of the eighteenth transistor and the tenth resistor.

20. The electronic circuit according to claim 19, characterized in that, The additional supply voltage generation circuit also includes a filter circuit between the control terminal of the eighteenth transistor and the control terminal of the first transistor.

21. The electronic circuit according to claim 1, characterized in that, The first transistor includes a metal-oxide-semiconductor transistor.

22. The electronic circuit according to claim 7, characterized in that, The first transistor and the fourth transistor each include a low-voltage threshold transistor.

23. An electronic system, characterized in that, The electronic system includes: The electronic circuit according to any one of claims 1 to 22; and The circuitry coupled to the output stage is configured to operate based on the power-on reset signal.

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