A multi-protocol compatible data communication and acquisition device

Abstract

This utility model relates to a multi-protocol compatible data communication and acquisition device, including a main control unit, at least one pluggable interface unit, and a non-volatile memory. Each interface unit is equipped with an in-situ detector and an onboard identification information memory. The in-situ detector is electrically connected to the main control unit via a freeze control line and a recovery confirmation line, and the onboard identification information memory is electrically connected to the main control unit. The non-volatile memory is an FRAM or NVRAM, connected in parallel with a supercapacitor to complete continuous recording during insertion / removal or power failure. The main control unit is electrically connected to the non-volatile memory and establishes corresponding data channels with each interface unit. When an interface unit is inserted / removed or disconnected, the in-situ detector triggers the main control unit to freeze the corresponding data channel via the freeze control line. During the freeze period, the main control unit writes continuous records (including segment numbers and water level lines) into the non-volatile memory and confirms them via the recovery confirmation line after unfreezing.

Description

Technical Field

[0001] This utility model relates to the field of industrial data communication and IoT edge acquisition technology, and in particular to a multi-protocol compatible data communication and acquisition device. Background Technology

[0002] In industrial settings, such as automated control of production lines, parameter monitoring in petrochemical plants, energy consumption metering in power plants, and operational assurance for rail transit, a variety of heterogeneous devices are typically deployed, including PLCs (Programmable Logic Controllers), DCS (Distributed Control Systems), smart meters, power metering devices, serial terminals, and industrial cameras. These devices perform functions such as operation control, process monitoring, energy consumption statistics, and safety detection, but their interfaces and communication protocols vary widely, including Ethernet, RS-485 / 232, CAN bus, and their upper-layer protocols. To achieve unified data access and aggregation from different devices, multi-interface acquisition devices are generally used in engineering practice, requiring them to be pluggable, replaceable, and expandable during operation to meet long-term maintenance and expansion needs.

[0003] In existing technologies, multi-interface acquisition devices mainly fall into two categories: one is the architecture of "multiple gateways in parallel + switch + server". This solution has a single function on the device side, and data recovery relies on server logs and database processing. It lacks fine control over channel boundaries and alignment, which can easily lead to data loss or misalignment when the interface is abnormal. The other is rack-mounted or stand-alone modular devices. Although module identification and alarms are achieved through interface boards and in-situ detection circuits, the handling of data channels during interface unit plugging / unplugging or power failure mainly relies on software logic. It does not form a closed loop of hardware detection, channel handling and recovery, and there is still a risk of data interruption, duplication or recovery misalignment.

[0004] Therefore, a multi-protocol compatible data communication and acquisition device is needed to ensure the continuity of the data channel at the device structure and electrical connection level, and to complete a correct and verifiable reconnection after recovery, thereby overcoming the problems of data interruption and unstable recovery in the existing technology. Utility Model Content

[0005] This invention aims to solve at least one of the technical problems existing in the prior art. To this end, one objective of this invention is to provide a multi-protocol compatible data communication and acquisition device, including a main control unit, at least one pluggable interface unit, and a non-volatile memory; wherein: each interface unit is equipped with an in-situ detector and an onboard identification information memory; the in-situ detector is electrically connected to the main control unit via a control connection, and the onboard identification information memory is electrically connected to the main control unit via an identification connection; the control connection includes a freeze control line and a restore confirmation line; the non-volatile memory is an FRAM or NVRAM connected in parallel with a supercapacitor to complete continuous recording during plugging / unplugging or power failure; the main control unit and the non-volatile memory... The volatile memory is electrically connected to and establishes a corresponding data channel with each of the interface units. When any of the interface units is plugged in, removed, or disconnected, the in-situ detector triggers the main control unit to freeze the data channel corresponding to the interface unit via the freeze control line. During the freeze, the main control unit writes the continuous record corresponding to the interface unit into the non-volatile memory. The continuous record includes at least a segment number and a water level. After the freeze is lifted, the main control unit confirms the data via the recovery confirmation line and establishes a mapping between the channel and the continuous record based on the channel identifier of the onboard identification information memory, and aligns it according to the segment number to perform data replenishment and recovery.

[0006] In one possible implementation, the freeze control line and the recovery confirmation line are independent physical signal lines and use an edge-triggered method to indicate the timing of freezing and unfreezing. The main control unit unfreezes the non-volatile memory only through the recovery confirmation line after confirming that the non-volatile memory has been written.

[0007] In one possible implementation, the device includes a synchronization signal line and at least one of the interface units is an Ethernet interface unit. The synchronization signal line distributes 1PPS and / or IEEE1588 signals in hardware to the timing / hardware timestamp unit of the main control unit and the physical layer chip timestamp pin of the Ethernet interface unit, respectively.

[0008] In one possible implementation, the phase jitter of the synchronization signal line is no greater than 100 ps.

[0009] In one possible implementation, the FRAM or NVRAM has a capacity of 1 to 16 MB and the supercapacitor connected in parallel has a capacity of 0.1 to 5 F to ensure that the segment number and water level record are written during power failure.

[0010] In one possible implementation, the non-volatile memory is electrically connected to the main control unit via a parallel bus or an SPI bus of at least 50MHz.

[0011] In one possible implementation, the in-situ detector employs a structure of long and short needles combined with a spring or micro switch and is equipped with a hardware anti-shake circuit of 5 to 20 ms.

[0012] In one possible implementation, the onboard identification information storage includes at least the following fields: channel identifier, board model, serial number, firmware version, and the last submitted waterline snapshot number.

[0013] In one possible implementation, the identification connection is an I²C bus and a unique address is assigned to each of the interface units so that the channel identifier and the I²C address form a one-to-one mapping, and the master control unit establishes a mapping table containing a verification field for verifying the alignment of the continuous records during the recovery phase.

[0014] Additional aspects and advantages of this invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.

[0015] Based on the above technical solution, this utility model provides a multi-protocol compatible data communication and acquisition device. By integrating a main control unit, a pluggable interface unit, and a non-volatile memory into the device, and incorporating a bit detector and onboard identification information memory within the interface unit, it achieves reliable freezing of the data channel and writing of continuous records when the interface unit is plugged in, unplugged, or disconnected, and performs data recovery and restoration after restoration. Specifically, when any interface unit is plugged in, unplugged, or disconnected, the bit detector immediately triggers the main control unit to freeze the corresponding data channel via the freeze control line, thereby preventing data loss or damage. During the freeze period, the main control unit writes the continuous record (including at least the segment number and water level line) corresponding to the interface unit into the non-volatile memory, ensuring persistent data storage and retaining critical information even in the event of power failure or unexpected situations. The non-volatile memory uses FRAM or NVRAM and is connected in parallel with a supercapacitor, which further enhances the reliability of data writing, especially during momentary plugging / unplugging or power failure, where the supercapacitor provides sufficient energy to complete the writing of continuous records. When the interface unit is reconnected or the system is unfrozen, the main control unit confirms the writing is complete via the recovery confirmation line and establishes a mapping relationship between the channel and the continuous record based on the channel identifier stored in the onboard identification information memory. Subsequently, the main control unit aligns the data according to the segment number of the record and accurately performs data replenishment and recovery operations, thereby ensuring the continuity and integrity of data communication. The above mechanism effectively solves the problem of data consistency in traditional multi-protocol communication equipment when the interface is plugged in or out or fails, significantly improving the system's reliability and data processing robustness, and has the effects of high data transmission reliability, strong system recovery capability, and convenient maintenance. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this utility model. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0017] Figure 1 A schematic diagram of the structural connection of the multi-protocol compatible data communication and acquisition device provided by this utility model;

[0018] Figure 2 Block diagram for controlling the data channel freeze and recovery triggered by the connection;

[0019] Figure 3 Flowchart for I²C identification mapping and continuous record alignment.

[0020] Explanation of reference numerals in the attached figures:

[0021] 11. Main control unit; 12. Pluggable interface unit; 13. Non-volatile memory; 14. Synchronization signal line; 111. Control connection; 112. Identification connection; 121. In-situ detector; 122. Onboard identification information memory; 131. Supercapacitor; FO, Freeze control line; ACK, Recovery confirmation line. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.

[0023] In the description of this utility model, it should be understood that the terms "center," "longitudinal," "transverse," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential," etc., indicating the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model. Furthermore, features defined with "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this utility model, unless otherwise stated, "a plurality of" means two or more.

[0024] In the description of this utility model, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.

[0025] The embodiments of this utility model are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this utility model, and should not be construed as limiting this utility model.

[0026] Figure 1 A schematic diagram of the structural connection of the multi-protocol compatible data communication and acquisition device provided by this utility model; Figure 2 Block diagram for controlling the data channel freeze and recovery triggered by the connection; Figure 3 Flowchart for I²C identification mapping and continuous record alignment.

[0027] Please see Figure 1-3In one possible implementation, a multi-protocol compatible data communication and acquisition device includes a main control unit 11, at least one pluggable interface unit 12, and a non-volatile memory 13. Each interface unit 12 is equipped with an in-situ detector 121 and an onboard identification information memory 122. The in-situ detector 121 is electrically connected to the main control unit 11 via a control connection 111, and the onboard identification information memory 122 is electrically connected to the main control unit 11 via an identification connection 112. The control connection 111 includes a freeze control line FO and a recovery confirmation line ACK. The non-volatile memory 13 is an FRAM or NVRAM connected in parallel with a supercapacitor 131 to complete continuous recording during plugging / unplugging or power failure. The main control unit 11 is electrically connected to the non-volatile memory 13 and establishes corresponding data channels with each interface unit 12. When any interface unit 12 is plugged in, unplugged, or disconnected, the presence detector 121 triggers the main control unit 11 to freeze the data channel corresponding to the interface unit 12 via the freeze control line FO. During the freeze period, the main control unit 11 writes the continuous record corresponding to the interface unit 12 into the non-volatile memory 13. The continuous record includes at least the segment number and water level line. After the freeze is lifted, the main control unit 11 confirms via the recovery confirmation line ACK and establishes a mapping between the channel and the continuous record based on the channel identifier of the onboard identification information memory 122 and aligns it according to the segment number to perform data replenishment and recovery.

[0028] Specifically, when the interface unit 12 is plugged in, unplugged, or disconnected, the presence detector 121 quickly triggers the main control unit 11 to freeze the corresponding data channel via the freeze control line FO, thereby preventing data loss or misalignment. During the freeze, critical continuity records (including segment numbers and water level lines) are reliably written to the non-volatile memory 13, which is powered by the supercapacitor 131 to ensure data writing can be completed even in the event of an unexpected power outage. During recovery, the main control unit 11 confirms via the recovery confirmation line ACK and establishes a mapping using the channel identifier in the onboard identification information memory 122. Based on the segment number alignment, accurate data replenishment and recovery are achieved, forming a closed loop of hardware detection, channel handling, and recovery, ensuring data integrity.

[0029] This invention includes a main control unit 11, at least one pluggable interface unit 12, and a non-volatile memory 13. The main control unit 11 is the core of the device, responsible for data processing, channel management, and communication with various components. The pluggable interface units 12 are used to connect to external devices using different protocols. Each interface unit 12 integrates an in-situ detector 121 and an onboard identification information memory 122. The in-situ detector 121 monitors the physical connection status of the interface unit 12 in real time. When an interface unit 12 is plugged in, unplugged, or disconnected, the in-situ detector 121 sends a signal to the main control unit 11 via the freeze control line FO in the control connection 111. The onboard identification information memory 122 stores the unique identification information of the interface unit 12 and is electrically connected to the main control unit 11 via the identification connection 112. It is used to identify and map data channels during the recovery process. The control connection 111 also includes a recovery confirmation line ACK, through which the main control unit 11 unfreezes the state. The non-volatile memory 13 uses either FRAM or NVRAM to ensure data retention after power failure. A supercapacitor 131 is connected in parallel to provide short-term power for writing critical data. The main control unit 11 is electrically connected to the non-volatile memory 13 and establishes an independent data channel for each interface unit 12. When an interface unit 12 is plugged in, removed, or disconnected, the presence detector 121 immediately triggers the main control unit 11 to freeze the corresponding data channel. During the freeze, the main control unit 11 writes the continuity record (such as segment number and watermark) of the interface unit 12 into the non-volatile memory 13. Upon recovery, the main control unit 11 confirms via the recovery acknowledgment line (ACK) and establishes a mapping between the channel and the continuity record based on the channel identifier in the onboard identification information memory 122, aligning by segment number, and performing data replenishment and recovery to ensure data continuity and accuracy.

[0030] This invention, by introducing a hardware-level in-situ detector 121 and a freeze control line FO, can quickly respond to insertion / removal or disconnection events of the interface unit 12, shortening the data channel freeze time to the millisecond level and significantly reducing the risk of data interruption. The parallel connection of the non-volatile memory 13 and the supercapacitor 131 ensures that critical continuous records (segment numbers and water level lines) can be reliably written in the event of a sudden power failure, avoiding data loss and improving data integrity and reliability. Through the channel identification and segment number alignment mechanism of the onboard identification information memory 122, the main control unit 11 can accurately perform data replenishment and recovery after unfreezing, avoiding data misalignment or duplication and ensuring the continuity and accuracy of the data stream. The above structure solves the problems of data interruption and unstable recovery in the prior art, improving the operational reliability of the equipment and the continuity of data acquisition in complex industrial environments.

[0031] Please see Figure 2In one possible implementation, the freeze control line FO and the recovery confirmation line ACK are independent physical signal lines and use an edge-triggered method to indicate the timing of freezing and unfreezing. The main control unit 11 unfreezes the non-volatile memory 13 only after confirming that the writing has been completed.

[0032] Specifically, the freeze control line FO and the recovery confirmation line ACK are two independent physical signal lines, responsible for triggering the freeze operation and confirming the unfreeze operation, respectively. The freeze control line FO uses an edge-triggered method. For example, when the interface unit 12 is plugged in, removed, or disconnected, the presence detector 121 generates a rising or falling edge signal, which directly triggers the main control unit 11 to enter the data channel freeze state via the freeze control line FO. This edge-triggered mechanism ensures instantaneous signal response and high anti-interference capability, avoiding the signal jitter problem that may exist in traditional level triggering. After receiving the freeze signal, the main control unit 11 immediately stops writing real-time data to the corresponding data channel and starts the process of writing continuous records to the non-volatile memory 13. Only when the main control unit 11 confirms that the non-volatile memory 13 has successfully completed the writing operation of all continuous records (e.g., through the busy / idle signal of the memory 13 or the write completion interrupt), will it send an unfreeze signal through the recovery confirmation line ACK. The recovery confirmation line ACK also uses an edge-triggered method, indicating that the data channel can safely resume normal operation.

[0033] This invention significantly improves the response speed and accuracy of freeze and unfreeze operations by employing independent physical signal lines (freeze control line FO and recovery confirmation line ACK) and an edge-triggered method, avoiding false triggering caused by signal jitter or transient changes. The mechanism by which the main control unit 11 only unfreezes after confirming that the non-volatile memory 13 has completed writing fundamentally ensures the integrity and reliability of continuous recording, effectively preventing data loss or misalignment. These timing control and hardware confirmation mechanisms make the continuity of the data channel more reliable, improve the data processing stability of the device under complex operating conditions, and solve the pain points of data interruption and unstable recovery in existing technologies.

[0034] Please see Figure 1 In one possible implementation, the device includes a synchronization signal line 14 and at least one interface unit 12 is an Ethernet interface unit. The synchronization signal line 14 distributes 1PPS and / or IEEE1588 signals in hardware to the timing / hardware timestamp unit of the main control unit 11 and the physical layer chip timestamp pin of the Ethernet interface unit 12, respectively.

[0035] The data communication and acquisition device of this invention includes a synchronization signal line 14, which is specifically used for transmitting high-precision time synchronization signals. At least one pluggable interface unit 12 is configured as an Ethernet interface unit to meet the needs of high-speed data communication. The synchronization signal line 14 is responsible for distributing two commonly used and high-precision time synchronization signals—1PPS (pulses per second) signal and / or IEEE 1588 (Precision Time Protocol) signal—in a purely hardware manner. Specifically, the 1PPS signal is a pulse signal with a period of 1 second, whose rising or falling edge precisely indicates the start of each second, and has extremely high time accuracy. The IEEE 1588 signal is a more complex protocol that can achieve nanosecond-level time synchronization through network transmission. The synchronization signal line 14 directly connects these high-precision signals to the timing / hardware timestamp unit inside the main control unit 11. This unit is responsible for receiving the synchronization signals and using them to generate a precise system clock or to add hardware timestamps to system events, thereby providing a unified and high-precision time reference for all data processed by the main control unit 11. Simultaneously, synchronization signal line 14 also distributes these signals to the timestamp pins of the physical layer chip (PHY) of the Ethernet interface unit 12. The Ethernet physical layer chip is the underlying hardware that processes Ethernet packets, and its timestamp pins can directly add high-precision timestamps to received or transmitted packets at the hardware level, avoiding software-level delays and jitter. The above synchronization mechanism ensures a high degree of time consistency between the main control unit 11 and the Ethernet interface unit 12, as well as within the entire device and with external synchronization sources, thereby laying the foundation for the accurate fusion and analysis of multi-source heterogeneous data.

[0036] This invention directly distributes 1PPS and / or IEEE1588 signals to the physical layer chips of the main control unit 11 and the Ethernet interface unit 12 via synchronization signal line 14, achieving high-precision time synchronization at the hardware level. This mechanism significantly improves the timestamp accuracy of data acquisition and processing, overcoming the shortcomings of traditional software synchronization methods that are susceptible to network latency and jitter. Precise time synchronization ensures that data acquired by different interface units 12 are accurately aligned on the time axis, greatly improving the accuracy and reliability of data analysis. Especially in applications with extremely high time accuracy requirements, such as industrial control and fault diagnosis, it can provide more accurate event sequence and causal relationship analysis.

[0037] It is worth noting that, in addition to transmitting 1PPS and IEEE1588 signals, synchronization signal line 14 can also support IRIG-B code (Inter-Range Instrumentation Group Time Code, Format B) or GPS timing signals to adapt to different time synchronization sources and application requirements. The timing / hardware timestamp unit of the main control unit 11 can integrate multiple synchronization signal input ports and has automatic switching or priority selection functions to automatically switch to a backup synchronization source when one fails, improving system robustness. The physical layer chip of the Ethernet interface unit 12, in addition to the timestamp pin, can also support hardware timestamp calibration to compensate for internal clock drift or delay. For interface units 12 that do not support hardware timestamps, time synchronization can be achieved through software algorithms combined with the hardware timestamp unit of the main control unit 11, for example, by periodically reading the precise timestamp of the main control unit 11 and applying it to the data of the interface unit 12. The physical medium of synchronization signal line 14 can be optical fiber to further improve the anti-interference capability and transmission distance of signal transmission, especially in industrial environments with severe electromagnetic interference. In addition, the device can be equipped with a time synchronization status monitoring function to display the quality of the synchronization signal, the status of the synchronization source, and the time deviation in real time, and provide an alarm function to promptly detect and resolve time synchronization problems.

[0038] In one possible implementation, the phase jitter of the synchronization signal line 14 is no greater than 100 ps.

[0039] In this invention, the synchronization signal line 14 is used to transmit high-precision time synchronization signals to ensure signal transmission quality. Phase jitter of the synchronization signal line 14 refers to the instantaneous phase deviation of the signal relative to the ideal clock signal during transmission. This invention strictly controls the phase jitter of the synchronization signal line 14 to no more than 100 picoseconds. Low-loss, low-dielectric-constant coaxial cables or differential transmission lines are used, and impedance matching technology is employed to reduce signal reflection. Furthermore, the signal driving and receiving circuits also require a low-jitter, high-bandwidth design to minimize additional jitter at the transmitting and receiving ends. By optimizing the physical characteristics and circuit design of the synchronization signal line 14, it is ensured that the transmitted high-precision time synchronization signal (such as 1PPS or IEEE 1588) maintains extremely high timing accuracy when it reaches the timing / hardware timestamp unit of the main control unit 11 and the physical layer chip timestamp pin of the Ethernet interface unit 12, thereby providing a stable and accurate time reference for the entire device.

[0040] This invention significantly improves the accuracy and stability of internal time synchronization by controlling the phase jitter of the synchronization signal line 14 to no more than 100 ps. The extremely low phase jitter ensures that the main control unit 11 and the Ethernet interface unit 12 can obtain highly accurate and consistent timestamps, thus providing a reliable time reference for all collected data. This is crucial for applications requiring high-precision event sequencing, fault diagnosis, and data fusion, significantly improving data accuracy and system reliability in fields such as industrial control and power monitoring.

[0041] In one possible implementation, the FRAM or NVRAM has a capacity of 1 to 16 MB and the supercapacitor 131 connected in parallel has a capacity of 0.1 to 5 F to ensure that the segment number and water level record are written during power failure.

[0042] In this invention, the non-volatile memory 13 is selected from FRAM (ferroelectric random access memory) or NVRAM (non-volatile random access memory). Both types of memory 13 feature fast write speeds, long erase / write lifespans, and data retention even in the event of power failure, making them ideal for storing data that requires frequent updates and power-loss protection. To ensure sufficient time and energy to complete the writing of critical continuous records (including segment numbers and watermarks) during device insertion / removal or unexpected power outages, this invention optimizes the capacity of the memory 13 and its backup power supply. Specifically, the capacity of the FRAM or NVRAM is set in the range of 1–16 MB. This capacity range meets the continuous recording requirements of multiple interface units 12 while considering a balance between cost and write speed. For example, a larger capacity can be selected for devices that need to record large amounts of historical data or support more interface units 12. The capacity of the supercapacitor 131 connected in parallel with the non-volatile memory 13 is set in the range of 0.1–5 F (farads). The supercapacitor 131 features high energy density and rapid charge / discharge characteristics, enabling it to provide stable power to the non-volatile memory 13 for a short period after the mains power is disconnected. A capacity of 0.1F is typically sufficient to support write operations to the memory 13 within milliseconds to tens of milliseconds, while a capacity of 5F provides a longer power supply time to handle more complex power outages or larger data write demands. By precisely matching the capacities of the memory 13 and the supercapacitor 131, continuous recording is ensured to be completely and reliably written to the non-volatile memory 13 during any insertion / removal or power outage, thereby guaranteeing data integrity and system recovery capabilities.

[0043] In one possible implementation, the non-volatile memory 13 is electrically connected to the main control unit 11 via a parallel bus or an SPI bus of not less than 50MHz.

[0044] In this invention, the electrical connection between the non-volatile memory 13 and the main control unit 11 is optimized to ensure high-speed and efficient data transmission. One connection method is to use a parallel bus. A parallel bus transmits multiple bits simultaneously through multiple data lines, achieving extremely high data transmission rates, making it ideal for scenarios requiring rapid writing of large amounts of data. For example, an 8-bit parallel bus can transmit 8 bits of data in one clock cycle, far exceeding the speed of a serial bus. Another connection method is to use an SPI (Serial Peripheral Interface) bus. The SPI bus is a synchronous serial communication interface with full-duplex, high-speed, and low-power characteristics. To meet the requirement of rapid writing of continuous records in this invention, the operating frequency of the SPI bus is set to no less than 50MHz. At a frequency of 50MHz, the SPI bus can provide sufficient data throughput to ensure that the main control unit 11 can quickly write continuous records to the non-volatile memory 13 in emergency situations such as plugging / unplugging the interface unit 12 or power failure. For example, a high-speed SPI interface can complete a write operation of hundreds of bytes in a few microseconds. Whether using a parallel bus or a high-speed SPI bus, the core objective is to provide a sufficiently fast communication speed so that the main control unit 11 can complete data interaction with the non-volatile memory 13 in a very short time. In particular, when the main power is interrupted and only the supercapacitor 131 provides power, the high-speed writing capability is especially critical, as it directly ensures the integrity and reliability of continuous recording.

[0045] This invention significantly improves data writing speed and efficiency by employing a parallel bus or an SPI bus of at least 50MHz as the electrical connection method between the master control unit 11 and the non-volatile memory 13. The high-speed interface ensures that critical segment numbers and watermark records can be quickly and completely written to the non-volatile memory 13 in emergency situations such as plugging / unplugging the interface unit 12 or power failure. This fundamentally solves the bottleneck problem of memory 13 writing speed that may exist in existing technologies, greatly enhancing the data reliability and system recovery capability of the device under sudden conditions.

[0046] In one possible implementation, the in-situ detector 121 employs a structure of long and short needles combined with a spring or micro switch and is equipped with a hardware anti-shake circuit of 5 to 20 ms.

[0047] The presence detector 121 is used to accurately monitor the physical connection status of the pluggable interface unit 12. The presence detector 121 employs one of two reliable physical structures: First, a long-short pin and spring-loaded structure. In this structure, the connector on the interface unit 12 has pins of varying lengths (long and short pins) and corresponding springs. When the interface unit 12 is inserted, the long pin contacts the spring first, establishing an initial connection, while the short pin contacts only after full insertion. When the interface unit 12 is removed, the short pin disconnects first, followed by the long pin. By monitoring the on / off state of the long and short pins, the presence status of the interface unit 12 can be determined. Second, a microswitch structure. A microswitch is a mechanical switch that can be triggered by a tiny displacement, possessing a precise trigger point and good repeatability. When the interface unit 12 is inserted or removed, its mechanical structure activates the microswitch, generating a presence signal. Whether using a long-short pin and spring-loaded structure or a microswitch, momentary jitter may occur at the instant of physical contact. To eliminate the impact of these jitter signals on the main control unit 11, a hardware anti-jitter circuit is provided at the output of the presence detector 121. This hardware anti-jitter circuit typically consists of an RC filter circuit, a Schmitt trigger, or a monostable multivibrator, and its function is to filter out glitches and transient jitter on the signal line, converting unstable level signals into stable digital signals. In this invention, the anti-jitter time of the hardware anti-jitter circuit is set within the range of 5–20 ms. This time range is long enough to cover the duration of most mechanical contact jitter, while short enough to ensure that the system's response to insertion / removal events does not incur excessive delays. For example, a 5 ms anti-jitter time can effectively filter out general mechanical jitter, while a 20 ms anti-jitter time can handle more severe jitter situations. Through this hardware anti-jitter mechanism, the presence detector 121 can output a stable and reliable presence signal, preventing the main control unit 11 from frequently triggering freeze and recovery operations due to misjudgment, thereby improving the overall stability and reliability of the system.

[0048] This invention solves the problem of signal misjudgment caused by mechanical jitter during the insertion and removal of the interface unit 12 by employing a long and short pin combined with a spring or micro switch structure in the in-place detector 121 and setting a hardware anti-jitter circuit with a duration of 5-20ms. This design ensures the accuracy and stability of the in-place detection signal, avoids the main control unit 11 from frequently triggering unnecessary freeze and recovery operations, thereby significantly improving the operational reliability and system stability of the device in interface insertion and removal scenarios and reducing the complexity of data processing.

[0049] In one possible implementation, the onboard identification information storage 122 includes at least the following fields: channel identifier, board model, serial number, firmware version, and the last submitted waterline snapshot number.

[0050] In this invention, the onboard identification information memory 122 is a key component on each pluggable interface unit 12, used to store the inherent identity and status information of that interface unit 12. This information is crucial for the main control unit 11 to accurately identify, map channels, and recover data after the interface unit 12 is plugged in, removed, or disconnected. The onboard identification information memory 122 includes at least the following five key fields:

[0051] Channel Identifier: This is a unique identifier used by the main control unit 11 to identify the logical data channel corresponding to the interface unit 12. For example, it can be an integer number or a string, ensuring that each interface unit 12 has a clear affiliation in the system.

[0052] Board Model: This field records the specific model information of interface unit 12, such as "Ethernet Interface Card V1.0" or "RS485 Interface Card V2.1". The main control unit 11 can load the corresponding driver or configuration parameters according to the board model.

[0053] Serial Number: This is a unique production serial number used to distinguish different interface units 12 of the same model. The serial number is written during the production process, is globally unique, and helps track the device's lifecycle and troubleshoot problems.

[0054] Firmware Version: This field records the version number of the firmware inside the interface unit 12. The main control unit 11 can determine whether a firmware upgrade is needed based on the firmware version, or provide a basis for compatibility checks.

[0055] Last submitted waterline snapshot number: This is a crucial field used for data recovery. The waterline represents the latest valid position of the data stream or the amount of data processed when the interface unit 12 last operated normally. The snapshot number identifies the version of this waterline record. When the interface unit 12 is re-inserted or the connection is restored, the main control unit 11 can read this "last submitted waterline snapshot number" and, in conjunction with the continuity record stored in the non-volatile memory 13, accurately determine the starting point for data recovery, thereby achieving seamless continuation of the data stream. For example, if the waterline snapshot number is 12345, the main control unit 11 will start recovering data from the data after this number. By integrating this key information into the onboard identification information memory 122, the main control unit 11 can quickly and accurately obtain the identity and status of the interface unit 12, thereby achieving efficient and reliable data channel management and recovery.

[0056] This invention significantly enhances the identification and status tracking capabilities of the interface unit 12 by including key fields such as channel identifier, board model, serial number, firmware version, and the last submitted water level snapshot number in the onboard identification information storage 122. This ensures that the main control unit 11 can accurately and quickly map, align, and replenish data channels after the interface unit 12 is plugged in, unplugged, or disconnected, thereby significantly improving the accuracy and efficiency of data recovery. Simultaneously, this standardized information also enhances the overall manageability and maintainability of the device.

[0057] Please see Figure 3 In one possible implementation, the connection 112 is identified as an I²C bus and a unique address is assigned to each interface unit 12 so that the channel identifier and the I²C address are mapped one-to-one. The main control unit 11 establishes a mapping table containing a check field for checking the alignment of continuous records during the recovery phase.

[0058] In this invention, the identification connection 112 is a crucial communication link between the main control unit 11 and each pluggable interface unit 12 for identification and configuration. The identification connection 112 can utilize an I²C (Inter-Integrated Circuit) bus. The I²C bus is a serial communication bus with advantages such as simple wiring (typically requiring only SDA data lines and SCL clock lines), support for multi-master / multi-slave modes, and address addressing, making it ideal for connecting multiple peripheral devices. Under the I²C bus architecture, this invention assigns a unique I²C address to each interface unit 12. This unique I²C address forms a one-to-one mapping with the channel identifier of each interface unit 12 (stored in the onboard identification information memory 122). The main control unit 11 can quickly discover and identify online interface units 12 by scanning the addresses on the I²C bus, and directly obtain the corresponding channel identifier based on their I²C address, thereby establishing a clear association between the physical interface and the logical data channel. The main control unit 11 internally maintains a mapping table containing a check field. This mapping table not only stores the one-to-one mapping between channel identifiers and I²C addresses, but also includes a check field. The check field can be a Cyclic Redundancy Check (CRC) code, checksum, or hash value, used to verify the correctness of the mapping and the integrity of the data. During the recovery phase after device startup or reinsertion of interface unit 12, the main control unit 11 uses this mapping table, combined with the check field, to perform alignment checks on the continuous records stored in non-volatile memory 13. For example, the main control unit 11 can read the channel identifier of interface unit 12 and its corresponding I²C address, then calculate a check value and compare it with the check field in the mapping table. If the check fails, it indicates that the mapping may be incorrect or the data may be corrupted, and the main control unit 11 can trigger an alarm or attempt to re-establish the mapping. This mechanism ensures that during data recovery, continuous records can be accurately aligned to the correct channel, avoiding data misalignment or confusion, thereby greatly improving the accuracy and reliability of data recovery.

[0059] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0060] Although embodiments of the present invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the present invention, the scope of which is defined by the claims and their equivalents.

[0061] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0062] Although embodiments of the present invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the present invention, the scope of which is defined by the claims and their equivalents.

Claims

1. A multi-protocol compatible data communication and acquisition device, comprising a main control unit, at least one pluggable interface unit, and a non-volatile memory; wherein: Each interface unit is equipped with an in-situ detector and an onboard identification information memory. The in-situ detector is electrically connected to the main control unit via a control connection, and the onboard identification information memory is electrically connected to the main control unit via an identification connection. The control connection includes a freeze control line (FO) and a recovery confirmation line (ACK). The non-volatile memory is an FRAM or NVRAM connected in parallel with a supercapacitor to complete the writing of continuous records during insertion / removal or power failure. The main control unit is electrically connected to the non-volatile memory and establishes a corresponding data channel with each interface unit. When any interface unit is inserted / removed or disconnected, the in-situ detector triggers the main control unit to freeze the data channel corresponding to that interface unit via the freeze control line. During the freeze, the main control unit writes the continuous record corresponding to that interface unit into the non-volatile memory. The continuous record includes at least a segment number and a watermark. After unfreezing, the main control unit confirms via the recovery confirmation line and establishes a mapping between the channel and the continuous record based on the channel identifier of the onboard identification information memory, aligning it according to the segment number to perform data replenishment and recovery.

2. The data communication and acquisition device according to claim 1, characterized in that, The freeze control line and the recovery confirmation line are independent physical signal lines and use an edge-triggered method to indicate the timing of freezing and unfreezing. The main control unit only unfreezes the non-volatile memory through the recovery confirmation line after confirming that the non-volatile memory has been written.

3. The data communication and acquisition device according to claim 1, characterized in that, The device includes a synchronization signal line and at least one of the interface units is an Ethernet interface unit. The synchronization signal line distributes 1PPS and / or IEEE 1588 signals in hardware to the timing / hardware timestamp unit of the main control unit and the physical layer chip timestamp pin of the Ethernet interface unit, respectively.

4. The data communication and acquisition device according to claim 3, characterized in that, The phase jitter of the synchronization signal line is no greater than 100 ps.

5. The data communication and acquisition device according to claim 1, characterized in that, The FRAM or NVRAM has a capacity of 1 to 16 MB, and the supercapacitors connected in parallel have a capacity of 0.1 to 5 F to ensure that the segment number and water level record are written during power failure.

6. The data communication and acquisition device according to claim 1, characterized in that, The non-volatile memory is electrically connected to the main control unit via a parallel bus or an SPI bus of not less than 50 MHz.

7. The data communication and acquisition device according to claim 1, characterized in that, The in-situ detector adopts a structure of long and short needles combined with springs or microswitches and is equipped with a hardware anti-shake circuit of 5 to 20 ms.

8. The data communication and acquisition device according to claim 1, characterized in that, The onboard identification information storage includes at least the following fields: channel identifier, board model, serial number, firmware version, and the last submitted water level snapshot number.

9. The data communication and acquisition device according to claim 1, characterized in that, The identification connection is an I²C bus, and a unique address is assigned to each interface unit to form a one-to-one mapping between the channel identifier and the I²C address. The main control unit establishes a mapping table containing a verification field to verify the alignment of the continuous records during the recovery phase.

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