A synchronous rectified pulse width modulation signal control drive circuit

Abstract

This utility model relates to the field of pulse width modulation (PWM) technology and provides an output synchronous rectified PWM signal control and driving circuit, including an oscillation control circuit, a shaping drive circuit, an output drive circuit, and an interlock control circuit. The oscillation control circuit is electrically connected to the shaping drive circuit and is used to correct the waveform of the transformer signal. The interlock control circuit is also electrically connected to the shaping drive circuit and is used to control the cutoff and turn-on of the power MOSFETs at the positive and negative output terminals of the interlock transformer. The shaping drive circuit is electrically connected to the output drive circuit and is used to reduce the internal losses of the main power MOSFETs. The output drive circuit is also electrically connected to the shaping drive circuit and is used to improve the operating efficiency of the output synchronous rectifier circuit. This utility model reduces the internal losses of the main power MOSFETs, improves the operating efficiency of the output synchronous rectifier circuit, and enhances the overall power conversion efficiency and electrical performance of the rectifier module.

Description

Technical Field

[0001] This utility model relates to the field of pulse width modulation technology, and in particular to a control and drive circuit for outputting synchronous rectified pulse width modulation signals. Background Technology

[0002] With the rapid development of 5G mobile communication in China, the power supply quality requirements for communication equipment loads are becoming increasingly stringent, thus placing higher demands on the output power and efficiency of rectifier modules in communication power supply systems. The output rectifier circuit is the main power circuit of the rectifier module, and synchronous output rectifier circuits are increasingly widely used in rectifier module design, replacing the inefficient output diode rectifier circuit design. The circuit adopts a self-excited synchronous rectifier topology that follows the transformer output waveform. This requires the four MOSFETs at the positive and negative output terminals of the synchronous rectifier circuit to operate more safely and efficiently, necessitating the participation of more reliable and efficient gate PWM control signals. The interlocking control function effectively controls the interlocking on and off of the MOSFETs at the positive and negative output terminals of the synchronous rectifier circuit transformer, preventing mutual interference and thus ensuring more reliable operation.

[0003] Chinese patent CN107094011A discloses an intrinsically safe dynamic drive circuit that employs optocoupler isolation, dual-path dynamic pulse control, and high-frequency transformer energy conversion to achieve safe energy transmission and high conversion efficiency under 30-80Hz pulse signal control. However, this drive circuit lacks an interlocking control mechanism for synchronous rectification circuits, failing to effectively prevent bridge arm shoot-through caused by simultaneous conduction of MOSFETs at the positive and negative output terminals of the transformer. This poses a safety risk of damaging power devices and affects the reliability and safety of the synchronous rectification system. Utility Model Content

[0004] In view of this, this utility model proposes an output synchronous rectification pulse width modulation signal control and driving circuit to solve the problem that the existing technology lacks an interlock control mechanism for synchronous rectification circuits, which cannot effectively prevent the bridge arm shoot-through problem caused by the simultaneous conduction of MOSFETs at the positive and negative output terminals of the transformer, posing a safety risk of damaging power devices and affecting the reliability and safety of the synchronous rectification system.

[0005] The technical solution of this utility model is implemented as follows: an output synchronous rectified pulse width modulation signal control and driving circuit, including an oscillation control circuit, a shaping driving circuit, an output driving circuit, and an interlock control circuit, wherein:

[0006] The oscillation control circuit is electrically connected to the shaping drive circuit, and the oscillation control circuit is used to correct the waveform of the transformer signal.

[0007] The interlock control circuit is electrically connected to the shaping drive circuit, and the interlock control circuit is used to control the power MOSFETs at the positive and negative output terminals of the interlock transformer to be turned off and on.

[0008] The shaping drive circuit is electrically connected to the output drive circuit, and the shaping drive circuit is used to reduce the internal loss of the main power MOSFET.

[0009] The output driving circuit is electrically connected to the shaping driving circuit, and the output driving circuit is used to improve the working efficiency of the output synchronous rectification circuit.

[0010] Based on the above technical solutions, preferably, the oscillation control circuit includes resistors R4-R5, resistors R16-R17, diode group D5, diode group D10, Zener diode D2, Zener diode D7, transistor group Q2, and transistor group Q8.

[0011] Based on the above technical solution, preferably, one end of resistor R4 is electrically connected to the negative terminal of Zener diode D2 and pin 3 of transistor group Q2, the other end of resistor R4 is electrically connected to one end of resistor R5, the other end of resistor R5 is electrically connected to the positive terminal of Zener diode D2 and pins 2, 5, and 6 of transistor group Q2, pin 1 of transistor group Q2 is electrically connected to pin 3 of diode group D5, pin 4 of transistor group Q2 is electrically connected to pin 4 of diode group D5, pin 2 of diode group D5 is connected to the positive terminal of transformer to output signal Tout+, and pin 1 of diode group D5 is grounded;

[0012] One end of resistor R16 is electrically connected to the cathode of Zener diode D7 and pin 3 of transistor group Q8. The other end of resistor R16 is electrically connected to one end of resistor R17. The other end of resistor R17 is electrically connected to the anode of Zener diode D7 and pins 2, 5, and 6 of transistor group Q8. Pin 1 of transistor group Q8 is electrically connected to pin 3 of diode group D10. Pin 4 of transistor group Q8 is electrically connected to pin 4 of diode group D10. Pin 2 of diode group D10 is connected to the negative terminal of transformer to output signal Tout-. Pin 1 of diode group D10 is grounded.

[0013] Based on the above technical solutions, preferably, the interlock control circuit includes resistors R1-R2, resistors R13-R14, capacitor C1, capacitor C5, diode D1, diode D6, MOSFET Q1, and MOSFET Q7.

[0014] Based on the above technical solution, preferably, one end of resistor R1 is electrically connected to one end of capacitor C1 and the positive terminal of diode D1, the other end of capacitor C1 is electrically connected to the negative terminal of diode D1, the gate of MOSFET Q1, and one end of resistor R2, and the other end of resistor R2 is electrically connected to ground via the source of MOSFET Q1.

[0015] One end of resistor R13 is electrically connected to one end of capacitor C5 and the positive terminal of diode D6. The other end of capacitor C5 is electrically connected to the negative terminal of diode D6, the gate of MOSFET Q7, and one end of resistor R14. The other end of resistor R14 is electrically connected to the source of MOSFET Q7 and ground.

[0016] Based on the above technical solutions, preferably, the shaping drive circuit includes resistor R3, resistor R15, capacitors C2-C4, capacitors C6-C8, diode D4, diode D9, Zener diode D3, Zener diode D8, transistors Q3-Q4, and transistors Q9-Q10.

[0017] Based on the above technical solution, preferably, one end of resistor R3 is input to a +12V power supply, and the other end of resistor R3 is electrically connected to one end of capacitor C2, one end of capacitor C3, and the collector of transistor Q3. The other ends of capacitor C2 and capacitor C3 are both grounded. The emitter of transistor Q3 is electrically connected to the emitter of transistor Q4, the anode of diode D4, the cathode of Zener diode D3, and one end of capacitor C4. The other end of capacitor C4 is electrically connected to the anode of Zener diode D3 and the cathode of diode D4. The base of transistor Q4 is electrically connected to the base of transistor Q3, and the collector of transistor Q4 is grounded.

[0018] One end of resistor R15 is connected to a +12V power supply. The other end of resistor R15 is electrically connected to one end of capacitor C6, one end of capacitor C7, and the collector of transistor Q9. The other ends of capacitors C6 and C7 are grounded. The emitter of transistor Q9 is electrically connected to the emitter of transistor Q10, the anode of diode D9, the cathode of Zener diode D8, and one end of capacitor C8. The other end of capacitor C8 is electrically connected to the anode of Zener diode D8 and the cathode of diode D9. The base of transistor Q10 is electrically connected to the base of transistor Q9. The collector of transistor Q10 is grounded.

[0019] Based on the above technical solutions, preferably, the output driving circuit includes resistors R6-R12, resistors R18-R24, transistors Q5-Q6, and transistors Q11-Q12.

[0020] Based on the above technical solution, preferably, one end of resistor R6 is electrically connected to one end of resistor R7, the other end of resistor R6 is electrically connected to the other end of resistor R7 and the collector of transistor Q5, the base of transistor Q5 is electrically connected to the base of transistor Q6 and one end of resistor R8, the emitter of transistor Q5 is electrically connected to the emitter of transistor Q6, one end of resistor R9, and one end of resistor R11, the other end of resistor R9 is electrically connected to one end of resistor R10, the other end of resistor R11 is electrically connected to one end of resistor R12, and the other ends of resistor R10, resistor R12, the collector of transistor Q6, and resistor R8 are all grounded.

[0021] One end of resistor R19 is electrically connected to one end of resistor R20. The other end of resistor R19 is electrically connected to the other end of resistor R20 and the collector of transistor Q11. The base of transistor Q11 is electrically connected to the base of transistor Q12 and one end of resistor R18. The emitter of transistor Q11 is electrically connected to the emitter of transistor Q12, one end of resistor R21, and one end of resistor R23. The other end of resistor R21 is electrically connected to one end of resistor R22. The other end of resistor R23 is electrically connected to one end of resistor R24. The other ends of resistor R22, resistor R24, the collector of transistor Q12, and the other end of resistor R18 are all grounded.

[0022] Based on the above technical solutions, preferably, transistors Q5 and Q11 both use PBSS4330X transistors, and transistors Q6 and Q12 both use PBSS5330X transistors.

[0023] The present invention provides an output synchronous rectified pulse width modulation signal control and driving circuit, which has the following advantages over the prior art:

[0024] (1) Through the coordinated operation of the oscillation control circuit, interlock control circuit, shaping drive circuit and output drive circuit, the transformer output waveform is accurately followed and corrected, the transformer positive and negative output MOSFETs are safely interlocked and controlled, the pulse width modulation signal is standardized and shaped, and the gate drive capability is strong. This reduces the internal loss of the main power MOSFETs and improves the working efficiency of the output synchronous rectifier circuit, thereby significantly improving the overall power conversion efficiency and electrical performance of the rectifier module. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a schematic diagram of the system structure of a synchronous rectified pulse width modulation signal control and driving circuit according to the present invention;

[0027] Figure 2 This is the overall circuit wiring diagram of a synchronous rectified pulse width modulation signal control and drive circuit according to the present invention. Detailed Implementation

[0028] The technical solutions of this utility model will be clearly and completely described below with reference to the embodiments of this utility model. Obviously, the described embodiments are only a part of the embodiments of this utility model, and not all of them. Based on the embodiments of this utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this utility model.

[0029] Please see Figure 1 This utility model provides an output synchronous rectified pulse width modulation signal control and driving circuit, including an oscillation control circuit, a shaping driving circuit, an output driving circuit, and an interlock control circuit, wherein:

[0030] The oscillation control circuit and the interlock control circuit are both electrically connected to the shaping drive circuit, and the shaping drive circuit is electrically connected to the output drive circuit.

[0031] The oscillation control circuit is used to correct the waveform of the transformer signal;

[0032] The interlock control circuit is used to control the power MOSFETs at the positive and negative output terminals of the interlock transformer to be turned off and on.

[0033] The shaping drive circuit is used to reduce the internal losses of the main power MOSFET.

[0034] The output drive circuit is used to improve the working efficiency of the output synchronous rectifier circuit.

[0035] Specifically, this embodiment achieves precise tracking and correction of the transformer output waveform, safe interlock control of the MOSFETs at the positive and negative output terminals of the transformer, standardized shaping of the pulse width modulation signal, and strong gate driving capability through the coordinated operation of the oscillation control circuit, interlock control, shaping drive circuit, and output drive circuit. This reduces the internal losses of the main power MOSFETs and improves the working efficiency of the output synchronous rectification circuit, thereby significantly improving the overall power conversion efficiency and electrical performance of the rectifier module.

[0036] Please see Figure 2 The oscillation control circuit includes resistors R4-R5, resistors R16-R17, diode group D5, diode group D10, Zener diode D2, Zener diode D7, transistor group Q2, and transistor group Q8.

[0037] One end of resistor R4 is electrically connected to the cathode of Zener diode D2 and pin 3 of transistor group Q2. The other end of resistor R4 is electrically connected to one end of resistor R5. The other end of resistor R5 is electrically connected to the anode of Zener diode D2 and pins 2, 5, and 6 of transistor group Q2. Pin 1 of transistor group Q2 is electrically connected to pin 3 of diode group D5. Pin 4 of transistor group Q2 is electrically connected to pin 4 of diode group D5. Pin 2 of diode group D5 is connected to the positive terminal of transformer to output signal Tout+. Pin 1 of diode group D5 is grounded.

[0038] One end of resistor R16 is electrically connected to the cathode of Zener diode D7 and pin 3 of transistor group Q8. The other end of resistor R16 is electrically connected to one end of resistor R17. The other end of resistor R17 is electrically connected to the anode of Zener diode D7 and pins 2, 5, and 6 of transistor group Q8. Pin 1 of transistor group Q8 is electrically connected to pin 3 of diode group D10. Pin 4 of transistor group Q8 is electrically connected to pin 4 of diode group D10. Pin 2 of diode group D10 is connected to the negative terminal of transformer to output signal Tout-. Pin 1 of diode group D10 is grounded.

[0039] Specifically, the working principle of the oscillation control circuit in this embodiment is as follows: when the positive (negative) output terminal of the transformer outputs a high level, transistor 1 inside transistor group Q2 (Q8) is cut off, transistor 2 is turned on, the control circuit outputs a low level, and the power MOSFET is turned off; when the positive (negative) output terminal of the transformer outputs a low level, transistor 1 in transistor group Q2 (Q8) is turned on, transistor 2 is cut off, the control circuit outputs a high level, and the power MOSFET is turned on. This effectively tracks and corrects the transformer output waveform.

[0040] Please see Figure 2The interlock control circuit includes resistors R1-R2, resistors R13-R14, capacitors C1 and C5, diodes D1 and D6, MOSFET Q1, and MOSFET Q7.

[0041] One end of resistor R1 is electrically connected to one end of capacitor C1 and the positive terminal of diode D1, the other end of capacitor C1 is electrically connected to the negative terminal of diode D1, the gate of MOSFET Q1, and one end of resistor R2, and the other end of resistor R2 is electrically connected to ground via the source of MOSFET Q1.

[0042] One end of resistor R13 is electrically connected to one end of capacitor C5 and the positive terminal of diode D6. The other end of capacitor C5 is electrically connected to the negative terminal of diode D6, the gate of MOSFET Q7, and one end of resistor R14. The other end of resistor R14 is electrically connected to the source of MOSFET Q7 and ground.

[0043] Specifically, the working principle of the interlock control circuit in this embodiment is that MOSFETs Q1 and Q7 control the interlocking cutoff and conduction through two PWM signal outputs, so that the waveforms of the two PWM signals are exactly opposite, causing the power MOSFETs at the positive and negative output terminals of the transformer to interlock on and off without affecting each other, thus achieving a safe and reliable PWM signal drive circuit.

[0044] Please see Figure 2 The shaping drive circuit includes resistors R3 and R15, capacitors C2-C4 and C6-C8, diodes D4 and D9, Zener diodes D3 and D8, transistors Q3-Q4 and Q9-Q10.

[0045] One end of resistor R3 is connected to a +12V power supply. The other end of resistor R3 is electrically connected to one end of capacitor C2, one end of capacitor C3, and the collector of transistor Q3. The other ends of capacitor C2 and capacitor C3 are both grounded. The emitter of transistor Q3 is electrically connected to the emitter of transistor Q4, the anode of diode D4, the cathode of Zener diode D3, and one end of capacitor C4. The other end of capacitor C4 is electrically connected to the anode of Zener diode D3 and the cathode of diode D4. The base of transistor Q4 is electrically connected to the base of transistor Q3. The collector of transistor Q4 is grounded.

[0046] One end of resistor R15 is connected to a +12V power supply. The other end of resistor R15 is electrically connected to one end of capacitor C6, one end of capacitor C7, and the collector of transistor Q9. The other ends of capacitors C6 and C7 are grounded. The emitter of transistor Q9 is electrically connected to the emitter of transistor Q10, the anode of diode D9, the cathode of Zener diode D8, and one end of capacitor C8. The other end of capacitor C8 is electrically connected to the anode of Zener diode D8 and the cathode of diode D9. The base of transistor Q10 is electrically connected to the base of transistor Q9. The collector of transistor Q10 is grounded.

[0047] Specifically, the shaping drive circuit in this embodiment works by using two sets of upper and lower transistor totem circuits composed of transistors Q3, Q4, Q9, and Q10 to clamp the two PWM pulse width modulation signals, making the waveform more standard and free from distortion. A forward conduction circuit composed of diodes D4 and D9, and a reverse discharge circuit composed of Zener diodes D3 and D8, allows for rapid discharge of the MOSFET gate charge when the main power MOSFET is turned off, resulting in a more complete and faster turn-off and thus reducing the internal operating losses of the main power MOSFET.

[0048] Please see Figure 2 The output drive circuit includes resistors R6-R12, resistors R18-R24, transistors Q5-Q6, and transistors Q11-Q12.

[0049] One end of resistor R6 is electrically connected to one end of resistor R7. The other end of resistor R6 is electrically connected to the other end of resistor R7 and the collector of transistor Q5. The base of transistor Q5 is electrically connected to the base of transistor Q6 and one end of resistor R8. The emitter of transistor Q5 is electrically connected to the emitter of transistor Q6, one end of resistor R9, and one end of resistor R11. The other end of resistor R9 is electrically connected to one end of resistor R10. The other end of resistor R11 is electrically connected to one end of resistor R12. The other ends of resistor R10, resistor R12, the collector of transistor Q6, and the other end of resistor R8 are all grounded.

[0050] One end of resistor R19 is electrically connected to one end of resistor R20. The other end of resistor R19 is electrically connected to the other end of resistor R20 and the collector of transistor Q11. The base of transistor Q11 is electrically connected to the base of transistor Q12 and one end of resistor R18. The emitter of transistor Q11 is electrically connected to the emitter of transistor Q12, one end of resistor R21, and one end of resistor R23. The other end of resistor R21 is electrically connected to one end of resistor R22. The other end of resistor R23 is electrically connected to one end of resistor R24. The other ends of resistor R22, resistor R24, the collector of transistor Q12, and the other end of resistor R18 are all grounded.

[0051] Transistors Q5 and Q11 both use PBSS4330X transistors, while transistors Q6 and Q12 both use PBSS5330X transistors.

[0052] Specifically, the output drive circuit in this embodiment works by using two sets of upper and lower transistor totem circuits composed of transistors Q5, Q6, Q11, and Q12 to clamp the two PWM pulse width modulation signals, making the waveform more standard and improving the gate drive capability of the MOSFETs. The circuit composed of resistors R9, R10, R11, R12, R21, R22, R23, and R24 matches the parameters of the drive circuit with the performance indicators such as the forward switching time and input impedance of the main power MOSFET, achieving a more efficient switching state for the MOSFETs and improving the working efficiency of the output synchronous rectification circuit.

[0053] Specifically, the output synchronous rectification pulse width modulation signal control and driving circuit of this embodiment adopts a self-excited synchronous rectification control topology that follows the transformer output waveform, effectively corrects the transformer output waveform, and the PWM signal is generated autonomously without being affected by external factors.

[0054] The interlock control circuit uses the interlocking conduction principle of two MOSFETs to achieve the opposite waveforms of the two PWM signals, so that they do not affect each other, thus achieving a safe and reliable PWM signal drive circuit.

[0055] Two sets of upper and lower transistor totem circuits are used to clamp the two PWM pulse width modulation signals to make the waveform more standard and without distortion, thereby improving the performance of the power MOSFET gate drive signal.

[0056] By employing a reverse diode fast discharge circuit, the gate charge of the MOSFET is discharged rapidly, allowing the MOSFET to be turned off more fully and achieving a high-efficiency switching state. This reduces the power consumption of the module's main power circuit and improves its operating efficiency.

[0057] The entire circuit features simple and efficient interlocked switch control, standard correction and shaping of PWM signals, strong output load driving performance, and high-efficiency switching performance of MOSFETs.

[0058] The above description is only a preferred embodiment of the present utility model and is not intended to limit the present utility model. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present utility model should be included within the protection scope of the present utility model.

Claims

1. A synchronous rectified pulse width modulation signal output control and driving circuit, characterized in that, It includes an oscillation control circuit, a shaping drive circuit, an output drive circuit, and an interlock control circuit, wherein: The oscillation control circuit is electrically connected to the shaping drive circuit, and the oscillation control circuit is used to correct the waveform of the transformer signal. The interlock control circuit is electrically connected to the shaping drive circuit, and the interlock control circuit is used to control the power MOSFETs at the positive and negative output terminals of the interlock transformer to be turned off and on. The shaping drive circuit is electrically connected to the output drive circuit, and the shaping drive circuit is used to reduce the internal loss of the main power MOSFET. The output driving circuit is electrically connected to the shaping driving circuit, and the output driving circuit is used to improve the working efficiency of the output synchronous rectification circuit.

2. The output synchronous rectified pulse width modulation signal control and driving circuit as described in claim 1, characterized in that, The oscillation control circuit includes resistors R4-R5, resistors R16-R17, diode group D5, diode group D10, Zener diode D2, Zener diode D7, transistor group Q2, and transistor group Q8.

3. The output synchronous rectified pulse width modulation signal control and driving circuit as described in claim 2, characterized in that, One end of resistor R4 is electrically connected to the cathode of Zener diode D2 and pin 3 of transistor group Q2. The other end of resistor R4 is electrically connected to one end of resistor R5. The other end of resistor R5 is electrically connected to the anode of Zener diode D2 and pins 2, 5, and 6 of transistor group Q2. Pin 1 of transistor group Q2 is electrically connected to pin 3 of diode group D5. Pin 4 of transistor group Q2 is electrically connected to pin 4 of diode group D5. Pin 2 of diode group D5 is connected to the positive terminal of transformer to output signal Tout+. Pin 1 of diode group D5 is grounded. One end of resistor R16 is electrically connected to the cathode of Zener diode D7 and pin 3 of transistor group Q8. The other end of resistor R16 is electrically connected to one end of resistor R17. The other end of resistor R17 is electrically connected to the anode of Zener diode D7 and pins 2, 5, and 6 of transistor group Q8. Pin 1 of transistor group Q8 is electrically connected to pin 3 of diode group D10. Pin 4 of transistor group Q8 is electrically connected to pin 4 of diode group D10. Pin 2 of diode group D10 is connected to the negative terminal of transformer to output signal Tout-. Pin 1 of diode group D10 is grounded.

4. The output synchronous rectified pulse width modulation signal control and driving circuit as described in claim 1, characterized in that, The interlock control circuit includes resistors R1-R2, resistors R13-R14, capacitor C1, capacitor C5, diode D1, diode D6, MOSFET Q1, and MOSFET Q7.

5. The output synchronous rectified pulse width modulation signal control and driving circuit as described in claim 4, characterized in that, One end of resistor R1 is electrically connected to one end of capacitor C1 and the positive terminal of diode D1, the other end of capacitor C1 is electrically connected to the negative terminal of diode D1, the gate of MOSFET Q1, and one end of resistor R2, and the other end of resistor R2 is electrically connected to ground via the source of MOSFET Q1. One end of resistor R13 is electrically connected to one end of capacitor C5 and the positive terminal of diode D6. The other end of capacitor C5 is electrically connected to the negative terminal of diode D6, the gate of MOSFET Q7, and one end of resistor R14. The other end of resistor R14 is electrically connected to the source of MOSFET Q7 and ground.

6. The output synchronous rectified pulse width modulation signal control and driving circuit as described in claim 1, characterized in that, The shaping drive circuit includes resistors R3 and R15, capacitors C2-C4 and C6-C8, diodes D4 and D9, Zener diodes D3 and D8, transistors Q3-Q4, and transistors Q9-Q10.

7. The output synchronous rectified pulse width modulation signal control and driving circuit as described in claim 6, characterized in that, One end of resistor R3 is connected to a +12V power supply. The other end of resistor R3 is electrically connected to one end of capacitor C2, one end of capacitor C3, and the collector of transistor Q3. The other ends of capacitor C2 and capacitor C3 are both grounded. The emitter of transistor Q3 is electrically connected to the emitter of transistor Q4, the anode of diode D4, the cathode of Zener diode D3, and one end of capacitor C4. The other end of capacitor C4 is electrically connected to the anode of Zener diode D3 and the cathode of diode D4. The base of transistor Q4 is electrically connected to the base of transistor Q3. The collector of transistor Q4 is grounded. One end of resistor R15 is connected to a +12V power supply. The other end of resistor R15 is electrically connected to one end of capacitor C6, one end of capacitor C7, and the collector of transistor Q9. The other ends of capacitors C6 and C7 are grounded. The emitter of transistor Q9 is electrically connected to the emitter of transistor Q10, the anode of diode D9, the cathode of Zener diode D8, and one end of capacitor C8. The other end of capacitor C8 is electrically connected to the anode of Zener diode D8 and the cathode of diode D9. The base of transistor Q10 is electrically connected to the base of transistor Q9. The collector of transistor Q10 is grounded.

8. The output synchronous rectified pulse width modulation signal control and driving circuit as described in claim 1, characterized in that, The output drive circuit includes resistors R6-R12, resistors R18-R24, transistors Q5-Q6, and transistors Q11-Q12.

9. The output synchronous rectified pulse width modulation signal control and driving circuit as described in claim 8, characterized in that, One end of resistor R6 is electrically connected to one end of resistor R7. The other end of resistor R6 is electrically connected to the other end of resistor R7 and the collector of transistor Q5. The base of transistor Q5 is electrically connected to the base of transistor Q6 and one end of resistor R8. The emitter of transistor Q5 is electrically connected to the emitter of transistor Q6, one end of resistor R9, and one end of resistor R11. The other end of resistor R9 is electrically connected to one end of resistor R10. The other end of resistor R11 is electrically connected to one end of resistor R12. The other ends of resistor R10, resistor R12, the collector of transistor Q6, and the other end of resistor R8 are all grounded. One end of resistor R19 is electrically connected to one end of resistor R20. The other end of resistor R19 is electrically connected to the other end of resistor R20 and the collector of transistor Q11. The base of transistor Q11 is electrically connected to the base of transistor Q12 and one end of resistor R18. The emitter of transistor Q11 is electrically connected to the emitter of transistor Q12, one end of resistor R21, and one end of resistor R23. The other end of resistor R21 is electrically connected to one end of resistor R22. The other end of resistor R23 is electrically connected to one end of resistor R24. The other ends of resistor R22, resistor R24, the collector of transistor Q12, and the other end of resistor R18 are all grounded.

10. The output synchronous rectified pulse width modulation signal control and driving circuit as described in claim 9, characterized in that, Transistors Q5 and Q11 both use PBSS4330X transistors, while transistors Q6 and Q12 both use PBSS5330X transistors.

Images