A slope compensation circuit for a DC-DC full-bridge converter in peak current mode

Abstract

This utility model relates to the field of circuit design technology, and in particular to a slope compensation circuit for a DC-DC full-bridge converter in peak current mode, including a current transformer T1; the secondary output terminal of the current transformer T1 is connected to the anode of diode D1, and the cathode of diode D1 is connected to one end of resistor R3, one end of resistor R4, and one end of resistor R1 respectively; the other end of resistor R1 is connected to one end of capacitor C1, forming signal point A; the other end of capacitor C1 is connected to signal point B; one end of capacitor C2 is connected to signal point B, and the other end is grounded; one end of resistor R5 is connected to a PWM signal source, and the other end is connected to signal point B. This solution does not require a dedicated constant current source chip, nor does it rely on the slope compensation module integrated inside the controller. It only uses conventional resistors, capacitors, and diodes to construct the slope signal generation path, has strong adaptability, and can be widely used in general PWM controllers without built-in slope compensation functions and various digital control platforms, especially suitable for digital power control systems.

Description

Technical Field

[0001] This utility model relates to the field of circuit design technology, and in particular to a slope compensation circuit for a DC-DC full-bridge converter in peak current mode. Background Technology

[0002] DC / DC full-bridge converters are widely used in communication power supplies, server power supplies, electric vehicle charging, and other fields due to their high efficiency and high power density. Peak Current Mode Control (PCMC) is a common control method with good current loop dynamic performance and overcurrent protection characteristics, and is therefore widely used in full-bridge converters. However, under this control method, when the PWM duty cycle is greater than 50%, the system is prone to entering an unstable subharmonic oscillation state, manifested as alternating wide and narrow pulses in the switching waveform of the power devices, especially when the output inductance is small. This oscillation will lead to a deterioration in the system's dynamic response, an increase in output voltage ripple, and even system control failure, affecting the stability and reliability of the entire power supply system.

[0003] To address the aforementioned issues, slope compensation technology is typically employed. This technology superimposes a set of sawtooth or linear ramp signals onto the inductor current detection signal, transforming the output of the error amplifier in the control loop from a constant reference signal into a dynamic signal with a certain slope. This effectively suppresses subharmonic oscillations and improves system stability. Currently, there are two main methods for implementing slope compensation signals.

[0004] One approach uses a dedicated control chip, where an internal current source generates a ramp compensation signal. The user can set the compensation amplitude via an external resistor. This method is compact but highly dependent on the specific control chip model, resulting in poor versatility. Another approach involves building an external constant current source circuit. A push-pull PWM signal controls the switch; when the PWM signal is valid, the constant current source charges an external capacitor, generating a linearly rising ramp signal, which is then superimposed on the inductor current signal to form the compensation current signal. This solution offers some flexibility, but the circuit structure is more complex, requiring a constant current chip, PWM signal controller, and multiple peripheral components, increasing the system design difficulty and cost. Utility Model Content

[0005] This invention addresses the problem that existing slope compensation schemes suffer from strong chip dependence or complex circuit structures, which hinder the simplification and standardization of control system design. It proposes a slope compensation circuit scheme that is simple in structure, highly versatile, and easy to implement, to meet the needs of controllers or conventional digital power systems without built-in compensation mechanisms.

[0006] This utility model is achieved through the following technical solution:

[0007] A slope compensation circuit for a DC-DC full-bridge converter in peak current mode includes: a current transformer T1, a diode D1, a resistor R1, a resistor R3, a resistor R4, a resistor R5, a capacitor C1, and a capacitor C2.

[0008] The secondary output terminal of the current transformer T1 is connected to the anode of diode D1. The cathode of diode D1 is connected to one end of resistor R3, one end of resistor R4, and one end of resistor R1, respectively. The other end of resistor R1 is connected to one end of capacitor C1, forming signal point A. The other end of capacitor C1 is connected to signal point B. One end of capacitor C2 is connected to signal point B, and the other end is grounded. One end of resistor R5 is connected to the PWM signal source, and the other end is connected to signal point B.

[0009] Furthermore, resistors R3 and R4 are connected in parallel, with their common parallel terminal connected to the cathode of diode D1, and the other common parallel terminal grounded.

[0010] Furthermore, the PWM signal source includes a PWMA signal terminal and a PWMB signal terminal; one end of the resistor R5 is connected to the logic OR output terminal of the PWMA signal source.

[0011] Furthermore, it also includes a resistor R2 and a diode D2. One end of the resistor R2 is connected to the anode of the diode D1, and the other end of the resistor R2 is connected to the cathode of the diode D2. The anode of the diode D2 is connected to the other end of the resistor R3, the other end of the resistor R4, and one end of the capacitor C2.

[0012] Furthermore, it also includes diode D3, the anode of which is connected to the other end of resistor R5, and the cathode of which is connected to the logic OR output terminal of the PWMA signal source.

[0013] Furthermore, it also includes diode D4, the anode of which is connected to one end of capacitor C1, and the cathode of diode D4 is connected to one end of resistor R5 and the cathode of diode D3.

[0014] Furthermore, it also includes capacitor C3, one end of which is connected to the VCC voltage input terminal, and the other end of which is grounded.

[0015] Beneficial effects of the utility model:

[0016] This invention proposes a slope compensation circuit for a DC-DC full-bridge converter in peak current mode, which has advantages such as simple structure, few components, and flexible implementation. Compared with existing compensation methods that rely on dedicated chips or constant current sources, this solution combines current sampling from a current transformer with PWM signal coupling. Resistor R5 controls the PWM level to charge capacitor C2, forming a slope compensation signal CP, which is then superimposed on the current sampling signal CS, thereby achieving a stable and reliable slope compensation function.

[0017] This solution does not require a dedicated constant current source chip, nor does it rely on the ramp compensation module integrated inside the controller. It can construct the ramp signal generation path using only conventional resistors, capacitors, and diodes. It has strong adaptability and can be widely used in general PWM controllers without built-in ramp compensation functions and various digital control platforms, especially in digital power control systems.

[0018] In this circuit, the slope compensation amplitude can be flexibly adjusted by changing the resistance value of resistor R5, facilitating optimized design based on different control strategies and power supply characteristics. Simultaneously, the slope signal generated by the direct coupling of capacitor C2 with the PWM signal exhibits natural synchronization, closely coordinating with the PWM switching state. When both PWMA and PWMB are low, it automatically completes the discharge process of C1 and C2, preparing for the next compensation cycle and ensuring signal periodicity and system stability.

[0019] Furthermore, the circuit has a compact structure, is easy to integrate and lay out, has strong component versatility, high reliability, and low cost. It is particularly suitable for digital power supply systems with high performance requirements and cost sensitivity. It can effectively suppress subharmonic oscillations that may be generated when the duty cycle exceeds 50% under peak current mode control, thereby improving the dynamic response speed and operational stability of the system. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a circuit diagram of a slope compensation circuit for a DC-DC full-bridge converter in peak current mode, as proposed in this utility model. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of this utility model clearer, the present utility model will be further described in detail below with reference to the embodiments and accompanying drawings. The illustrative embodiments and descriptions of this utility model are only used to explain this utility model and are not intended to limit this utility model. Example

[0023] refer to Figure 1 This embodiment proposes a slope compensation circuit for a DC-DC full-bridge converter in peak current mode, including a current transformer T1, a diode D1, a resistor R1, a resistor R3, a resistor R4, a resistor R5, a capacitor C1, and a capacitor C2.

[0024] The primary side of the current transformer T1 has four pins connected to a power conversion circuit. Pin 1 of the secondary side of the current transformer T1 is connected to the anode of diode D1 and one end of resistor R2. The cathode of diode D1 is connected to one end of resistor R3, one end of resistor R4, and one end of resistor R1. The other end of resistor R1 is connected to one end of capacitor C1, forming signal point A and the anode of diode D4. Signal point A outputs a CS signal. The other end of capacitor C1 is connected to signal point B. One end of capacitor C2 is connected to signal point B, and the other end is grounded. Pins 2 of the secondary side of the current transformer T1 are connected to two... The signal source is connected to the anode of diode D2, the other end of resistor R3, the other end of resistor R4, signal point B, one end of resistor R5, the anode of diode D3, and one end of capacitor C2. The cathode of diode D2 is connected to the other end of resistor R2. The other end of resistor R5 is connected to the cathodes of diode D4 and D3, and the output pin 4 of the signal source. The voltage input pin of the signal source is connected to the VCC voltage terminal and one end of capacitor C3. The other end of capacitor C3 is grounded. Input pin 1 of the signal source is connected to the PWMA signal, and input pin 2 of the signal source is connected to the PWMB signal.

[0025] The current transformer T1 is used to sample the current in the main circuit of the converter, and its secondary side leads out pins 3 and 4 as current signal output terminals. Pin 3 of the current transformer T1 is connected to the anode of diode D1 and one end of resistor R2; pin 4 of the current transformer T1 is connected to the anode of diode D2, the other end of resistors R3 and R4, signal point B, one end of resistor R5, the anode of diode D3, and one end of capacitor C2, forming a multi-point common connection structure.

[0026] In this embodiment, the main circuit current signal acquired by the current transformer T1 is rectified by diode D1. The cathode of diode D1 is connected to one end of resistors R3 and R4, and one end of resistor R1, to convert the forward current into a unidirectional voltage signal. Resistors R3 and R4 act as voltage dividers and impedance matching, and their parallel structure can adjust the output amplitude. Resistor R1 serves as a pre-stage filter resistor, forming a low-pass filter with capacitor C1 to smooth the current sampling signal. The filtered voltage forms signal point A between resistor R1 and capacitor C1, outputting signal CS. This signal represents the current information of the main current channel and has a certain anti-interference capability.

[0027] Signal point B is located at the connection between capacitors C1 and C2, and is the superposition point of the CS signal and the ramp signal CP. Capacitor C2 is connected to ground and is used to store the voltage energy provided by the PWM signal source through resistor R5, generating the ramp signal CP. Resistor R5 is connected to the output terminal of the PWM signal source, guiding the high level of the PWM to charge capacitor C2, forming a linearly rising ramp waveform. The resistance value of resistor R5 determines the charging rate and compensation slope, i.e., the compensation depth. The PWM signal source is a push-pull PWM signal with dead time, and its output is controlled by PWMA and PWMB. To control the formation and release of the ramp compensation signal, diodes D2, D3, and D4 are set in the circuit. Diode D2 is connected in series with resistor R2 to form a clamping protection path for the inductor current sampling channel; when there is reverse spike interference in the current transformer T1, it can be discharged through the conduction of diode D2 to prevent false triggering of the controller. Diode D3 is used to prevent the PWM signal from flowing back to resistor R5 and the subsequent circuit, improving signal isolation. Diode D4 is connected between one end of capacitor C1 and the node of resistor R5 and diode D3, ensuring that capacitor C1 can quickly discharge to the reference potential during the PWM low-level period, preparing for compensation in the next cycle. Capacitor C3 is connected in parallel with the voltage input pin of the PWM signal source, serving as a power supply decoupling agent, stabilizing the power supply to the signal source, and preventing power supply disturbances from affecting the stability of the compensation signal. The PWM signal source receives PWMA and PWMB signals through pins 1 and 2 respectively, and alternately drives the output PWM waveform according to the control strategy.

[0028] In this embodiment, the main circuit current signal is obtained through current transformer T1, and the CS signal is extracted by combining resistor voltage divider and filter network. At the same time, the PWM signal charges capacitor C2 through resistor R5 to form CP ramp signal. Finally, CS and CP are naturally superimposed at node A to form a stable and reliable compensation current signal. The entire compensation circuit relies only on conventional electronic components, without the need for a dedicated ramp generation chip or constant current source. It has a simple structure, high control accuracy, and is suitable for situations where ramp compensation function is missing in digital power supply control. Example

[0029] This embodiment proposes a working principle of a slope compensation circuit in the peak current mode of a DC-DC full-bridge converter, based on embodiment 1.

[0030] When the full-bridge converter operates in peak current mode control, the PWM signal source outputs a set of push-pull PWM signals with dead time, namely PWMA and PWMB. During the high level of either PWM signal, a positive current I is generated in the main power circuit, which flows through the primary side of current transformer T1. The secondary side of transformer T1 induces a sampling current proportional to the primary current. This current is rectified by diode D1 and flows through the parallel branch of resistors R3 and R4, converting the current signal into a voltage signal.

[0031] The converted voltage signal is then processed by an RC filter network consisting of resistor R1 and capacitor C1, outputting a smoothed current-voltage signal CS. This signal appears between signal point A and signal point B, i.e., the voltage between point A and point B. This voltage CS reflects the peak value of the load current and is one of the fundamental signals for peak current control.

[0032] Simultaneously, during the high period of the PWM signal, the PWM output level also charges capacitor C2 through resistor R5, forming a voltage signal CP that rises approximately linearly, i.e., the voltage of signal point B relative to ground. Since resistor R5 limits the charging current of capacitor C2, the rising slope of the ramp signal can be set by adjusting the resistance value of R5, thereby adjusting the depth of ramp compensation.

[0033] Therefore, the voltage at signal point A is actually composed of two parts: one is the CS signal reflecting the magnitude of the main current, and the other is the CP ramp signal formed by PWM signal control. These two are naturally superimposed in the circuit structure to form a current detection signal with slope compensation function. This signal is sent to the controller for current loop regulation, which can effectively suppress subharmonic oscillations generated when the duty cycle is greater than 50%, improving system stability and dynamic response capability. When both PWMA and PWMB are low, the controller enters a non-conducting state, no current flows on the primary side of the transformer, and simultaneously diodes D3 and D4 conduct, causing capacitors C2 and C1 to discharge rapidly through the loop, restoring them to their initial state and preparing for the re-establishment of the compensation waveform in the next PWM cycle.

[0034] This embodiment implements ramp compensation using a minimal number of conventional components, resulting in a simple structure and high adaptability. It is particularly suitable for PWM controllers or digital power supply systems that lack internal ramp compensation functionality, avoiding the use of DSP internal resources to generate ramp signals in digital control, simplifying control implementation, and improving reliability and system cost-effectiveness.

[0035] The foregoing has shown and described the basic principles, main features, and advantages of this utility model. Those skilled in the art should understand that this utility model is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of this utility model. Various changes and modifications can be made to this utility model without departing from its spirit and scope, and all such changes and modifications fall within the scope of the claimed utility model. The scope of protection of this utility model is defined by the appended claims and their equivalents.

Claims

1. A slope compensation circuit for a DCDC full-bridge converter in peak current mode, characterized by, include: Current transformer T1, diode D1, resistor R1, resistor R3, resistor R4, resistor R5, capacitor C1, capacitor C2; The secondary output terminal of the current transformer T1 is connected to the anode of diode D1, and the cathode of diode D1 is connected to one end of resistor R3, one end of resistor R4 and one end of resistor R1 respectively; the other end of resistor R1 is connected to one end of capacitor C1, forming signal point A. The other end of capacitor C1 is connected to signal point B; One end of capacitor C2 is connected to signal point B, and the other end is grounded; one end of resistor R5 is connected to the PWM signal source, and the other end is connected to signal point B.

2. The slope compensation circuit for peak current mode of a DCDC full bridge converter according to claim 1, characterized in that, The resistors R3 and R4 are connected in parallel, with their common terminal connected to the cathode of diode D1 and the other common terminal grounded.

3. The slope compensation circuit for a DC-DC full-bridge converter in peak current mode according to claim 1, characterized in that, The PWM signal source includes a PWMA signal terminal and a PWMB signal terminal; one end of the resistor R5 is connected to the logic OR output terminal of the PWMA signal source.

4. The slope compensation circuit for a DC-DC full-bridge converter in peak current mode according to claim 1, characterized in that, It also includes a resistor R2 and a diode D2. One end of the resistor R2 is connected to the anode of the diode D1, and the other end of the resistor R2 is connected to the cathode of the diode D2. The anode of the diode D2 is connected to the other end of the resistor R3, the other end of the resistor R4, and one end of the capacitor C2.

5. The slope compensation circuit for a DC-DC full-bridge converter in peak current mode according to claim 1, characterized in that, It also includes diode D3, the anode of which is connected to the other end of resistor R5, and the cathode of which is connected to the logic OR output terminal of the PWMA signal source.

6. The slope compensation circuit for a DC-DC full-bridge converter in peak current mode according to claim 1, characterized in that, It also includes diode D4, the anode of which is connected to one end of capacitor C1, and the cathode of diode D4 is connected to one end of resistor R5 and the cathode of diode D3.

7. The slope compensation circuit for a DC-DC full-bridge converter in peak current mode according to claim 1, characterized in that, It also includes capacitor C3, one end of which is connected to the VCC voltage input terminal, and the other end of which is grounded.

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