An edge-isolated sliced ​​cell and photovoltaic module

Abstract

This invention provides an edge-isolated sliced ​​solar cell and photovoltaic module, comprising a silicon wafer. The front side of the silicon wafer has a cell working area covering a boron emitter and a pn junction isolation area formed by removing the boron emitter. A front electrode is disposed within the cell working area. At least one side of the silicon wafer along its length has a sliced ​​area. The pn junction isolation area is located between the front electrode and the sliced ​​area. The surface of the pn junction isolation area is covered with a first passivation layer, and the surface of the sliced ​​area is covered with a second passivation layer. This invention forms a pn junction-free isolation structure between the sliced ​​area and the electrode, cutting off the transport path of minority carriers from the cell working area to the sliced ​​area. This effectively suppresses the influence of carrier recombination dark current in the sliced ​​area on the cell working area. Combined with the first passivation layer of the pn junction isolation area and the second passivation layer of the sliced ​​area, recombination and leakage at the cell cutting edge can be essentially eliminated, thereby improving the efficiency of the sliced ​​solar cell.

Description

Technical Field

[0001] This utility model relates to the field of crystalline silicon solar cell fabrication technology, and more specifically, to an edge-isolated sliced ​​cell and photovoltaic module. Background Technology

[0002] Slicing technology is a photovoltaic module technology that involves cutting standard-sized solar cells into identical half-cells or multiple cells along a direction perpendicular to the main grid lines, and then welding them together in series. Slicing technology offers advantages such as improved encapsulation efficiency, reduced module temperature rise, and reduced shading losses. However, for sliced ​​cells, the edges of the laser-cut cells exhibit significant carrier recombination, and this recombination becomes increasingly severe as the perimeter-to-area ratio of small-sized cells increases. This is because the laser thermal ablation and mechanical damage caused by cutting the cells create defects on the cell surface or edges, leading to edge recombination of charge carriers (electrons and holes) at these defects. For TOPCon tunneling silicon oxide passivated contact (TOPCon) sliced ​​cells, the efficiency impact of edge recombination is particularly significant.

[0003] To address the efficiency loss in TOPCon cells caused by wafer slicing, the industry has proposed using atomic layer deposition (ALD) technology to deposit a certain thickness (approximately 20-60 nm) of aluminum oxide (AlO2) at the edge of the silicon wafer after slicing. x Edge passivation can be performed using other passivation films. However, studies have found that the sliced ​​cells processed by this technique still exhibit significant edge recombination, resulting in substantial efficiency loss. Utility Model Content

[0004] In view of the shortcomings of the existing technology, the present invention aims to solve the problem that the existing edge passivation technology cannot eliminate edge commingling and results in a large loss of efficiency.

[0005] To achieve the above objectives, this utility model provides an edge-isolated sliced ​​battery, comprising a silicon wafer. The front side of the silicon wafer has a battery working area covering a boron emitter and a pn junction isolation area formed by removing the boron emitter. A front electrode is provided in the battery working area. At least one side of the silicon wafer along its length has a sliced ​​area. The pn junction isolation area is located between the front electrode and the sliced ​​area. The surface of the pn junction isolation area is covered with a first passivation layer, and the surface of the sliced ​​area is covered with a second passivation layer.

[0006] This invention forms a pn-junction-free isolation structure between the slicing region and the electrode, cutting off the transmission path of minority carriers from the battery working region to the slicing region. This effectively suppresses the influence of carrier recombination dark current in the slicing region on the battery working region. Combined with the first passivation layer of the pn-junction isolation region and the second passivation layer of the slicing region, recombination and leakage at the battery cutting edge can be basically eliminated, thereby improving the efficiency of the sliced ​​battery.

[0007] Furthermore, the distance between the pn junction isolation region and the slice region is 0~5 mm. The pn junction isolation region is connected to or close to the slice region to ensure the isolation effect.

[0008] Furthermore, the pn junction isolation region is connected to the slice region. This structure allows the pn junction isolation region to completely cover the potential recombination region at the slice edge, ensuring effective blocking of carrier transport.

[0009] Furthermore, the first passivation layer is selected from AlO. x Thin film, SiN x Thin film, SiO x Thin film, SiO x N y The thin film or its stacked combination thereof, wherein the thickness of the first passivation layer is 10~200 nm. The first passivation layer performs surface passivation on the pn junction isolation region to avoid additional recombination; the thickness range of the first passivation layer takes into account both passivation effect and process compatibility.

[0010] Furthermore, the second passivation layer is selected from AlO. x Thin film, SiN x Thin film, SiO x Thin film, SiO x N y The thin film or its stacked combination, wherein the thickness of the second passivation layer is 5~100nm. The second passivation layer precisely repairs surface damage in the sliced ​​area, eliminating recombination and leakage phenomena; the thickness of the first passivation layer ensures both passivation effect and manufacturing cost.

[0011] Furthermore, the surface height of the pn junction isolation region is lower than that of the battery working region. The pn junction isolation region and the battery working region are connected by a transition region with a slope structure. The first passivation layer continuously covers the pn junction isolation region, the transition region, and the boron emitter. The slope structure of the transition region helps the first passivation layer to cover more uniformly, reduces void formation, lowers the probability of recombination centers, and further optimizes battery performance.

[0012] Furthermore, the slope angle of the transition region is 20°~60°, and the vertical height is 1~10μm. The angle range of the transition region ensures that the first passivation layer fits better when the transition region achieves the transition connection between the emitter region and the pn junction isolation region. It avoids the unnatural transition caused by too small a slope angle, which would affect the passivation layer coverage, and also avoids material waste caused by too large a slope angle. The height range of the transition region ensures both edge isolation effect and sufficient transition space between the battery working area and the pn junction isolation region.

[0013] Furthermore, the back side of the silicon wafer is provided with a nano-silicon oxide layer, a phosphorus-doped polycrystalline silicon layer, and a back electrode in contact with the phosphorus-doped polycrystalline silicon layer.

[0014] This invention also provides a photovoltaic module, including the aforementioned edge-isolated sliced ​​cells, which can fully utilize the high-efficiency photoelectric conversion performance of the cells and improve the overall output power and conversion efficiency of the photovoltaic module.

[0015] In summary, the present invention has the following advantages over the prior art:

[0016] (1) This utility model suppresses significant carrier recombination at the edge of the slice by using the pn junction isolation structure, effectively cutting off the minority carrier transport channel, thereby reducing battery efficiency loss.

[0017] (2) The present invention adopts a composite passivation layer system. The first passivation layer on the surface of the pn junction isolation region reduces the surface defect state density, while the second passivation layer on the surface of the slicing region performs directional repair on the laser-damaged area and reduces surface recombination. The two passivation layers work together to significantly reduce recombination and leakage phenomena at the cutting edge.

[0018] (3) The pn junction isolation area and the battery working area of ​​this utility model are connected by a specific slope structure, which provides a smooth transition basis for the first passivation layer coverage, avoids the occurrence of coverage gaps and defects, reduces the interface recombination center, and improves the surface passivation effect. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the structure of a sliced ​​battery in a specific embodiment.

[0020] Figure 2 This is a schematic diagram of another sliced ​​battery structure in a specific embodiment.

[0021] Figure 3 for Figure 2 Enlarged view of a section at point A

[0022] Explanation of reference numerals in the attached figures:

[0023] 1-Silicon wafer, 2-Boron emitter, 3-pn junction isolation region, 4-Battery working region, 5-Transition region, 6-Slice region, 7-First passivation layer, 8-Second passivation layer, 9-Phosphorus diffusion layer, 10-Nano silicon oxide layer, 11-Phosphorus-doped polycrystalline silicon layer, 12-Third passivation layer, 13-Front electrode, 14-Back electrode. Detailed Implementation

[0024] To make the above-mentioned objectives, features, and advantages of this utility model more apparent and understandable, specific embodiments of this utility model will be described in detail below with reference to the accompanying drawings. It should be noted that the following embodiments are only used to illustrate the implementation methods and typical parameters of this utility model, and are not intended to limit the parameter range described in this utility model. Reasonable variations derived therefrom are still within the protection scope of the claims of this utility model.

[0025] It should be noted that the endpoints and any values ​​of the ranges disclosed herein are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges or values. For numerical ranges, the endpoint values ​​of the various ranges, the endpoint values ​​of the various ranges and individual point values, and individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed herein.

[0026] A specific embodiment of this utility model provides an edge-isolated sliced ​​battery, with a typical structure as follows: Figure 1 As shown, the device includes a silicon wafer 1, with a sliced ​​region 6 formed by slicing on one side along its length. A boron emitter 2 is present on the front side of the silicon wafer 1, forming a battery working region 4. A PN junction is formed between the boron emitter 2 and the silicon wafer 1. A first electrode is provided on the front side of the silicon wafer 1, contacting the boron emitter 2. The boron emitter 2 is removed from the front side of the silicon wafer 1 near the sliced ​​region 6 to form a PN junction isolation region 3, which can cut off the transport path of minority carriers from the battery working region 4 to the sliced ​​region 6, effectively suppressing the influence of carrier recombination dark current in the sliced ​​region 6 on the battery working region 4. A phosphorus diffusion layer 9 is present on the back side of the silicon wafer 1. A nano-silicon oxide layer 10 and a phosphorus-doped polycrystalline silicon layer 11 are sequentially disposed on the phosphorus diffusion layer 9, forming a TOPCon structure. A back electrode 14 is also provided on the back side of the silicon wafer 1, contacting the phosphorus-doped polycrystalline silicon layer 11.

[0027] In a specific embodiment, the distance between the pn junction isolation region 3 and the slicing region 6 is less than or equal to 5 mm, and the width of the pn junction isolation region 3 is greater than or equal to 10 µm. In a preferred embodiment, the pn junction isolation region 3 is connected to the slicing region 6, and the width of the pn junction isolation region 3 is 60~300 µm. The surface of the pn junction isolation region 3 has a textured or planar structure.

[0028] Combination Figure 1 As shown, the boron emission and pn junction isolation region 3 on the front side of silicon wafer 1 is covered by a continuous first passivation layer 7. In a specific embodiment, the first passivation layer 7 is selected from SiN. x Thin film, SiO x Thin film, SiO x N y The thin film or its stacked combination has an overall thickness of 10-200 nm. In a preferred embodiment, the first passivation layer 7 is made of AlO₂. x Thin films and SiNx The thin film is composed of a stacked layer. The surface of the sliced ​​region 6 is covered with a second passivation layer 8. In a specific embodiment, the second passivation layer 8 is selected from SiN. x Thin film, SiO x Thin film, SiO x N y The thin film or its stacked combination has an overall thickness of 5-100 nm. In a preferred embodiment, the second passivation layer 8 is made of AlO₂. x The thin film is constructed as follows: A first passivation layer 7 on the surface of the pn junction isolation region 3 reduces the surface defect state density, while a second passivation layer 8 on the surface of the slice region 6 performs directional repair on the laser-damaged area, reducing surface recombination. The two passivation layers work together to significantly reduce recombination and leakage phenomena at the cutting edge. In some embodiments, the second passivation layer 8 extends to the side of the first passivation layer 7. Since the surface height of the pn junction isolation region 3 is lower than the surface height of the boron emitter 2, a step gap will appear where the first passivation layer 7 covers the surface of the pn junction isolation region 3. In some embodiments, the second passivation layer 8 extends to fill this gap; in other embodiments, the first passivation layer 7 extends to the top surface of the second passivation layer 8. In some embodiments, the first passivation layer 7 extends to cover the uncut side of the silicon wafer 1, which helps to eliminate recombination at the uncut edge. A third passivation layer 12 is provided on the phosphorus-doped polycrystalline silicon layer 11 on the back side of the silicon wafer 1. In a specific embodiment, the third passivation layer 12 is selected from SiN. x Thin film, SiO x Thin film, SiO x N y The thin film or its stacked combination has an overall thickness of 10-200 nm. In a preferred embodiment, the third passivation layer 12 is made of SiN. x Thin film composition.

[0029] Combination Figure 2 and Figure 3 As shown, another edge-isolated sliced ​​cell structure is provided, which differs from the sliced ​​cell described above in that: both sides of the silicon wafer 1 along its length have sliced ​​regions 6 formed after slicing, and the surfaces of both sliced ​​regions 6 are covered with a second passivation layer 8. The pn junction isolation region 3 and the cell working region 4 on the front side of the silicon wafer 1 are connected by a transition region 5, which has a sloping structure. The first passivation layer 7 continuously covers the pn junction isolation region 3, the transition region 5, and the boron emitter 2. The sloping structure of the transition region 5 helps to achieve more uniform passivation layer coverage, reduce void formation, and lower the probability of recombination centers.

[0030] In some specific embodiments, the size of the transition region 5 is optimized, controlling the slope angle of the transition region 5 to be 20°~60° and the vertical height to be 1~10μm. By limiting the size of the transition region 5, the edge isolation effect is ensured, and sufficient transition space is provided between the battery working area 4 and the pn junction isolation area 3, ensuring the coverage effect of the first passivation layer 7 and avoiding gaps.

[0031] A photovoltaic module composed of edge-isolated sliced ​​cells can fully utilize the high photoelectric conversion performance of the sliced ​​cells, thereby improving the overall output power and conversion efficiency of the photovoltaic module.

[0032] The technical solution and effects of this utility model are illustrated by specific embodiments below.

[0033] Example 1

[0034] The steps for fabricating edge-isolated TOPCon sliced ​​solar cells are as follows:

[0035] (1) Prepare an n-type silicon wafer, perform texturing on the front side, polishing on the back side, and standard RCA cleaning. Boron diffusion occurs on the front side of the silicon wafer to form a boron emitter.

[0036] (2) Backside polishing; nano-silicon oxide and phosphorus-doped amorphous silicon are deposited sequentially on the backside.

[0037] (3) Perform high-temperature annealing to obtain TOPCon structure passivated sheet.

[0038] (4) Grooving is performed on the area with a certain width corresponding to the reserved cutting line of the passivation sheet, and the emitter at the corresponding position is removed to form a pn junction isolation region with a width of about 80 μm. The edge of the pn junction isolation region is a nearly vertical structure with a vertical height of 4 μm.

[0039] (5) An aluminum oxide film with a thickness of about 10 nm is prepared on the front side of the passivation sheet, and then a silicon nitride film with a thickness of about 70 nm is deposited on both sides. The passivation sheet is then metallized on both sides.

[0040] (6) Align with the reserved cutting line and perform laser cutting to obtain two sliced ​​batteries.

[0041] (7) Prepare an aluminum oxide film with a thickness of about 20 nm in the side slicing area of ​​the sliced ​​battery.

[0042] Test the performance of the prepared sliced ​​cells: open circuit voltage (V) oc =735.4mV, short-circuit current density (J) sc =41.36mA / cm 2 The fill factor (FF) is 85.92% and the efficiency (Eff.) is 25.97%.

[0043] The sliced ​​battery prepared in this embodiment was used to fabricate 10 108 half-cell TOPCon battery modules, each module measuring 9.1 cm × 18.2 cm. The average power of the modules was tested to be 442.5 W.

[0044] Example 2

[0045] The steps for preparing edge-isolated TOPCon sliced ​​batteries are basically the same as those in Example 1, except that the thickness of the alumina film prepared in step (7) is about 5 nm.

[0046] Test the performance of sliced ​​batteries with sliced ​​areas on both sides: V oc =735.6V, J sc =41.35mA / cm 2 FF=85.88%, Eff=25.96%.

[0047] The sliced ​​battery prepared in this embodiment was used to make a battery module with the same structure as in Example 1. After testing, the average power of the module was 442.3W.

[0048] Example 3

[0049] The preparation of the edge-isolated TOPCon sliced ​​battery follows the same steps as in Example 1, except that in step (4), two cutting lines are reserved on the passivation sheet, and grooves are made at the corresponding positions to remove the emitter and form a pn junction isolation region with a width of about 60 μm. The edge of the pn junction isolation region is a nearly vertical structure with a vertical height of 5 μm. In step (7), an aluminum oxide film with a thickness of about 30 nm is prepared on the surface of the sliced ​​area on both sides of the sliced ​​battery.

[0050] Test the performance of sliced ​​batteries with sliced ​​areas on both sides: V oc =735.1V, J sc =41.37mA / cm 2 FF=85.37%, Eff=25.91%.

[0051] The sliced ​​battery prepared in this embodiment was used to make a battery module with the same structure as in Example 1. After testing, the average power of the module was 441.2W.

[0052] Example 4

[0053] The steps for preparing edge-isolated TOPCon sliced ​​cells are basically the same as those in Example 1, except that: in step (4), a pn junction isolation region with a width of about 100 μm is formed, and the two sides of the pn junction isolation region are transition regions with a slope structure. The vertical height of the transition region is about 4 μm and the slope angle is about 50°.

[0054] Performance of the prepared sliced ​​battery tested: Voc =737.9V, J sc =42.11mA / cm 2 FF=86.64%, Eff=26.46%.

[0055] The sliced ​​battery prepared in this embodiment was used to make a battery module with the same structure as in Example 1. The average power of the module was tested and found to be 446.7W.

[0056] Example 5

[0057] The steps for preparing edge-isolated TOPCon sliced ​​cells are basically the same as those in Example 1, except that: in step (4), a pn junction isolation region with a width of about 100 μm is formed, and the two sides of the pn junction isolation region are transition regions with a slope structure. The vertical height of the transition region is about 3 μm and the slope angle is about 30°.

[0058] Performance of the prepared sliced ​​battery tested: V oc =737.2V, J sc =41.15mA / cm 2 FF=86.45%, Eff=26.42%.

[0059] The sliced ​​battery prepared in this embodiment was used to make a battery module with the same structure as in Example 1. After testing, the average power of the module was 445.9W.

[0060] Comparative Example 1

[0061] The steps for preparing edge-isolated TOPCon sliced ​​cells are basically the same as those in Example 1, except that steps (4) and (7) are omitted.

[0062] Performance of the prepared sliced ​​battery tested: V oc =732.2V, J sc =41.82mA / cm 2 FF=84.92%, Eff=25.69%.

[0063] The sliced ​​battery prepared in this comparative example was used to make a battery module with the same structure as in Example 1. The average power of the module was tested and found to be 436.8W.

[0064] Comparative Example 2

[0065] The steps for preparing edge-isolated TOPCon sliced ​​cells are basically the same as those in Example 1, except that step (4) is omitted.

[0066] Performance of the prepared sliced ​​battery tested: V oc =734.5V, J sc =41.59mA / cm2 FF=85.11%, Eff=25.84%.

[0067] The sliced ​​battery prepared in this comparative example was used to make a battery module with the same structure as in Example 1. The average power of the module was tested and found to be 439.5W.

[0068] Table 1. Comparison of battery performance between the examples and comparative examples.

[0069]

[0070] The statistical results in Table 1 demonstrate that the technology of this invention can significantly improve the sliced ​​cells, reduce efficiency loss, and increase the overall power of photovoltaic modules.

[0071] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the present invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A sliced ​​battery with edge isolation, characterized in that, The silicon wafer includes a cell working region covering a boron emitter and a pn junction isolation region formed by removing the boron emitter on its front side. A front electrode is disposed within the cell working region. At least one side of the silicon wafer along its length has a sliced ​​area. The pn junction isolation region is located between the front electrode and the sliced ​​area. The surface of the pn junction isolation region is covered with a first passivation layer, and the surface of the sliced ​​area is covered with a second passivation layer. The first passivation layer is selected from AlO₂. x Thin film, SiN x Thin film, SiO x Thin film, SiO x N y The thin film or its stacked combination thereof, wherein the thickness of the first passivation layer is 10~200 nm, and the second passivation layer is selected from AlO. x Thin film, SiN x Thin film, SiO x Thin film, SiO x N y The thin film or its stacked combination thereof, wherein the thickness of the second passivation layer is 5~100nm.

2. The edge-isolated sliced ​​battery according to claim 1, characterized in that, The distance between the pn junction isolation region and the slice region is 0~5 mm.

3. The edge-isolated sliced ​​battery according to claim 2, characterized in that, The pn junction isolation region is connected to the slice region.

4. The edge-isolated sliced ​​battery according to claim 1, characterized in that, The width of the pn junction isolation region is greater than or equal to 10µm.

5. The edge-isolated sliced ​​battery according to claim 1, characterized in that, The surface height of the pn junction isolation region is lower than that of the battery working region. The pn junction isolation region and the battery working region are connected by a transition region with a slope structure. The first passivation layer continuously covers the pn junction isolation region, the transition region and the boron emitter.

6. The edge-isolated sliced ​​battery according to claim 5, characterized in that, The slope angle of the transition zone is 20°~60°, and the vertical height is 1~10μm.

7. The edge-isolated sliced ​​battery according to any one of claims 1-6, characterized in that, The back side of the silicon wafer is provided with a nano-silicon oxide layer, a phosphorus-doped polycrystalline silicon layer, and a back electrode in contact with the phosphorus-doped polycrystalline silicon layer.

8. A photovoltaic module, characterized in that, Including edge-isolated sliced ​​batteries as described in any one of claims 1-7.

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