Power supply circuit for quantum chip readout link, quantum computer

Abstract

This application discloses a power supply circuit for a quantum chip readout link and a quantum computer, belonging to the field of quantum computing technology. The quantum chip readout link includes a first low-noise amplifier in a low-temperature region and a second low-noise amplifier in a room-temperature region connected in series. The quantum chip readout link includes: an FPGA module that outputs a control signal including a first voltage signal, a second voltage signal, and a third voltage signal of a target value; and several pairs of adjustable voltage output modules and fixed voltage output modules. Each pair of adjustable voltage output modules and fixed voltage output modules is electrically connected to the output control terminal of the FPGA module, used to output an adjustable first voltage signal and a second voltage signal to the gate and drain of the first low-noise amplifier, and a fixed third voltage signal to the drain of the second low-noise amplifier, according to the target value. This application significantly increases the number of channels while allowing the output voltage to be adjusted as needed.

Description

Technical Field

[0001] This application relates to the field of quantum computing technology, and in particular to a power supply circuit for a quantum chip readout link and a quantum computer. Background Technology

[0002] In quantum computing measurement and control systems, the readout link is a crucial component for detecting and amplifying the weak signals output by quantum chips (such as superconducting qubits and semiconductor quantum dots). Its design must balance low noise, high bandwidth, and signal integrity. Its components can be categorized into cryogenic and room-temperature ends based on temperature range and signal flow. The cryogenic end consists of: quantum chip → isolator / JPA (parametric amplifier) ​​→ cryogenic low-noise amplifier → cryogenic transmission line; the room-temperature end consists of: signal transmission line → room-temperature low-noise amplifier → signal processing equipment. Multiple readout buses are used on the quantum chip to read the quantum state information of the qubits. Each readout bus includes the aforementioned readout link, requiring an isolator / JPA, a cryogenic low-noise amplifier, and a room-temperature low-noise amplifier. As the number of qubits on the quantum chip increases significantly, the number of readout links also increases dramatically, as does the number of cryogenic and room-temperature low-noise amplifiers. The cryogenic and room-temperature low-noise amplifiers require a power supply signal during operation, typically provided by a voltage source.

[0003] Existing voltage sources for powering low-temperature and room-temperature low-noise amplifiers, such as the dedicated power supply socket for Swedish LNF, have 8-channel outputs. Their limited number of channels and difficulty in expansion make them unsuitable for the low-noise amplifier power supply requirements of quantum computing measurement and control systems that are compatible with large-scale quantum chips. Summary of the Invention

[0004] The purpose of this application is to solve the problem of the limited number of low-noise discharge power supply voltage source channels in existing quantum measurement and control integrated machines. While significantly increasing the number of channels, the output voltage can also be adjusted according to requirements.

[0005] To solve the above technical problems, the technical solution of this application is as follows:

[0006] The first aspect of this application provides a power supply circuit for a quantum chip readout link, the quantum chip readout link including a first low-noise amplifier in a low-temperature region and a second low-noise amplifier in a room-temperature region connected in series, the power supply circuit including:

[0007] The FPGA module outputs control signals including a first voltage signal, a second voltage signal, and a third voltage signal, representing the target values.

[0008] Several pairs of adjustable voltage output modules and fixed voltage output modules are provided. Each pair of adjustable voltage output modules and fixed voltage output modules is electrically connected to the output control terminal of the FPGA module. The modules are used to output an adjustable first voltage signal and a second voltage signal to the gate and drain of the first low-noise amplifier, and a fixed third voltage signal to the drain of the second low-noise amplifier, according to the target value.

[0009] Optionally, in the power supply circuit of the quantum chip readout link described above, the fixed voltage output module includes:

[0010] Several linear regulated power supplies are each electrically connected to an output control terminal of the FPGA module, and output a third voltage signal to the drain of the second low-noise amplifier according to the target value.

[0011] Several ADC modules measure the third voltage signal and send the measured value to the FPGA module.

[0012] Optionally, in the power supply circuit of the quantum chip readout link described above, the adjustable voltage output module includes:

[0013] Several DAC modules are electrically connected to one output control terminal of the FPGA module, and output a first voltage signal and a second voltage signal to the gate and drain of the first low-noise amplifier respectively according to the target value;

[0014] Each ADC module corresponds to one of the multiple DAC modules. Each ADC module measures the second voltage signal output by the corresponding DAC module to obtain a measured value and sends the measured value to the FPGA module so that the FPGA module adjusts the target value according to the measured value.

[0015] Optionally, in the power supply circuit of the quantum chip readout link described above, the adjustable voltage output module further includes a voltage converter, wherein:

[0016] The positive input terminal of the voltage converter is electrically connected to the output terminal of the DAC module to receive the first voltage signal. The negative input terminal of the voltage converter receives the third voltage signal. The output terminal of the voltage converter outputs the first voltage signal after the current direction is reversed.

[0017] Optionally, the adjustable voltage output module further includes a power-on control unit, one end of which is electrically connected to the output terminal of the voltage converter and the other end of which is electrically connected to the second voltage signal output port, for controlling the output of the first voltage signal and the second voltage signal.

[0018] As described above, the power supply circuit of the quantum chip readout link optionally includes a power-on control unit comprising a diode and a comparator, wherein:

[0019] The diode has one end electrically connected to the output terminal of the voltage converter and the other end electrically connected to an input terminal of the comparator.

[0020] The other input of the comparator receives the second voltage signal and outputs the second voltage signal based on the comparison result between the first voltage signal and the second voltage signal.

[0021] As described above, the power supply circuit of the quantum chip readout link can optionally have a DAC module with a bit width of not less than 12 bits and an ADC module with a bit width of not less than 16 bits.

[0022] As described above, in the power supply circuit of the quantum chip readout link, optionally, the FPGA module, several pairs of adjustable voltage output modules and fixed voltage output modules are all integrated on a PCB board.

[0023] Optionally, the power supply circuit of the quantum chip readout link described above may also include a host computer, which is communicatively connected to the FPGA module and used to send the target value to the FPGA module.

[0024] A second aspect of this application provides a quantum computer, including a quantum chip and a quantum computing measurement and control system. The quantum computing measurement and control system reads the quantum chip through a quantum chip readout link. The low-noise amplifier in the quantum chip readout link is provided with a power supply signal using a power supply circuit of the quantum chip readout link as described in any of the first aspects above.

[0025] Compared with the prior art, this application has the following beneficial effects:

[0026] The power supply circuit of the quantum chip readout link in this application includes an adjustable voltage output section and a fixed voltage output section, both of which are controlled by an FPGA module. The adjustable voltage output section outputs an adjustable first voltage signal and a second voltage signal to the gate and drain of a first low-noise amplifier in a low-temperature environment to ensure its normal operation. The fixed voltage output section outputs a fixed voltage signal to the drain of a second low-noise amplifier in a room-temperature environment to ensure its normal operation. By setting the adjustable voltage output section and the fixed voltage output section in pairs, power signals are provided to the low-temperature low-noise amplifier and the room-temperature low-noise amplifier in each readout link. Multiple sets are set to provide voltage signals to the low-noise amplifiers in more readout links. The voltage signals are adjusted by the voltage signals output by the FPGA module to achieve voltage signal adjustability and match the voltage signal requirements of the low-noise amplifiers in more readout links.

[0027] The quantum computer proposed in this application and the power supply circuit of the quantum chip readout link belong to the same concept and therefore have the same beneficial effects, which will not be elaborated here. Attached Figure Description

[0028] Figure 1 A circuit diagram illustrating the power supply circuit of a quantum chip readout link, as exemplified by an embodiment of this application;

[0029] Figure 2 This is a circuit diagram of an adjustable voltage output module, which is an example of an embodiment of this application. Detailed Implementation

[0030] The specific embodiments of this application will be described in more detail below with reference to the schematic diagrams. The advantages and features of this application will become clearer from the following description and claims. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this application.

[0031] In the description of this application, it should be understood that the terms "center", "upper", "lower", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0032] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0033] A quantum computer comprises a quantum chip, a quantum computing control system, and a control link connecting the quantum chip and the quantum computing control system. The control link includes a control link and a readout link. The readout link incorporates multiple microwave devices, such as a circulator located in a cryogenic environment, a low-noise amplifier (LNA), and a LNA located at room temperature. As an active device, the LNA requires a voltage source signal to ensure its proper operation.

[0034] As the number of qubits on quantum chips increases dramatically, so does the number of readout links, and consequently, the number of cryogenic and room-temperature low-noise amplifiers (LNAs). Furthermore, these LNAs require a power signal to operate, and the power signal required by cryogenic LNAs differs across readout links, while room-temperature LNAs typically require a fixed power signal. In other words, to match quantum chips with more qubits, more cryogenic LNAs and more voltage sources with adjustable power signals are needed to provide the necessary power signals for both cryogenic and room-temperature LNAs.

[0035] like Figure 1 As shown, this embodiment provides a power supply circuit for a quantum chip readout link. The quantum chip readout link includes a first low-noise amplifier in a low-temperature region and a second low-noise amplifier in a room-temperature region connected in series. The power supply circuit includes an FPGA module and several pairs of adjustable voltage output modules and fixed voltage output modules. The FPGA module outputs control signals including a first voltage signal, a second voltage signal, and a third voltage signal with target values. The FPGA module has multiple output control terminals, and each pair of adjustable voltage output modules and fixed voltage output modules is connected to one output control terminal. The FPGA module controls the output of each pair of adjustable voltage output modules and fixed voltage output modules.

[0036] In this embodiment, the low-temperature zone is the temperature zone inside the dilution refrigerator, which may include a 20mk layer located in the same temperature zone as the quantum chip, or a 4K layer, a 1K layer, etc. The room temperature zone is the temperature zone outside the dilution refrigerator, i.e., the room temperature environment.

[0037] Several pairs of adjustable voltage output modules and fixed voltage output modules are provided. Each pair of adjustable voltage output modules and fixed voltage output modules is electrically connected to the output control terminal of the FPGA module. It is used to output an adjustable first voltage signal and a second voltage signal to the gate and drain of the first low noise amplifier, and a fixed third voltage signal to the drain of the second low noise amplifier, according to the target value.

[0038] It should be further described that each readout link includes a low-temperature low-noise amplifier and a room-temperature low-noise amplifier. The gate and drain voltage signals of the low-temperature low-noise amplifier are output by an adjustable voltage output module, while the drain voltage signal of the room-temperature low-noise amplifier is output by a fixed voltage output module. Therefore, the adjustable voltage output module and the fixed voltage output module are paired to provide power signals to the low-noise amplifiers in one readout link. When power signals need to be provided to the low-noise amplifiers in multiple quantum chip readout links, several pairs of adjustable voltage output modules and fixed voltage output modules can be used.

[0039] The power supply circuit of the quantum chip readout link in this application includes an adjustable voltage output section and a fixed voltage output section, both of which are controlled by an FPGA module. The adjustable voltage output section outputs an adjustable first voltage signal and a second voltage signal to the gate and drain of a first low-noise amplifier in a low-temperature environment to ensure its normal operation. The fixed voltage output section outputs a fixed voltage signal to the drain of a second low-noise amplifier in a room-temperature environment to ensure its normal operation. By setting the adjustable voltage output section and the fixed voltage output section in pairs, power signals are provided to the low-temperature low-noise amplifier and the room-temperature low-noise amplifier in each readout link. Multiple sets are set to provide voltage signals to the low-noise amplifiers in more readout links. The voltage signals are adjusted by the voltage signals output by the FPGA module to achieve voltage signal adjustability and match the voltage signal requirements of the low-noise amplifiers in more readout links.

[0040] like Figure 2 As shown, as one embodiment, a circuit diagram of a fixed voltage output module is provided, including: several linear regulated power supplies and several ADC modules; the several linear regulated power supplies are respectively electrically connected to an output control terminal of an FPGA module, and output a third voltage signal to the drain of a second low-noise amplifier according to the target value; the several ADC modules measure the third voltage signal and send the measured value to the FPGA module.

[0041] A third voltage signal with a fixed value is output from a linear regulated power supply to the drain of a second low-noise amplifier at room temperature. The specific value of the third voltage signal can be determined based on the target value output by the FPGA module. Furthermore, an ADC module is used to acquire the output third voltage signal. By comparing the acquired third voltage signal with the target value, it is determined whether the output third voltage signal meets the requirements. If it does not meet the requirements, the target value is adjusted via the FPGA module to ensure that the linear regulated power supply outputs the required third voltage signal.

[0042] like Figure 2 As shown in the diagram, as one embodiment, a circuit diagram of an adjustable voltage output module is provided, including: a plurality of DAC modules and a plurality of ADC modules; the plurality of DAC modules are electrically connected to an output control terminal of an FPGA module respectively, and output a first voltage signal and a second voltage signal to the gate and drain of a first low-noise amplifier according to a target value; the plurality of ADC modules measure the second voltage signal and send the measured value to the FPGA module.

[0043] The system comprises multiple DACs and multiple ADCs, each with a one-to-one correspondence. Each DAC module has multiple output channels, and each ADC module has multiple acquisition channels. The output channels of the DAC modules are used to output voltage signals, while the channels of the ADC modules are used to acquire the voltage signals output by the DAC modules. By comparing the acquired voltage signals with the target values, it is determined whether the output voltage signals meet the requirements.

[0044] The DAC module outputs different voltage signals through its output channels. For example, it outputs a first voltage signal and a second voltage signal to the gate and drain of a low-temperature, low-noise amplifier. When outputting voltage signals, the DAC module outputs them according to the control signals output by the FPGA module, which include the target values ​​of the first and second voltage signals, ensuring that the first and second voltage signals are set as required. By adjusting the target values ​​output by the FPGA module, the adjustability of the first and second voltage signals output by the DAC module can be achieved.

[0045] The FPGA module has multiple output control terminals, and each DAC module is connected to one output control terminal. The FPGA module controls the output of multiple DAC modules. In addition, the FPGA module also has multiple signal input terminals, each of which is connected to an ADC module. The ADC module is used to acquire the second voltage signal output by the corresponding DAC module and send the measured value to the signal input terminal of the FPGA module. The FPGA module then adjusts the target value of the second voltage signal according to the measured value.

[0046] It should be added that, Figure 2 Only two DAC modules and two ADC modules are shown in the example, with four output channels. More outputs can be achieved by expanding the DAC and ADC modules, each controlled by an FPGA module. Taking the power supply circuit of a quantum chip readout link with 40 channels as an example, the ADC chip in this application circuit has the function of simultaneously acquiring and processing 12 analog signals. All 40 channels of voltage output and data acquisition functions can be completed by controlling 40 DAC modules and 4 ADC modules by the FPGA module.

[0047] like Figure 2 As shown, the adjustable voltage output module in the power supply circuit of the quantum chip readout link in this embodiment also includes a voltage converter, wherein: the positive input terminal of the voltage converter is electrically connected to the output terminal of the DAC to receive a first voltage signal, the negative input terminal of the voltage converter receives a third voltage signal, and the output terminal of the voltage converter outputs the first voltage signal after the current direction is converted.

[0048] The first and second voltage signals are output to the gate and drain of the low-noise amplifier to control its operation. In some applications, the gate and drain require voltage signals of different directions, such as positive and negative voltages. In this case, the first and second voltage signals output by the DAC module are in the same direction. A voltage converter is then used, with its positive input connected to the DAC's output, to reverse the current direction of the first voltage signal, outputting a voltage signal with the current direction opposite to the first voltage direction, ensuring the low-noise amplifier meets various application requirements. Furthermore, a third voltage signal is required through its inverting input to ensure the voltage converter functions correctly.

[0049] When a low-noise amplifier is working, its gate and drain are usually powered on simultaneously. When it is turned off, its gate and drain are also powered off simultaneously. When reading the low-noise amplifier in the link, it is necessary to ensure that the gate is powered on first and then the drain is powered on. When they are powered off simultaneously, it is also necessary to ensure that the drain is powered off first and then the gate is powered off.

[0050] Therefore, as Figure 2 As shown, the adjustable voltage output module in the power supply circuit of the quantum chip readout link in this embodiment also includes a power-on control unit, one end of which is electrically connected to the output terminal of the voltage converter, and the other end of which is electrically connected to the second voltage signal output port, for controlling the output of the first voltage signal and the second voltage signal.

[0051] A power-on control unit is used to control the output of the first voltage signal and the second voltage signal to ensure that the power-on timing of the gate and drain meets the requirements of the application scenario.

[0052] For example, the power-on control unit includes a diode and a comparator, wherein: one end of the diode is electrically connected to the output of the voltage converter, and the other end is electrically connected to an input of the comparator; the other input of the comparator receives a second voltage signal and outputs a second voltage signal based on the comparison result of the first voltage signal and the second voltage signal.

[0053] Specifically, the diode is a diode. The first voltage signal output by the DAC module is directly transmitted to the gate, ensuring that the gate is powered on. At the same time, it is also output to one output terminal of the comparator through the diode. The DAC module outputs a second voltage signal to the other input terminal of the comparator. After the comparator compares the first voltage signal and the second voltage signal, it determines that the gate is powered on. Then, it turns on the control switch of the drain output and outputs a second signal to the drain, so that the drain is powered on.

[0054] When powering down, the DAC module can control the order in which it shuts down the first and second voltage signals via control signals sent by the FPGA module. Specifically, the output of the second voltage signal is shut down first, so that the drain is powered down first. After waiting for several seconds, the output of the second voltage signal is shut down, so that the gate is powered down then.

[0055] In this embodiment, a hardware and software collaborative control method is used to realize the power-down sequence of the gate and drain. On the software side, the power-on and power-down sequence in the FPGA control signals is controlled. On the hardware side, a comparator comparison method is used to realize that when powering on, the gate is powered on first, and the drain is powered on after waiting for several seconds, and when powering off, the drain is powered off first, and the gate is powered off after waiting for several seconds, so as to meet the working requirements of the low noise amplifier.

[0056] In addition, the low-noise amplifier has high requirements for the adjustment accuracy of the first and second voltages. To ensure that the requirements are met, the DAC module has a bit depth of no less than 12 bits and the ADC module has a bit depth of no less than 16 bits.

[0057] Specifically, the voltage regulation accuracy is mainly determined by the full-scale output voltage and the number of bits in the DAC module. The smaller the full-scale voltage and the more DAC modules, the higher the voltage regulation accuracy. This design uses a 12-bit AD5025 DAC module with a full-scale voltage of 2.5V. Therefore, the adjustable accuracy is:

[0058] 2.5V / (2^12)=0.0006103515625V<1mV.

[0059] The more bits an ADC module has, the higher its sampling accuracy will be. The ADC module can be selected to achieve the target current adjustment accuracy. In this case, the ADC module selected in the design is the 16-bit ADS114S08B, with a full-scale design of 2.5V.

[0060] Therefore, the designed voltage reading accuracy is:

[0061] 2.5V / (2^16)=0.00003814697265625V.

[0062] By selecting DAC and ADC modules with appropriate bit depths, the adjustment accuracy of the first and second voltage signals is ensured to meet the requirements of the low-noise amplifier.

[0063] Furthermore, this embodiment also includes a sampling resistor, located in the circuit for the second voltage signal. The ADC module is electrically connected across the sampling resistor to sample the second voltage signal. Specifically, the sampling resistor value is 0.01Ω, and the maximum design current is 100mA. Therefore, the voltage variation range across the sampling resistor is 0V to 0.001V. In this embodiment, the current sampling chip is INA285, which, together with an operational amplifier, amplifies the voltage by 2000 times, resulting in a sampling voltage of 0V to 2.0V. Within this range, the design requirements are met.

[0064] The FPGA module, several pairs of adjustable voltage output modules, and a fixed voltage output module are all integrated onto a single PCB board. Furthermore, all other modules and functional components are integrated onto this PCB board, which is then fixedly integrated into the chassis. In this embodiment, at least 40 voltage signal outputs are required, necessitating the use of numerous DAC and ADC modules, all integrated into a 2U chassis.

[0065] Furthermore, the power supply circuit of the quantum chip readout link in this embodiment also includes a host computer, which is communicatively connected to the FPGA module and used to send the target value to the FPGA module. The host computer controls the FPGA module to control the output of the DAC module and the linear regulated power supply, thereby adjusting the voltage values ​​and controlling the power-on sequence of the first, second, and third voltage signals.

[0066] Based on the same concept, this embodiment also provides a quantum computer, including a quantum chip and a quantum computing measurement and control system. The quantum computing measurement and control system reads the quantum chip through a quantum chip readout link. The low-noise amplifier in the quantum chip readout link uses the power supply circuit of the quantum chip readout link described above to provide a power signal.

[0067] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," or "specific example," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0068] The above are merely preferred embodiments of this application and do not constitute any limitation on this application. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in this application without departing from the scope of the technical solutions of this application shall still fall within the protection scope of this application.

Claims

1. A power supply circuit for a quantum chip readout link, characterized in that, The quantum chip readout link includes a first low-noise amplifier in the low-temperature region and a second low-noise amplifier in the room-temperature region connected in series. The power supply circuit includes: The FPGA module outputs control signals including a first voltage signal, a second voltage signal, and a third voltage signal, representing the target values. Several pairs of adjustable voltage output modules and fixed voltage output modules are provided. Each pair of adjustable voltage output modules and fixed voltage output modules is electrically connected to the output control terminal of the FPGA module. The modules are used to output an adjustable first voltage signal and a second voltage signal to the gate and drain of the first low-noise amplifier, and a fixed third voltage signal to the drain of the second low-noise amplifier, according to the target value.

2. The power supply circuit of the quantum chip readout link as described in claim 1, characterized in that, The fixed voltage output module includes: Several linear regulated power supplies are each electrically connected to an output control terminal of the FPGA module, and output a third voltage signal to the drain of the second low-noise amplifier according to the target value. Several ADC modules measure the third voltage signal and send the measured value to the FPGA module.

3. The power supply circuit of the quantum chip readout link as described in claim 1, characterized in that, The adjustable voltage output module includes: Several DAC modules are electrically connected to an output control terminal of the FPGA module, and output a first voltage signal and a second voltage signal to the gate and drain of the first low-noise amplifier respectively according to the target value; Each ADC module corresponds to one of the multiple DAC modules. Each ADC module measures the second voltage signal output by the corresponding DAC module to obtain a measured value and sends the measured value to the FPGA module so that the FPGA module adjusts the target value according to the measured value.

4. The power supply circuit of the quantum chip readout link as described in claim 3, characterized in that, The adjustable voltage output module further includes a voltage converter, wherein: The positive input terminal of the voltage converter is electrically connected to the output terminal of the DAC module to receive the first voltage signal. The negative input terminal of the voltage converter receives the third voltage signal. The output terminal of the voltage converter outputs the first voltage signal after the current direction is reversed.

5. The power supply circuit for the quantum chip readout link as described in claim 4, characterized in that, The adjustable voltage output module also includes a power-on control unit, one end of which is electrically connected to the output terminal of the voltage converter, and the other end of which is electrically connected to the second voltage signal output port, for controlling the output of the first voltage signal and the second voltage signal.

6. The power supply circuit for the quantum chip readout link as described in claim 5, characterized in that, The power-on control unit includes diodes and comparators, wherein: The diode has one end electrically connected to the output terminal of the voltage converter and the other end electrically connected to an input terminal of the comparator. The other input of the comparator receives the second voltage signal and outputs the second voltage signal based on the comparison result between the first voltage signal and the second voltage signal.

7. The power supply circuit for the quantum chip readout link as described in claim 3, characterized in that, The DAC module has a minimum of 12 bits, and the ADC module has a minimum of 16 bits.

8. The power supply circuit of the quantum chip readout link as described in claim 1, characterized in that, The FPGA module, several pairs of adjustable voltage output modules, and fixed voltage output modules are all integrated on a PCB board.

9. The power supply circuit of the quantum chip readout link as described in claim 1, characterized in that, It also includes a host computer, which is connected to the FPGA module for sending target values ​​to the FPGA module.

10. A quantum computer, characterized in that, The system includes a quantum chip and a quantum computing measurement and control system. The quantum computing measurement and control system reads the quantum chip through a quantum chip readout link. The low-noise amplifier in the quantum chip readout link is powered by a power supply circuit as described in any one of claims 1-9.

Images