A supercapacitor charge and discharge monitoring and control circuit

Abstract

This utility model discloses a supercapacitor charging and discharging monitoring and control circuit, comprising: a first power conversion circuit that converts an external power supply into a first output voltage and a second output voltage; a second power conversion circuit that converts the second output voltage into a third output voltage; an external power supply failure detection circuit for outputting a high or low level, the external power supply failure detection circuit being electrically connected to the output terminal of the first power conversion circuit, and the external power supply failure detection circuit also having an input terminal for connecting an external power supply; and a control circuit for controlling the supercapacitor charging and discharging circuit, the first input terminal of the control circuit being electrically connected to the output terminal of the external power supply failure detection circuit, and the second and third input terminals of the control circuit being electrically connected to the output terminal of the supercapacitor charging and discharging circuit. This utility model can ensure that power can be supplied to the load through the supercapacitor even in the event of a mains power failure.

Description

Technical Field

[0001] This utility model relates to the field of substation insulation performance monitoring, and in particular to a supercapacitor charging and discharging monitoring and control circuit. Background Technology

[0002] With the increasing application of IoT and automation technologies, real-time data acquisition, uploading, and storage in industrial settings are crucial, as this data is primarily used to monitor the operating conditions of industrial equipment and analyze product performance trends. Therefore, ensuring the accurate storage of data collected by industrial control acquisition devices is a primary concern, especially when these devices require external power. A sudden power outage can lead to data loss and even damage to the software system of the acquisition device, a critical problem in industrial production lines. Thus, adding backup batteries to industrial control acquisition devices has become essential. Ensuring that industrial control acquisition devices can continue operating stably for a period after a power outage, providing sufficient time for the software system to cache and save data, is a growing challenge that engineers are considering and need to solve.

[0003] Existing backup batteries for industrial control data acquisition equipment are either lithium batteries or supercapacitors, each with its own advantages and disadvantages. Supercapacitors, however, have gained widespread use due to their fast charging, long lifespan, rapid discharge, non-combustible nature, and environmental friendliness. However, the low energy density of supercapacitors makes efficient energy utilization challenging. This is because it's necessary to ensure both full energy utilization and that the discharge voltage and current meet the requirements for stable operation and maintenance of the industrial control data acquisition equipment for a certain duration. Currently, there are two technical solutions:

[0004] One approach is to allow the supercapacitor to discharge continuously until all its energy is depleted. The drawback of this method is that while the supercapacitor continues to discharge, if the discharge voltage falls below the lower limit of the PMIC (Power Management IC, which integrates multiple power supply functions into a single chip to achieve high-efficiency, low-power power solutions) operating voltage of 3.8V, the SOC (System on Chip, which integrates CPU, GPU, memory, peripheral interfaces, and other modules onto a single chip, offering advantages such as high performance and low power consumption) may operate in an abnormal state.

[0005] Secondly, the supercapacitor is discharged to the PMIC operating voltage of 3.8V, forcibly shutting off the power. The disadvantage of this method is that the supercapacitor's energy is not fully utilized when it is discharged from 5V to 3.8V and then forcibly shut off, resulting in energy waste. Utility Model Content

[0006] This invention provides a supercapacitor charging and discharging monitoring and control circuit, which can ensure that the supercapacitor can still supply power to the load when the mains power is interrupted.

[0007] The technical solutions to the above technical problems are as follows:

[0008] A supercapacitor charge / discharge monitoring and control circuit includes:

[0009] A first power conversion circuit that converts an external power supply into a first output voltage and a second output voltage;

[0010] A second power conversion circuit converts the second output voltage into a third output voltage, and the second power conversion circuit is electrically connected to the first power conversion circuit.

[0011] Supercapacitor charging and discharging circuit; also includes:

[0012] An external power supply failure detection circuit is used to output a high or low level. The external power supply failure detection circuit is electrically connected to the output terminal of the first power conversion circuit. The external power supply failure detection circuit also has an input terminal for connecting an external power supply.

[0013] The control circuit for controlling the charging and discharging circuit of the supercapacitor has a first input terminal, a second input terminal, and a third input terminal. The first input terminal of the control circuit is electrically connected to the output terminal of the external power supply failure detection circuit, and the second and third input terminals of the control circuit are both electrically connected to the output terminal of the supercapacitor charging and discharging circuit.

[0014] This utility model has the following advantages:

[0015] This invention enables precise control of the charging and discharging timing of the supercapacitor through hardware, making full and effective use of the supercapacitor's electrical energy. In specific applications, it maximizes the usability of the supercapacitor, ensuring that the SOC system can operate normally and stably using the supercapacitor even when the external power supply is interrupted. No software intervention is required, and it also allows the SOC sufficient time to save data. Attached Figure Description

[0016] Figure 1 This is the circuit schematic of the first power conversion circuit.

[0017] Figure 2 This is the circuit schematic of the second power conversion circuit.

[0018] Figure 3 The circuit diagram of the external power supply failure detection circuit.

[0019] Figure 4This is the circuit schematic for the control circuit.

[0020] Figure 5 The circuit diagram for charging and discharging a supercapacitor. Detailed Implementation

[0021] like Figures 1 to 5 This utility model discloses a supercapacitor charging and discharging monitoring and control circuit, which includes a first power conversion circuit A, a second power conversion circuit B, an external power supply failure detection circuit C, a control circuit D, and a supercapacitor charging and discharging circuit E. The following is a detailed description of each part and the relationship between them.

[0022] The first power conversion circuit A converts the external power supply VVC_+24V into a first output voltage VDD_5V_SOM and a second output voltage VCC_5V. The first power conversion circuit A includes a first conversion unit, a filter energy storage unit, and a rectifier unit D8. The first conversion unit is connected to the filter energy storage unit, and the filter energy storage unit is connected to the rectifier unit D8.

[0023] The first conversion unit is used to connect to the external power supply VVC_+24V. The first conversion unit includes a third capacitor C3, a fourth capacitor C4, a fourth resistor R4, a sixth resistor R6, a third diode D3, a first power conversion chip U1, and a second capacitor C2. The first power conversion chip U1 is preferably a DC-DC conversion chip. One end of the third capacitor C3, the fourth capacitor C4, the fourth resistor R4, and the seventh pin of the first power conversion chip U1 are all used to connect to the external power supply VVC_+24V. The other end of the third capacitor C3 and the fourth capacitor C4 are grounded. One end of the sixth resistor R6 is connected to the other end of the fourth resistor R4, and the other end of the sixth resistor R6 is grounded. The fifth pin of the first power conversion chip U1 is connected to the sixth resistor R6 and one end of the third diode D3, respectively. The other end of the third diode D3 is grounded. One end of the second capacitor C2 is connected to the eighth pin of the first power conversion chip U1, and the other end of the second capacitor C2 is connected to the first pin of the first power conversion chip U1. The sixth and ninth pins of the first power conversion chip U1 are both grounded.

[0024] The filtering energy storage unit is used to output the first output voltage VDD_5V_SOM. The output terminal of the first conversion unit is electrically connected to the filtering energy storage unit. The filtering energy storage unit includes a first inductor L1, a second diode D2, a fifth resistor R5, an eighth resistor R8, a first capacitor C1, a sixth capacitor C6, an eighth capacitor C8, a fifth capacitor C5, and a seventeenth diode D17. One end of the first inductor L1 and the second diode D2 is electrically connected to the first conversion unit. One end of the first inductor L1 and the second diode D2 is preferably connected to one end of the second capacitor C2. One end of the fifth resistor R5, the first capacitor C1, the sixth capacitor C6, the eighth capacitor C8, the fifth capacitor C5, and the seventeenth diode D17 are all connected to the other end of the first inductor L1. The other end of the fifth resistor R5 is connected to the first conversion unit and one end of the eighth resistor R8. The other ends of the eighth resistor R8, the first capacitor C1, the sixth capacitor C6, the eighth capacitor C8, the fifth capacitor C5, and the seventeenth diode D17 are all grounded. In this invention, the fourth pin of the first power conversion chip U1 in the first conversion unit is preferentially connected to the other end of the fifth resistor R5.

[0025] In this embodiment, the first capacitor C1 and the fifth capacitor C5 are mainly used for energy storage, the sixth capacitor C6 and the eighth capacitor C8 are mainly used for filtering, and the seventeenth diode D17 is preferably a TVS diode.

[0026] The rectifier unit D8 is used to output the second output voltage VCC_5V. The rectifier unit D8 is connected to the output terminal of the filter energy storage unit. In this utility model, the end of the first capacitor C1, the sixth capacitor C6, the eighth capacitor C8, the fifth capacitor C5, and the seventeenth diode D17 connected in parallel is the output terminal of the filter energy storage unit. The rectifier unit D8 preferably uses a Schottky diode.

[0027] The second power conversion circuit B converts the second output voltage VCC_5V to the third output voltage VCC_3V3. The input terminal of the second power conversion circuit B is electrically connected to the output terminal of the first power conversion circuit A, which outputs the second output voltage VCC_5V. The second power conversion circuit B includes a 35th capacitor C35, a 37th capacitor C37, a 38th capacitor C38, a 27th resistor C27, a second power conversion chip U2, a 34th capacitor C34, a 5th inductor L5, a 28th resistor R28, a 29th resistor R29, a 39th capacitor C39, a 40th capacitor C40, and a 36th capacitor C36.

[0028] One end of the 35th capacitor C35, the 37th capacitor C37, the 38th capacitor C38, the 27th resistor C27, and the third pin of the second power conversion chip U2 are all connected to the output terminal of the first power conversion circuit A. The other end of the 35th capacitor C35, the 37th capacitor C37, and the 38th capacitor C38 is grounded. The other end of the 27th resistor C27 is electrically connected to the fifth pin of the second power conversion chip U2. The first pin of the second power conversion chip U2 is grounded.

[0029] The second pin of the second power conversion chip U2 and one end of the fifth inductor L5 are both connected to one end of the thirty-fourth capacitor C34. The other end of the thirty-fourth capacitor C34 is connected to the sixth pin of the second power conversion chip U2. The other end of the fifth inductor L5 is connected to one end of the fortieth capacitor C40 and the thirty-sixth capacitor C36, respectively. One end of the twenty-eighth resistor R28 and the twenty-ninth resistor R29 are both connected to the fourth pin of the second power conversion chip U2. The other end of the twenty-eighth resistor R28 is connected to one end of the thirty-ninth capacitor C39 and the fortieth capacitor C40, respectively. The other ends of the twenty-ninth resistor R29, the thirty-ninth capacitor C39, the fortieth capacitor C40, and the thirty-sixth capacitor C36 are grounded.

[0030] The external power supply failure detection circuit C is used to output a high level or a low level. The external power supply failure detection circuit C is electrically connected to the output terminal of the first power conversion circuit A. The external power supply failure detection circuit C also has an input terminal for connecting the external power supply VVC_+24V.

[0031] The external power supply failure detection circuit C includes a voltage reference chip U5, a seventh capacitor C7, a fifteenth resistor R15, a comparator U6, a twentieth resistor R20, a fifteenth diode D15, a twenty-first resistor R21, a twenty-second resistor R22, a seventh diode D7, a nineteenth resistor R19, a twenty-fifth capacitor C25, and a twenty-fourth capacitor C24. The first pin of the voltage reference chip U5 is connected to the output terminal of the first power conversion circuit A. Preferably, the first pin of the voltage reference chip U5 is electrically connected to the output terminal of the first power conversion circuit A, which outputs the second output voltage VCC_5V. The second pin of the voltage reference chip U5 is connected to one end of the seventh capacitor C7 and the fifteenth resistor R15. The third pin of the voltage reference chip U5 and the other end of the seventh capacitor C7 are grounded. The other end of the fifteenth resistor R15 is connected to the third pin of the comparator U6.

[0032] One end of the twentieth resistor R20 is used to connect to the external power supply VVC_+24V. The other end of the twentieth resistor R20 is connected to the fifteenth diode D15, one end of the twenty-first resistor R21, and the first pin of comparator U6. One end of the twenty-second resistor R22 is connected to the other end of the twenty-first resistor R21. The other end of the fifteenth diode D15, the twenty-second resistor R22, and the second pin of comparator U6 are grounded.

[0033] One end of the seventh diode D7 is connected to the fourth pin of comparator U6. The seventh diode D7 is also connected to one end of the nineteenth resistor R19 and the twenty-fifth capacitor C25. The other end of the nineteenth resistor R19 is connected to the output of the second power conversion circuit B. The other end of the twenty-fifth capacitor C25 is grounded. One end of the twenty-fourth capacitor C24 and the fifth pin of comparator U6 are electrically connected to the output of the second output voltage VCC_5V from the first power conversion circuit A. The other end of the twenty-fourth capacitor C24 is grounded.

[0034] The control circuit D is used to control the supercapacitor charging and discharging circuit E. The control circuit D has a first input terminal, a second input terminal, and a third input terminal. The first input terminal of the control circuit D is electrically connected to the output terminal CAP_TS of the external power supply failure detection circuit C. The second and third input terminals of the control circuit D are both electrically connected to the output terminal VDC_5V of the supercapacitor charging and discharging circuit E.

[0035] The control circuit D includes a boost unit, a switching unit, and a voltage monitoring unit for controlling the switching unit to turn on or off. The second input terminal and the third input terminal are located in the boost unit, which is connected to the switching unit. The third input terminal is located in the voltage monitoring unit, which is connected to the switching unit.

[0036] The boost unit includes a boost control chip U4, a second inductor L2, a fourth diode D4, a forty-eighth resistor R48, a tenth capacitor C10, a seventy-eighth capacitor C78, ​​a tenth resistor R10, a twelfth resistor R12, a ninety-first capacitor C91, and a ninety-second capacitor C92. One end of the tenth capacitor C10 and the seventy-eighth capacitor C78, ​​the fifth pin of the boost control chip U4, and one end of the second inductor L2 are all connected to the output terminal VDC_5V of the supercapacitor charging and discharging circuit E. The other ends of the tenth capacitor C10 and the seventy-eighth capacitor C78 are grounded. One end of the forty-eighth resistor R48 is electrically connected to the output terminal CAP_TS of the external power supply failure detection circuit C, and the other end of the forty-eighth resistor R48 is connected to the fourth pin of the boost control chip U4.

[0037] The first pin of the boost control chip U4 and the other end of the second inductor L2 are both connected to one end of the fourth diode D4. The other end of the fourth diode D4 is connected to the input terminal of the switching unit. One end of the tenth resistor R10 and the twelfth resistor R12 are both connected to the third pin of the boost control chip U4. The other end of the tenth resistor R10, one end of the ninety-first capacitor C91, and one end of the ninety-second capacitor C92 are all connected to the other end of the fourth diode D4. The other ends of the twelfth resistor R12, the ninety-first capacitor C91, the ninety-second capacitor C92, and the second pin of the boost control chip U4 are all grounded.

[0038] The switching unit is a MOSFET Q4. The source of MOSFET Q4 is connected to the other end of the fourth diode D4, and the gate of MOSFET Q4 is electrically connected to the voltage monitoring unit.

[0039] The voltage monitoring unit includes the seventy-seventh capacitor C77, the voltage monitoring chip U3, the forty-fifth resistor R45, the forty-seventh resistor R47, the fifth transistor Q5, the thirty-first capacitor C31, and the forty-fourth resistor R44.

[0040] One end of the 77th capacitor C77 and the third pin of the voltage monitoring chip U3 are connected to the output terminal VDC_5V of the supercapacitor charging and discharging circuit E, and the other end of the 77th capacitor C77 is grounded. The second pin of the voltage monitoring chip U3 is connected to one end of the 45th resistor R45. The other end of the 45th resistor R45 and one end of the 47th resistor R47 are connected to the base of the fifth transistor Q5. The other end of the 47th resistor R47, the emitter of the fifth transistor Q5, and one end of the 31st capacitor C31 are grounded. The other end of the 31st capacitor C31 is connected to the collector of the fifth transistor Q5. The collector of the fifth transistor Q5 is also connected to one end of the 44th resistor R44 and the switching unit. The other end of the 44th resistor R44 is connected to the switching unit. In this embodiment, the other end of the 44th resistor R44 is connected to the source of the MOSFET Q4.

[0041] The control circuit D also includes a rectification and filtering unit, which includes a fifth diode D5, an eleventh capacitor C11, a twelfth capacitor C12, a thirteenth capacitor C13, and a fourteenth capacitor C14. One end of the fifth diode D5 is connected to the output terminal of the switching unit. In this embodiment, the drain of the MOS transistor Q4 is connected to one end of the fifth diode D5. One end of each of the eleventh capacitor C11, the twelfth capacitor C12, the thirteenth capacitor C13, and the fourteenth capacitor C14 is connected to the other end of the fifth diode D5. The end of the eleventh capacitor C11, the twelfth capacitor C12, the thirteenth capacitor C13, and the fourteenth capacitor C14 connected in parallel is the output terminal of the control circuit D. The other ends of the eleventh capacitor C11, the twelfth capacitor C12, the thirteenth capacitor C13, and the fourteenth capacitor C14 are grounded.

[0042] The supercapacitor charging and discharging circuit E includes a first diode D1, a second resistor R2, a forty-sixth resistor R46, an eleventh resistor R11, a first supercapacitor CB1, a second supercapacitor CB2, a third supercapacitor CB3, a sixty-fifth capacitor C65, and a sixty-sixth capacitor C66. One end of the first diode D1 is connected to the output terminal of the first power conversion circuit A, which outputs the first output voltage VDD_5V_SOM. One end of the second resistor R2 is connected to the other end of the first diode D1. The forty-sixth resistor R46 and the eleventh resistor R11 are connected in parallel with the second resistor R2. The other end of the second resistor R2 is connected to one end of the first supercapacitor CB1, the second supercapacitor CB2, the third supercapacitor CB3, the sixty-fifth capacitor C65, and the sixty-sixth capacitor C66, respectively. The other ends of the first supercapacitor CB1, the second supercapacitor CB2, the third supercapacitor CB3, the sixty-fifth capacitor C65, and the sixty-sixth capacitor C66 are grounded.

[0043] The working process of this utility model is as follows:

[0044] S1, the external 24V power supply is converted by the first power conversion chip U1 and then filtered by the filter energy storage unit to obtain the first output voltage VDD_5V_SOM. The first output voltage VDD_5V_SOM is rectified by the rectifier unit D8 to obtain the second output voltage VCC_5V.

[0045] S2, the second power conversion circuit B obtains the second output voltage VCC_5V and provides it to the second power conversion chip U2 after filtering by the thirty-fifth capacitor C35, the thirty-seventh capacitor C37, and the thirty-eighth capacitor C38. The voltage after conversion by the second power conversion chip U2 is filtered by the thirty-sixth capacitor C36 to obtain the third output voltage VCC_3V3.

[0046] S3, Case 1: If the external 24V power supply is in operation, the second output voltage VCC_5V is converted into a 2.5V reference voltage by the voltage reference chip U5. This 2.5V reference voltage is input into comparator U6 through the third pin. The external 24V voltage is divided by resistors R20, R20, R22 and R22 to a voltage of 3.4V. This voltage is then input into comparator U6 through the first pin. Comparator U6 compares the 2.5V and 3.4V voltages and finally outputs a low level from the fourth pin. This low level is output from the output terminal CAP_TS of the external power supply failure detection circuit C.

[0047] Scenario 2: If the external 24V power supply is off, since the first capacitor C1 and the fifth capacitor C5 are energy storage capacitors, the second output voltage VCC_5V will not immediately become 0V. The second output voltage VCC_5V is converted into a 2.5V reference voltage by the voltage reference chip U5. This 2.5V reference voltage is input into comparator U6 through the third pin. Since the external 24V power supply is off at this time, the voltage across the twentieth resistor R20, the twenty-first resistor R21, and the twenty-second resistor R22 is 0V. This 0V voltage is input into comparator U6 through the first pin. After comparing the 2.5V voltage and the 0V voltage, comparator U6 finally outputs a high level from the fourth pin. This high level is output from the output terminal CAP_TS of the external power supply off detection circuit C.

[0048] S4, Case 1: When the external 24V power supply is in operation, the output terminal CAP_TS of the external power supply failure detection circuit C is low, and the enable signal provided by the external power supply failure detection circuit C to the boost control chip U4 is low. Therefore, the boost control chip U4 is in the off state, meaning it will not boost the output voltage VDC_5V of the supercapacitor charging / discharging circuit E. Since the first output voltage VDD_5V_SOM is not 0V when the external 24V power supply is in operation, the first output voltage VDD_5V_SOM, after passing through the parallel branch of the first diode D1 and the second resistor R2, the forty-sixth resistor R46, and the eleventh resistor R11, is applied to the first supercapacitor CB1, the second supercapacitor CB2, and the third supercapacitor CB3, continuously charging them. The first supercapacitor CB1, the second supercapacitor CB2, and the third supercapacitor CB3 will not discharge externally. Simultaneously, the first output voltage VDD_5V_SOM, after passing through the first diode D1 and the second resistor R11, is applied to the first supercapacitor CB1, the second supercapacitor CB2, and the third supercapacitor CB3. 2. The voltage at the output terminal VDC_5V of the supercapacitor charging and discharging circuit E after the parallel branch of resistors R46 (46th) and R11 (11th) is ≥2.6V. Therefore, the voltage monitoring chip U3 outputs a high level. This high level turns on transistor Q5 (5th), which in turn turns on MOSFET Q4. The voltage output from the output terminal VDC_5V of the supercapacitor charging and discharging circuit E passes through the second inductor L2, the fourth diode D4, the MOSFET Q4, and the fifth diode D5 in sequence. The final voltage is definitely less than the second output voltage VCC_5V of the first power conversion circuit A. Therefore, the load (PMIC) is powered by the output terminal of the second output voltage VCC_5V of the first power conversion circuit A.

[0049] Scenario 2: If the external 24V power supply is off, the output terminal CAP_TS of the external power supply failure detection circuit C is high, and the enable signal provided by the external power supply failure detection circuit C to the boost control chip U4 is also high, causing the boost control chip U4 to be in the conducting state. Since the first output voltage VDD_5V_SOM is 0V when the external 24V power supply is off, no external voltage is applied to the first supercapacitor CB1, the second supercapacitor CB2, and the third supercapacitor CB3. Therefore, without external power supply, the first supercapacitor CB1, the second supercapacitor CB2, and the third supercapacitor CB3 discharge. The voltage released by the first supercapacitor CB1, the second supercapacitor CB2, and the third supercapacitor CB3 is provided to the second and third input terminals of the control circuit D through the output terminal VDC_5V of the supercapacitor charging and discharging circuit E. Since the boost control chip U4 is in the conducting state, the boost control chip U4 boosts the output voltage VDC_5V of the supercapacitor charging and discharging circuit E to 5.27V. Since the voltage monitoring chip U3 outputs a high level after obtaining a high level, this high level turns on the fifth transistor Q5, which in turn drives the MOSFET Q4 to turn on. Therefore, the 5.27V voltage is finally output to the load as VCC_5V after passing through the MOSFET Q4 and the fifth diode D5.

Claims

1. A supercapacitor charge / discharge monitoring and control circuit, comprising: A first power conversion circuit (A) converts an external power supply (VVC_+24V) into a first output voltage (VDD_5V_SOM) and a second output voltage (VCC_5V). The second power conversion circuit (B) converts the second output voltage (VCC_5V) to the third output voltage (VCC_3V3), and the second power conversion circuit (B) is electrically connected to the first power conversion circuit (A); A supercapacitor charging and discharging circuit (E); characterized in that it further includes: An external power supply failure detection circuit (C) is used to output a high or low level. The external power supply failure detection circuit (C) is electrically connected to the output terminal of the first power conversion circuit (A). The external power supply failure detection circuit (C) also has an input terminal for connecting an external power supply (VVC_+24V). The control circuit (D) is used to control the supercapacitor charging and discharging circuit (E). The control circuit (D) has a first input terminal, a second input terminal, and a third input terminal. The first input terminal of the control circuit (D) is electrically connected to the output terminal of the external power supply failure detection circuit (C). The second and third input terminals of the control circuit (D) are both electrically connected to the output terminal of the supercapacitor charging and discharging circuit (E).

2. The super capacitor charge and discharge monitoring control circuit according to claim 1, wherein, The first power conversion circuit (A) includes a first conversion unit for connecting to an external power supply (VVC_+24V); A filter energy storage unit is used to output the first output voltage (VDD_5V_SOM), and the output terminal of the first conversion unit is electrically connected to the filter energy storage unit. The rectifier unit (D8) is used to output the second output voltage (VCC_5V), and the rectifier unit (D8) is connected to the output terminal of the filter energy storage unit.

3. The super capacitor charge and discharge monitoring control circuit according to claim 2, wherein, The first conversion unit includes a third capacitor (C3), a fourth capacitor (C4), a fourth resistor (R4), a sixth resistor (R6), a third diode (D3), a first power conversion chip (U1), and a second capacitor (C2). One end of the third capacitor (C3), the fourth capacitor (C4), and the fourth resistor (R4), as well as the seventh pin of the first power conversion chip (U1), are used to connect to the external power supply (VVC_+24V). The other ends of the third capacitor (C3) and the fourth capacitor (C4) are grounded. One end of the sixth resistor (R6) is connected to the other end of the fourth resistor (R4), and the other end of the sixth resistor (R6) is grounded. The fifth pin of the first power conversion chip (U1) is connected to one end of the sixth resistor (R6) and the third diode (D3), respectively. The other end of the third diode (D3) is grounded. One end of the second capacitor (C2) is connected to the eighth pin of the first power conversion chip (U1), and the other end of the second capacitor (C2) is connected to the first pin of the first power conversion chip (U1).

4. The super capacitor charge and discharge monitoring control circuit according to claim 2, wherein, The filter energy storage unit includes a first inductor (L1), a second diode (D2), a fifth resistor (R5), an eighth resistor (R8), a first capacitor (C1), a sixth capacitor (C6), an eighth capacitor (C8), a fifth capacitor (C5), and a seventeenth diode (D17). One end of the first inductor (L1) and the second diode (D2) are electrically connected to the first conversion unit, and one end of the fifth resistor (R5), the first capacitor (C1), the sixth capacitor (C6), the eighth capacitor (C8), the fifth capacitor (C5), and the seventeenth diode (D17) are all connected to the other end of the first inductor (L1). The other end of the fifth resistor (R5) is connected to one end of the first conversion unit and one end of the eighth resistor (R8). The other ends of the eighth resistor (R8), the first capacitor (C1), the sixth capacitor (C6), the eighth capacitor (C8), the fifth capacitor (C5), and the seventeenth diode (D17) are all grounded.

5. The super capacitor charge and discharge monitoring control circuit according to claim 1, wherein, The external power supply failure detection circuit (C) includes a voltage reference chip (U5), a seventh capacitor (C7), a fifteenth resistor (R15), a comparator (U6), a twentieth resistor (R20), a fifteenth diode (D15), a twenty-first resistor (R21), a twenty-second resistor (R22), a seventh diode (D7), a nineteenth resistor (R19), and a twenty-fifth capacitor (C25). The first pin of the voltage reference chip (U5) is connected to the output of the first power conversion circuit (A). The second pin of the voltage reference chip (U5) is connected to one end of the seventh capacitor (C7) and the fifteenth resistor (R15) respectively. The third pin of the voltage reference chip (U5) and the other end of the seventh capacitor (C7) are grounded. The other end of the fifteenth resistor (R15) is connected to the third pin of the comparator (U6). One end of the twentieth resistor (R20) is used to connect to the external power supply (VVC_+24V). The other end of the twentieth resistor (R20) is connected to the fifteenth diode (D15), one end of the twenty-first resistor (R21), and the first pin of the comparator (U6). One end of the twenty-second resistor (R22) is connected to the other end of the twenty-first resistor (R21). The other end of the fifteenth diode (D15), the twenty-second resistor (R22), and the second pin of the comparator (U6) are grounded. One end of the seventh diode (D7) is connected to the fourth pin of the comparator (U6). The seventh diode (D7) is connected to one end of the nineteenth resistor (R19) and the twenty-fifth capacitor (C25). The other end of the nineteenth resistor (R19) is connected to the output of the second power conversion circuit (B). The other end of the twenty-fifth capacitor (C25) is grounded.

6. The super capacitor charge and discharge monitoring control circuit according to claim 1, wherein, The control circuit (D) includes: A boost unit, wherein the second input terminal and the third input terminal are disposed in the boost unit; Switching unit, which is connected to boost unit; A voltage monitoring unit for controlling the switching unit to turn on or off, wherein the third input terminal is disposed in the voltage monitoring unit and the voltage monitoring unit is connected to the switching unit.

7. The super capacitor charge and discharge monitoring control circuit according to claim 6, wherein, The boost unit includes a boost control chip (U4), a second inductor (L2), a fourth diode (D4), and a forty-eighth resistor (R48). The fifth pin of the boost control chip (U4) and one end of the second inductor (L2) are connected to the output of the supercapacitor charging and discharging circuit (E); One end of the forty-eighth resistor (R48) is electrically connected to the output terminal of the external power supply failure detection circuit (C), and the other end of the forty-eighth resistor (R48) is connected to the fourth pin of the boost control chip (U4). The first pin of the boost control chip (U4) and the other end of the second inductor (L2) are both connected to one end of the fourth diode (D4), and the other end of the fourth diode (D4) is connected to the input terminal of the switching unit.

8. The super capacitor charge and discharge monitoring control circuit according to claim 6, wherein, The voltage monitoring unit includes a voltage monitoring chip (U3), a 45th resistor (R45), a 47th resistor (R47), a 5th transistor (Q5), a 31st capacitor (C31), and a 44th resistor (R44). The third pin of the voltage monitoring chip (U3) is connected to the output terminal of the supercapacitor charging and discharging circuit (E). The second pin of the voltage monitoring chip (U3) is connected to one end of the forty-fifth resistor (R45). The other end of the forty-fifth resistor (R45) and one end of the forty-seventh resistor (R47) are connected to the base of the fifth transistor (Q5). The other end of the forty-seventh resistor (R47), the emitter of the fifth transistor (Q5), and one end of the thirty-first capacitor (C31) are grounded. The other end of the thirty-first capacitor (C31) is connected to the collector of the fifth transistor (Q5). The collector of the fifth transistor (Q5) is also connected to one end of the forty-fourth resistor (R44) and the switching unit. The other end of the forty-fourth resistor (R44) is connected to the switching unit.

9. The super capacitor charge and discharge monitoring control circuit according to claim 6, wherein, The control circuit (D) also includes a rectifier and filter unit, which includes a fifth diode (D5), an eleventh capacitor (C11), a twelfth capacitor (C12), a thirteenth capacitor (C13), and a fourteenth capacitor (C14). One end of the fifth diode (D5) is connected to the output terminal of the switching unit, and one end of each of the eleventh capacitor (C11), twelfth capacitor (C12), thirteenth capacitor (C13), and fourteenth capacitor (C14) is connected to the other end of the fifth diode (D5). The other ends of the eleventh capacitor (C11), twelfth capacitor (C12), thirteenth capacitor (C13), and fourteenth capacitor (C14) are grounded.

10. The super capacitor charge and discharge monitoring control circuit according to claim 1, wherein, The supercapacitor charging and discharging circuit (E) includes a first diode (D1), a second resistor (R2), a forty-sixth resistor (R46), an eleventh resistor (R11), a first supercapacitor (CB1), a second supercapacitor (CB2), a third supercapacitor (CB3), a sixty-fifth capacitor (C65), and a sixty-sixth capacitor (C66). One end of the first diode (D1) is connected to the output terminal of the first power conversion circuit (A) which outputs the first output voltage (VDD_5V_SOM). One end of the second resistor (R2) is connected to the first diode (D1). The other end is connected, and the forty-sixth resistor (R46) and the eleventh resistor (R11) are connected in parallel with the second resistor (R2). The other end of the second resistor (R2) is connected to one end of the first supercapacitor (CB1), the second supercapacitor (CB2), the third supercapacitor (CB3), the sixty-fifth capacitor (C65), and the sixty-sixth capacitor (C66). The other end of the first supercapacitor (CB1), the second supercapacitor (CB2), the third supercapacitor (CB3), the sixty-fifth capacitor (C65), and the sixty-sixth capacitor (C66) is grounded.

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