A power device PWM dead zone protection circuit
By combining upper and lower bridge interlocking, software dead time, and hardware dead time in the half-bridge drive circuit, a symmetrical hardware dead time delay is formed, which solves the problem of bridge arm shoot-through short circuit in the prior art, achieves stronger dead time protection, and avoids circuit damage.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- SHENZHEN ESPIRIT TECH
- Filing Date
- 2025-05-13
- Publication Date
- 2026-07-03
Smart Images
Figure CN224459654U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to a half-bridge power device drive circuit, and more particularly to a power device PWM dead-time protection circuit. Background Technology
[0002] In the existing technology, the half-bridge drive circuit of power devices needs to be equipped with dead-time protection measures to prevent the bridge arm of the power device from being shot-through short-circuited. The common half-bridge drive method is upper and lower bridge interlock + software dead time. Under this drive method, once the software fails, the gate charge of the power device will increase, and the upper and lower bridge interlock circuit will still have an instantaneous bridge arm shot-through short-circuit phenomenon. This phenomenon can easily cause serious damage to the circuit. Utility Model Content
[0003] The technical problem to be solved by this utility model is to provide a PWM dead-time protection circuit that can enhance the dead-time protection function and avoid the short circuit of the bridge arm of the power device, in order to address the shortcomings of the existing technology.
[0004] To solve the above-mentioned technical problems, the present invention adopts the following technical solution.
[0005] A PWM dead-time protection circuit for a power device includes a gate driver chip U6, diodes D51 and D53, resistors R67, R69, R72, and R73, capacitors C129 and C140. The first terminal of resistor R69 is connected to the upper bridge drive signal PWM_H, and the second terminal of resistor R69 is connected to the anode of diode D51. The cathode of diode D51 is connected to the upper bridge input terminal IN+ of the gate driver chip U6. Resistor R67 is connected to the first terminal of resistor R69 and... Between the cathodes of diode D51, capacitor C129 is connected between the cathode of diode D51 and ground, the first end of resistor R73 is used to connect the lower bridge drive signal PWM_L, the second end of resistor R73 is connected to the anode of diode D53, the cathode of diode D53 is connected to the lower bridge input terminal IN- of gate driver chip U6, resistor R72 is connected between the first end of resistor R73 and the cathode of diode D53, and capacitor C140 is connected between the cathode of diode D53 and ground.
[0006] Preferably, resistors R67, R69, R72, and R73 are all resistors with a resistance of 1KΩ.
[0007] Preferably, both capacitor C129 and capacitor C140 are capacitors with a capacitance of 3.3nF.
[0008] Preferably, it includes a capacitor C147, which is connected between the power supply terminal of the gate driver chip U6 and ground.
[0009] Preferably, the gate driver chip U6 is a driver chip with the model number UCC21750.
[0010] In the PWM dead-time protection circuit for power devices disclosed in this utility model, the circuit composed of resistor R69, diode D51, resistor R67, and capacitor C129 causes a 1.3µs delay in the low-to-high transition of the upper bridge drive signal PWM_H applied to pin 10 of the gate drive chip U6, and a 2.6µs delay in the high-to-low transition of the diode D51, resistor R67, and capacitor C129. Similarly, the lower bridge drive signal PWM_L on the interlocked side also has a 2.6µs high-to-low transition delay and a 1.3µs low-to-high transition delay, thus forming a symmetrical hardware dead time of 2.6 - 1.3 = 1.3µs. The dead-time simulation waveform is shown below. Figure 2 As shown. Compared with the existing technology that only uses upper and lower bridge interlocking + software dead time, this utility model adopts a combination of upper and lower bridge interlocking, software dead time and hardware dead time, which can effectively enhance the dead time protection function and further avoid the power device bridge arm shoot-through short circuit. Attached Figure Description
[0011] Figure 1 This is a schematic diagram of the PWM dead-time protection circuit for the power device of this utility model.
[0012] Figure 2 This is a simulation waveform diagram of the dead zone when the circuit of this utility model is working. Detailed Implementation
[0013] The present invention will now be described in more detail with reference to the accompanying drawings and embodiments.
[0014] This utility model discloses a PWM dead-time protection circuit for power devices. Please refer to [link / reference]. Figure 1It includes a gate driver chip U6, diodes D51 and D53, resistors R67, R69, R72, R73, capacitors C129 and C140. The first terminal of resistor R69 is used to connect to the upper bridge drive signal PWM_H. The second terminal of resistor R69 is connected to the anode of diode D51. The cathode of diode D51 is connected to the upper bridge input terminal IN+ of the gate driver chip U6. Resistor R67 is connected between the first terminal of resistor R69 and diode D51. Between the cathodes of the diodes, capacitor C129 is connected between the cathode of the diode D51 and ground. The first end of resistor R73 is used to connect the lower bridge drive signal PWM_L. The second end of resistor R73 is connected to the anode of the diode D53. The cathode of the diode D53 is connected to the lower bridge input terminal IN- of the gate driver chip U6. Resistor R72 is connected between the first end of resistor R73 and the cathode of the diode D53. Capacitor C140 is connected between the cathode of the diode D53 and ground.
[0015] In the circuit described above, the circuit consisting of resistor R69, diode D51, resistor R67, and capacitor C129 causes a 1.3µs delay in the transition from low to high level of the upper bridge drive signal PWM_H applied to pin 10 of the gate drive chip U6, and a 2.6µs delay in the transition from high to low level formed by diode D51, resistor R67, and capacitor C129. Similarly, the lower bridge drive signal PWM_L on the interlocked side also has a 2.6µs delay in transitioning from high to low level and a 1.3µs delay in transitioning from low to high level, thus forming a symmetrical hardware dead zone of 2.6 - 1.3 = 1.3µs. The simulation waveform of the dead zone is shown below. Figure 2 As shown. Compared with the existing technology that only uses upper and lower bridge interlocking + software dead time, this utility model adopts a combination of upper and lower bridge interlocking, software dead time and hardware dead time, which can effectively enhance the dead time protection function and further avoid the power device bridge arm shoot-through short circuit.
[0016] As a preferred embodiment, resistors R67, R69, R72, and R73 are all 1KΩ resistors. Furthermore, capacitors C129 and C140 are both 3.3nF capacitors.
[0017] In practical applications, this invention is suitable for driving half-bridge and full-bridge power devices. It employs a circuit design combining upper and lower bridge interlocking, software dead time, and hardware dead time, which strengthens dead time protection and prevents shoot-through short circuits in the bridge arms of the power devices. Specifically, the software can set the dead time delay to x according to actual needs, resulting in a total dead time delay of x + 1.3 µs.
[0018] To ensure stable circuit operation, this embodiment includes a capacitor C147, which is connected between the power supply terminal of the gate driver chip U6 and ground.
[0019] As a preferred embodiment, the gate driver chip U6 is a UCC21750 driver chip. In practical applications, pins 10 and 11 of the gate driver chip U6 are positive and negative input pins, and pin 11 is connected to the drive signal of the complementary bridge, which can perform the interlock function between the upper and lower bridges.
[0020] The above description is only a preferred embodiment of the present utility model and is not intended to limit the present utility model. All modifications, equivalent substitutions or improvements made within the technical scope of the present utility model should be included within the scope of protection of the present utility model.
Claims
1. A power device PWM dead-time protection circuit, characterized by, The system includes a gate driver chip U6, diodes D51 and D53, resistors R67, R69, R72, and R73, capacitors C129 and C140. The first terminal of resistor R69 is connected to the upper bridge drive signal PWM_H. The second terminal of resistor R69 is connected to the anode of diode D51. The cathode of diode D51 is connected to the upper bridge input terminal IN+ of the gate driver chip U6. Resistor R67 is connected between the first terminal of resistor R69 and the cathode of diode D51. Between the cathodes, capacitor C129 is connected between the cathode of diode D51 and ground. The first end of resistor R73 is used to connect the lower bridge drive signal PWM_L. The second end of resistor R73 is connected to the anode of diode D53. The cathode of diode D53 is connected to the lower bridge input terminal IN- of gate driver chip U6. Resistor R72 is connected between the first end of resistor R73 and the cathode of diode D53. Capacitor C140 is connected between the cathode of diode D53 and ground.
2. The power device PWM dead-time protection circuit of claim 1, wherein, The resistors R67, R69, R72, and R73 are all 1KΩ resistors.
3. The power device PWM dead-time protection circuit of claim 1, wherein, Both capacitors C129 and C140 are capacitors with a capacitance of 3.3nF.
4. The power device PWM dead-time protection circuit of claim 1, wherein, It includes a capacitor C147, which is connected between the power supply terminal of the gate driver chip U6 and ground.
5. The power device PWM dead-time protection circuit of claim 1, wherein, The gate driver chip U6 is a driver chip with the model number UCC21750.