A new energy automobile clock pulse signal charging signal acquisition circuit

Abstract

This utility model discloses a clock pulse signal charging signal acquisition circuit for new energy vehicles, belonging to the field of electric vehicle charging technology. It includes: a filtering module, whose first input terminal is used to receive clock pulse signals; a judgment module, whose second input terminal is electrically connected to the first output terminal of the filtering module; a first voltage value acquisition module, whose third input terminal is electrically connected to the second output terminal of the judgment module; and a second voltage value acquisition module, whose fourth input terminal is electrically connected to the third output terminal of the first voltage value acquisition module, and whose fourth output terminal is electrically connected to the clock pulse chip level acquisition terminal. This utility model solves the problem of existing circuits being unable to accurately acquire the voltage, frequency, and duty cycle of the CP clock pulse signal through the orderly cooperation of the filtering module, judgment module, first voltage value acquisition module, and second voltage value acquisition module.

Description

Technical Field

[0001] This utility model discloses a clock pulse signal charging signal acquisition circuit for new energy vehicles, belonging to the field of electric vehicle charging technology. Background Technology

[0002] The charging environment for new energy vehicles is filled with numerous sources of electromagnetic interference, including onboard electronic devices, power grid fluctuations, and other nearby charging equipment. The CP clock pulse signal itself is a weak electrical signal, making it highly susceptible to interference in such a complex electromagnetic environment.

[0003] Currently used signal acquisition techniques, such as those based on traditional ADCs (analog-to-digital converters), are insufficient in terms of sampling accuracy and speed to meet the requirements for acquiring CP clock pulse signals. The voltage variation range of the CP signal is narrow and requires extremely high accuracy; traditional ADCs have limited resolution and may not be able to accurately capture minute voltage changes. Regarding frequency and duty cycle acquisition, because the CP signal frequency is relatively high and dynamically changing, ordinary acquisition techniques cannot keep up with the signal processing speed, easily leading to missed samples or misjudgments. Utility Model Content

[0004] The purpose of this invention is to solve the problem of the inability to accurately acquire the voltage, frequency and duty cycle of the CP clock pulse signal, and to propose a clock pulse signal charging signal acquisition circuit for new energy vehicles.

[0005] The problem to be solved by this invention is achieved by the following technical solution:

[0006] A clock pulse signal charging signal acquisition circuit for a new energy vehicle includes: a filtering module, the first input terminal of which is used to receive clock pulse signals; a judgment module, the second input terminal of which is electrically connected to the first output terminal of the filtering module; a first voltage value acquisition module, the third input terminal of which is electrically connected to the second output terminal of the judgment module; and a second voltage value acquisition module, the fourth input terminal of which is electrically connected to the third output terminal of the first voltage value acquisition module, and the fourth output terminal of which is electrically connected to the clock pulse chip level acquisition terminal.

[0007] Preferably, the filtering module includes: an inductor, the first input terminal of which is used to receive a clock pulse signal; a MOS parasitic diode, the first terminal of which is electrically connected to the first input terminal and the second terminal of which is electrically connected to ground; and a first capacitor, the first terminal of which is electrically connected to the first output terminal of the inductor and the second terminal of which is electrically connected to ground.

[0008] The first diode has its first terminal electrically connected to the first terminal of the first capacitor and the first output terminal of the inductor, respectively; the first resistor has its first terminal electrically connected to the second terminal of the first diode.

[0009] Preferably, the filtering module includes: a second resistor, the first end of which is electrically connected to the second end of the first resistor, and the second end of the second resistor is electrically connected to ground; a third resistor, the first end of which is electrically connected to the second end of the first resistor; a second capacitor, the first end of which is electrically connected to the second end of the third resistor, and the second end of the second capacitor is electrically connected to ground; a first comparator, the non-inverting input terminal of which is electrically connected to the first end of the second capacitor and the second end of the third resistor, respectively; a fourth resistor, the first end of which is electrically connected to the positive terminal; and a fifth resistor, the fifth resistor's... One end of the capacitor is electrically connected to the ground terminal; the first end of the third capacitor is electrically connected to the ground terminal; the first end of the sixth resistor is electrically connected to the output terminal of the first comparator; the first end of the seventh resistor is electrically connected to the output terminal of the first comparator; the first end of the fourth capacitor is electrically connected to the ground terminal, and the second end of the fourth capacitor is electrically connected to the second end of the seventh resistor and the frequency and duty cycle acquisition terminal, respectively; wherein, the second ends of the fourth resistor, the fifth resistor, the third capacitor, and the sixth resistor are electrically connected to the inverting input terminal of the first comparator.

[0010] Preferably, the first voltage value acquisition module includes: a seventh resistor, the first end of which is electrically connected to the first end of a second resistor, the second end of the first resistor, and the first end of a third resistor; an eighth resistor, the first end of which is electrically connected to the second end of the seventh resistor, and the second end of the eighth resistor is electrically connected to a ground terminal; a ninth resistor, the first end of which is electrically connected to the first end of the seventh resistor and the first end of the eighth resistor; a tenth resistor, the first end of which is electrically connected to the second end of the ninth resistor; a fifth capacitor, the first end of which is electrically connected to a ground terminal, and the second end of which is electrically connected to the second end of the tenth resistor; a first operational amplifier, the non-inverting input terminal of which is electrically connected to the second end of the tenth resistor and the second end of the fifth capacitor; a sixth capacitor, the first end of which is electrically connected to the first end of the tenth resistor, and the second end of which is electrically connected to the output terminal of the first operational amplifier; and a second operational amplifier. The non-inverting input terminal of the amplifier is electrically connected to the second terminal of the sixth capacitor, the output terminal of the first operational amplifier, and the inverting input terminal of the first operational amplifier, respectively. The eleventh resistor has its first terminal electrically connected to the output terminal of the second operational amplifier. The base of the transistor is electrically connected to the second terminal of the eleventh resistor. The twelfth resistor has its first terminal electrically connected to the collector of the transistor, and its second terminal electrically connected to the positive terminal. The thirteenth resistor has its first terminal electrically connected to the emitter of the transistor, and its second terminal electrically connected to ground. The seventh capacitor has its first terminal electrically connected to the emitter of the transistor and the first terminal of the thirteenth resistor, respectively, and its second terminal electrically connected to ground. The third operational amplifier has its non-inverting input terminal electrically connected to the emitter of the transistor, the first terminal of the thirteenth resistor, and the first terminal of the seventh capacitor, respectively, and its inverting input terminal is electrically connected to the output terminal.

[0011] Preferably, the second voltage value acquisition module includes: a fourteenth resistor, the first end of which is electrically connected to the inverting input and output of the third operational amplifier; a fifteenth resistor, the first end of which is electrically connected to the second end of the fourteenth resistor; an eighth capacitor, the first end of which is electrically connected to the second end of the fifteenth resistor, and the second end of which is electrically connected to ground; a fourth operational amplifier, the non-inverting input of which is electrically connected to the first end of the eighth capacitor and the second end of the fifteenth resistor, and the inverting input of which is electrically connected to the output; a ninth capacitor, the first end of which is electrically connected to the output of the fourth operational amplifier, and the second end of which is electrically connected to the first end of the fifteenth resistor; a sixteenth resistor, the first end of which is electrically connected to the first end of the ninth capacitor, the inverting input of the fourth operational amplifier, and the output; and the second end of which is electrically connected to the CP chip level acquisition terminal; and a tenth capacitor, the first end of which is electrically connected to the second end of the sixteenth resistor and the CP chip level acquisition terminal, and the second end of which is electrically connected to ground.

[0012] The advantages of this invention compared to existing technologies are as follows:

[0013] This invention provides a clock pulse signal charging signal acquisition circuit for new energy vehicles. Through the orderly cooperation of a filtering module, a judgment module, a first voltage value acquisition module, and a second voltage value acquisition module, it achieves accurate acquisition of the CP clock pulse signal voltage, frequency, and duty cycle at the hardware level by filtering, judging, and acquiring the signal with high precision, thus providing a strong guarantee for the safe and stable operation of the charging process. Attached Figure Description

[0014] Figure 1 This is a circuit diagram of the clock pulse signal and charging signal acquisition circuit for new energy vehicles according to this utility model. Detailed Implementation

[0015] The following is based on the appendix Figure 1 Further explanation of this utility model:

[0016] The technical solution of this utility model will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this utility model. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this utility model.

[0017] In the description of this utility model, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.

[0018] In the description of this utility model, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.

[0019] like Figure 1 As shown, the first embodiment of this utility model provides a clock pulse signal charging signal acquisition circuit for new energy vehicles based on the prior art, including: a filtering module, a judgment module, a first voltage value acquisition module, and a second voltage value acquisition module. The first input terminal of the filtering module is used to receive clock pulse signals. The second input terminal of the judgment module is electrically connected to the first output terminal of the filtering module. The third input terminal of the first voltage value acquisition module is electrically connected to the second output terminal of the judgment module. The fourth input terminal of the second voltage value acquisition module is electrically connected to the third output terminal of the first voltage value acquisition module. The fourth output terminal of the second voltage value acquisition module is electrically connected to the clock pulse chip level acquisition terminal.

[0020] By applying this embodiment, through the orderly cooperation of the filtering module, the judgment module, the first voltage value acquisition module, and the second voltage value acquisition module, signal filtering, judgment, and high-precision acquisition at the hardware level can be achieved, enabling accurate acquisition of the CP clock pulse signal voltage, frequency, and duty cycle, thus providing a strong guarantee for the safe and stable operation of the charging process.

[0021] Furthermore, the filtering module includes: an inductor L1, a MOS parasitic diode D2, a first capacitor C1, a first diode D1, and a first resistor R1. The first input terminal of the inductor L1 is used to receive a clock pulse signal. The first terminal of the MOS parasitic diode D2 is electrically connected to the first input terminal, and the second terminal of the MOS parasitic diode D2 is electrically connected to the ground terminal. The first terminal of the first capacitor C1 is electrically connected to the first output terminal of the inductor L1, and the second terminal of the first capacitor C1 is electrically connected to the ground terminal. The first terminal of the first diode D1 is electrically connected to both the first terminal of the first capacitor C1 and the first output terminal of the inductor L1. The first terminal of the first resistor R1 is electrically connected to the second terminal of the first diode D1.

[0022] In this embodiment, the filtering module includes: a second resistor R2, a third resistor R3, a second capacitor C2, a first comparator U1, a fourth resistor R4, a fifth resistor R5, a third capacitor C3, a sixth resistor R6, a seventh resistor R7, and a fourth capacitor C4. The first terminal of the second resistor R2 is electrically connected to the second terminal of the first resistor R1, and the second terminal of the second resistor R2 is electrically connected to ground. The first terminal of the third resistor R3 is electrically connected to the second terminal of the first resistor R1. The first terminal of the second capacitor C2 is electrically connected to the second terminal of the third resistor R3, and the second terminal of the second capacitor C2 is electrically connected to ground. The first comparator... The non-inverting input terminal of U1 is electrically connected to the first terminal of the second capacitor and the second terminal of the third resistor R3, respectively. The first terminal of the fourth resistor R4 is electrically connected to the 3.3V positive terminal. The first terminal of the fifth resistor R5 is electrically connected to the ground terminal. The first terminal of the third capacitor C3 is electrically connected to the ground terminal. The first terminal of the sixth resistor R6 is electrically connected to the output terminal of the first comparator U1. The first terminal of the seventh resistor R7 is electrically connected to the output terminal of the first comparator U1. The first terminal of the fourth capacitor C4 is electrically connected to the ground terminal. The second terminal of the fourth capacitor C4 is electrically connected to the second terminal of the seventh resistor R7 and the frequency and duty cycle acquisition terminals, respectively. The second terminals of the fourth resistor R4, the fifth resistor R5, the third capacitor C3, and the sixth resistor R6 are all electrically connected to the inverting input terminal of the first comparator U1.

[0023] In this embodiment, the CP clock pulse signal, after passing through the first diode D1, is filtered into a PWM waveform where a high level represents the battery voltage and a low level represents 0V. The input voltage at the non-inverting input of the first comparator U1 is the reference voltage V1+ obtained by dividing the voltage between the fourth resistor R4 and the fifth resistor R5. The input voltage at the inverting input is the voltage V1- obtained by dividing the voltage between the first resistor R1 and the second resistor R2. When V1- is greater than V1+, the comparator outputs a low level; when V1- is less than V1+, the comparator outputs a high level. The voltage level is the comparator's supply voltage, approximately 3.3V. The microcontroller acquires the output voltage of the first comparator U1 to determine the frequency and duty cycle of the current CP clock pulse signal.

[0024] In one exemplary embodiment, the first voltage value acquisition module includes: a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, a fifth capacitor C5, a first operational amplifier U2, a sixth capacitor C6, a second operational amplifier U3, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a seventh capacitor C7, a transistor Q1, and a third operational amplifier U4. The first terminal of the seventh resistor R7 is electrically connected to the first terminal of the second resistor R2, the second terminal of the first resistor, and the first terminal of the third resistor R3, respectively. The first terminal of the eighth resistor R8 is connected to the seventh resistor... The second terminal of resistor R7 is electrically connected; the second terminal of resistor R8 is electrically connected to ground; the first terminal of resistor R9 is electrically connected to the first terminals of resistors R7 and R8 respectively; the first terminal of resistor R10 is electrically connected to the second terminal of resistor R9; the first terminal of capacitor C5 is electrically connected to ground; the second terminal of capacitor C5 is electrically connected to the second terminal of resistor R10; the non-inverting input terminal of operational amplifier U2 is electrically connected to the second terminal of resistor R10 and the second terminal of capacitor C5 respectively; the first terminal of capacitor C6 is electrically connected to the ground terminal; the non-inverting input terminal of operational amplifier U2 is electrically connected to the second terminal of operational amplifier U2; the non-inverting input terminal of operational amplifier U2 is electrically connected to the second terminal of operational amplifier U2; the non-inverting input terminal of operational amplifier U2 is electrically connected to the second terminal of operational amplifier U2; the non-inverting input terminal of operational amplifier U2 is electrically connected to the second terminal of operational amplifier U2; the non-inverting input terminal of operational amplifier U2 is electrically connected to the second terminal of operational amplifier U2; the non-inverting input terminal of operational amplifier U2 is electrically connected to the second terminal of operational amplifier U2; the non-inverting input terminal of operational amplifier U2 is electrically connected to the ground terminal ... The first terminal of resistor R10 is electrically connected to the first terminal of the first operational amplifier U2. The second terminal of capacitor R6 is electrically connected to the output terminal of the first operational amplifier U2. The non-inverting input terminal of the second operational amplifier U3 is electrically connected to the second terminal of capacitor R6, the output terminal of the first operational amplifier U2, and the inverting input terminal of the first operational amplifier U2, respectively. The first terminal of resistor R11 is electrically connected to the output terminal of the second operational amplifier U3. The base of transistor Q1 is electrically connected to the second terminal of resistor R11. The first terminal of resistor R12 is electrically connected to the collector of transistor Q1. The second terminal of the third operational amplifier U4 is electrically connected to the positive terminal. The first terminal of the thirteenth resistor R13 is electrically connected to the emitter of the transistor Q1. The second terminal of the thirteenth resistor R13 is electrically connected to the ground terminal. The first terminal of the seventh capacitor C7 is electrically connected to the emitter of the transistor Q1 and the first terminal of the thirteenth resistor R13. The second terminal of the seventh capacitor C7 is electrically connected to the ground terminal. The non-inverting input terminal of the third operational amplifier U4 is electrically connected to the emitter of the transistor Q1, the first terminal of the thirteenth resistor R13, and the first terminal of the seventh capacitor C7. The inverting input terminal of the third operational amplifier U4 is electrically connected to the output terminal.

[0025] Furthermore, the second voltage value acquisition module includes: a fourteenth resistor R14, a fifteenth resistor R15, an eighth capacitor C8, a fourth operational amplifier U5, a ninth capacitor C9, a sixteenth resistor R16, and a tenth capacitor C10. The first terminal of the fourteenth resistor R14 is electrically connected to the inverting input and output terminals of the third operational amplifier U4, respectively. The first terminal of the fifteenth resistor R15 is electrically connected to the second terminal of the fourteenth resistor R14. The first terminal of the eighth capacitor C8 is electrically connected to the second terminal of the fifteenth resistor R15, and the second terminal of the eighth capacitor C8 is electrically connected to the ground terminal. The non-inverting input terminal of the fourth operational amplifier U5 is connected to the first terminal of the eighth capacitor C8 and the tenth capacitor C9 of the fifteenth resistor R15, respectively. The two terminals are electrically connected. The inverting input terminal and the output terminal of the fourth operational amplifier U5 are electrically connected. The first terminal of the ninth capacitor C9 is electrically connected to the output terminal of the fourth operational amplifier U5. The second terminal of the ninth capacitor C9 is electrically connected to the first terminal of the fifteenth resistor R15. The first terminal of the sixteenth resistor R16 is electrically connected to the first terminal of the ninth capacitor C9, the inverting input terminal and the output terminal of the fourth operational amplifier U5, respectively. The second terminal of the sixteenth resistor R16 is electrically connected to the level acquisition terminal of the CP chip. The first terminal of the tenth capacitor C10 is electrically connected to the second terminal of the sixteenth resistor R16 and the level acquisition terminal of the CP chip, respectively. The second terminal of the tenth capacitor C10 is electrically connected to the ground terminal.

[0026] In this embodiment, the input voltage V2+ at the non-inverting input of the first operational amplifier U2 is also a PWM signal, which is the voltage after being divided by the first resistor R1, the second resistor R2, the seventh resistor R7, and the eighth resistor R8. The high level is 0.2 times the battery voltage. When the battery voltage is 10V, V2+ is 2V. The output voltage of the first operational amplifier U2 is equal to V2+.

[0027] The voltage V3+ at the non-inverting input of the second operational amplifier U3 is equal to the output voltage of the first operational amplifier U2, which is 2V at the high level. Since the output voltage of the second operational amplifier U3 is equal to V3+, transistor Q1 conducts and capacitor C7 charges when the CP clock pulse signal is high, and Q1 is de-energized when the CP clock pulse signal is low. The voltage V3- at the inverting input of the second operational amplifier U3 is equal to V3+. Because capacitor C7 is a large-value capacitor, it keeps V3- at 2V when the CP clock pulse signal is low.

[0028] The voltage at the non-inverting input V4+ of the third operational amplifier U4 is equal to V3-, and the output voltage of the third operational amplifier U4 is equal to V4+. Therefore, the output voltage of the third operational amplifier U4 is 2V. The function of the third operational amplifier U4 is to make the input high impedance and the output low impedance, which facilitates data acquisition by the microcontroller.

[0029] The voltage at the non-inverting input V5+ of the fourth operational amplifier U5 is equal to the output voltage of the third operational amplifier U4, and the output voltage of the third operational amplifier U5 is equal to V5+. Therefore, the CP clock pulse signal voltage acquired by the microcontroller is 2V, which is 0.2 times the battery voltage. The function of the third operational amplifier U5 is filtering, making the voltage acquired by the microcontroller more stable.

[0030] Although embodiments of this utility model have been disclosed above, they are not limited to the applications listed in the specification and embodiments. It can be applied to various fields suitable for this utility model. Other modifications can be readily implemented by those skilled in the art. Therefore, without departing from the general concept defined by the claims and their equivalents, this utility model is not limited to the specific details and examples shown and described herein.

Claims

1. A clock pulse signal and charging signal acquisition circuit for new energy vehicles, characterized in that, include: The filtering module has a first input terminal for receiving clock pulse signals. The judgment module is electrically connected to the first output of the filtering module. The first voltage value acquisition module has its third input terminal electrically connected to the second output terminal of the judgment module; The second voltage value acquisition module has its fourth input terminal electrically connected to the third output terminal of the first voltage value acquisition module, and its fourth output terminal electrically connected to the clock pulse chip level acquisition terminal.

2. The new energy vehicle clock pulse signal charging signal acquisition circuit according to claim 1, characterized in that, The filtering module includes: An inductor, wherein the first input terminal of the inductor is used to receive the clock pulse signal; A MOS parasitic diode, wherein the first end of the MOS parasitic diode is electrically connected to the first input terminal, and the second end of the MOS parasitic diode is electrically connected to the ground terminal; A first capacitor, wherein a first terminal of the first capacitor is electrically connected to a first output terminal of the inductor, and a second terminal of the first capacitor is electrically connected to a ground terminal; A first diode, the first end of which is electrically connected to the first end of the first capacitor and the first output end of the inductor, respectively; The first resistor has its first end electrically connected to the second end of the first diode.

3. The new energy vehicle clock pulse signal charging signal acquisition circuit according to claim 2, characterized in that, The filtering module includes: The second resistor has its first end electrically connected to the second end of the first resistor, and its second end electrically connected to the ground terminal. The third resistor, wherein the first end of the third resistor is electrically connected to the second end of the first resistor; The second capacitor has its first terminal electrically connected to the second terminal of the third resistor, and its second terminal electrically connected to the ground terminal. A first comparator, wherein the non-inverting input terminal of the first comparator is electrically connected to the first terminal of the second capacitor and the second terminal of the third resistor, respectively; The fourth resistor, the first end of which is electrically connected to the positive electrode; The fifth resistor, wherein the first end of the fifth resistor is electrically connected to the grounding terminal; The third capacitor, wherein the first terminal of the third capacitor is electrically connected to the ground terminal; The sixth resistor, the first end of which is electrically connected to the output terminal of the first comparator; The seventh resistor, the first end of which is electrically connected to the output terminal of the first comparator; The fourth capacitor has its first terminal electrically connected to the ground terminal, and its second terminal electrically connected to the second terminal of the seventh resistor and the frequency and duty cycle acquisition terminal, respectively. The second terminals of the fourth resistor, the fifth resistor, the third capacitor, and the sixth resistor are electrically connected to the inverting input terminal of the first comparator.

4. The new energy vehicle clock pulse signal charging signal acquisition circuit according to claim 3, characterized in that, The first voltage value acquisition module includes: The seventh resistor has its first end electrically connected to the first end of the second resistor, the second end of the first resistor, and the first end of the third resistor, respectively. The eighth resistor has its first end electrically connected to the second end of the seventh resistor, and its second end electrically connected to the ground terminal. The ninth resistor has its first end electrically connected to the first end of the seventh resistor and the first end of the eighth resistor, respectively. The tenth resistor, wherein the first end of the tenth resistor is electrically connected to the second end of the ninth resistor; The fifth capacitor has its first terminal electrically connected to the ground terminal and its second terminal electrically connected to the second terminal of the tenth resistor. A first operational amplifier, wherein the non-inverting input terminal of the first operational amplifier is electrically connected to the second terminal of the tenth resistor and the second terminal of the fifth capacitor, respectively; The sixth capacitor has its first terminal electrically connected to the first terminal of the tenth resistor, and its second terminal electrically connected to the output terminal of the first operational amplifier. The second operational amplifier has its non-inverting input terminal electrically connected to the second terminal of the sixth capacitor, the output terminal of the first operational amplifier, and the inverting input terminal of the first operational amplifier, respectively. The eleventh resistor, the first end of which is electrically connected to the output terminal of the second operational amplifier; The base of the transistor is electrically connected to the second terminal of the eleventh resistor; The twelfth resistor has its first end electrically connected to the collector of the transistor and its second end electrically connected to the positive terminal. The thirteenth resistor has its first end electrically connected to the emitter of the transistor and its second end electrically connected to the ground terminal. The seventh capacitor has its first terminal electrically connected to the emitter of the transistor and the first terminal of the thirteenth resistor, and its second terminal electrically connected to the ground terminal. The third operational amplifier has its non-inverting input terminal electrically connected to the emitter of the transistor, the first terminal of the thirteenth resistor, and the first terminal of the seventh capacitor, respectively, and its inverting input terminal electrically connected to its output terminal.

5. The new energy vehicle clock pulse signal charging signal acquisition circuit according to claim 4, characterized in that, The second voltage value acquisition module includes: The fourteenth resistor, the first end of which is electrically connected to the inverting input terminal and the output terminal of the third operational amplifier, respectively; The fifteenth resistor, the first end of which is electrically connected to the second end of the fourteenth resistor; The eighth capacitor has its first terminal electrically connected to the second terminal of the fifteenth resistor, and its second terminal electrically connected to the ground terminal. The fourth operational amplifier has its non-inverting input terminal electrically connected to the first terminal of the eighth capacitor and the second terminal of the fifteenth resistor, and its inverting input terminal electrically connected to its output terminal. The ninth capacitor has its first terminal electrically connected to the output terminal of the fourth operational amplifier, and its second terminal electrically connected to the first terminal of the fifteenth resistor. The sixteenth resistor has its first end electrically connected to the first end of the ninth capacitor, the inverting input terminal and the output terminal of the fourth operational amplifier, and its second end electrically connected to the level acquisition terminal of the CP chip. The tenth capacitor has its first terminal electrically connected to the second terminal of the sixteenth resistor and the CP chip level acquisition terminal, and its second terminal electrically connected to the ground terminal.

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