Wireless radio frequency processing system

Abstract

This application discloses a wireless radio frequency (RF) processing system. The system includes an RF transceiver unit, a ZYNQ processing unit, and a coprocessor unit. The ZYNQ processing unit includes a first interface and a second interface. The ZYNQ processing unit converts RF data into RF signals. The first interface is connected to the RF transceiver unit and transmits the RF signals to the RF transceiver unit, enabling the RF transceiver unit to transmit RF signals. The second interface is connected to the coprocessor unit and transmits first RF data from the RF data to the coprocessor unit. The coprocessor unit receives the first RF data through the second interface, converts it into a first RF signal, and transmits the first RF signal to the ZYNQ processing unit through the second interface. The solution provided in this application can improve the data processing efficiency of wireless RF signals.

Description

Technical Field

[0001] This application belongs to the field of signal processing technology, and in particular relates to a wireless radio frequency processing system. Background Technology

[0002] Radio frequency signals are widely used in many fields and occasions. In complex radio frequency signal communication systems, there are strict requirements for the communication speed and interoperability of the communication system.

[0003] In related technologies, data processing can be achieved by combining FPGA (Field Programmable Gate Array) with ARM processor or DSP (Digital Signal Processing) processor. However, this method has slow communication speed and low data processing efficiency when acquiring, playing back and processing wireless radio frequency signals. Utility Model Content

[0004] This application provides a wireless radio frequency processing system that can improve the data processing efficiency of wireless radio frequency signals.

[0005] In a first aspect, embodiments of this application provide a wireless radio frequency processing system, which includes: a radio frequency transceiver unit, a ZYNQ processing unit, and a coprocessing unit. The ZYNQ processing unit includes a first interface and a second interface. The ZYNQ processing unit is used to convert radio frequency data into radio frequency signals. The first interface is connected to the radio frequency transceiver unit and is used to send the radio frequency signals to the radio frequency transceiver unit so that the radio frequency transceiver unit can transmit radio frequency signals. The second interface is connected to the coprocessing unit and is used to send first radio frequency data in the radio frequency data to the coprocessing unit. The coprocessing unit is used to receive the first radio frequency data through the second interface, convert the first radio frequency data into a first radio frequency signal, and send the first radio frequency signal to the ZYNQ processing unit through the second interface.

[0006] According to an embodiment of the first aspect of this application, the ZYNQ processing unit includes a data management unit and a logic processing unit. The logic processing unit includes a first interface and a second interface. The data management unit is connected to the logic processing unit and is used to manage radio frequency data. The logic processing unit is connected to the radio frequency transceiver unit through the first interface and is used to read and convert the radio frequency data into radio frequency signals, and send the radio frequency signals to the radio frequency transceiver unit through the first interface. The logic processing unit is connected to the coprocessing unit through the second interface and is used to send first radio frequency data to the coprocessing unit and receive the first radio frequency signal generated by the coprocessing unit.

[0007] In some embodiments, the data management unit includes a processor, a storage unit, and an interface unit; the processor is used to manage radio frequency data; the storage unit is connected to the processor and is used to store radio frequency data; the processor interacts with off-chip storage units and logic processing units through the interface unit.

[0008] In some embodiments, the data management unit further includes a bus controller and a data packet capture unit. The interface unit includes a bus interface and a data packet capture interface. The bus interface includes a general-purpose bus interface and a high-speed bus interface. The high-speed bus interface is connected between the bus controller and the logic processing unit and is used to transmit control signals output by the bus controller. The general-purpose bus interface is connected between the storage unit and the logic processing unit and is used to transmit radio frequency data stored in the storage unit to the logic processing unit. The data packet capture interface is connected between the data packet capture unit and the logic processing unit and is used to transmit a first configuration parameter from the data packet capture unit to the logic processing unit. The first configuration parameter is a parameter for configuring the bitstream program of the logic processing unit.

[0009] In some embodiments, the interface unit further includes a debug network port, a debug serial port, and a joint test workgroup interface; the debug network port is connected between the data management unit and the Ethernet interface chip; the debug serial port is connected between the data management unit and an external program debugging device; and the joint test workgroup interface is connected between the data management unit and an external test device.

[0010] In some embodiments, the first interface includes a low-voltage differential interface and a parameter configuration interface; the low-voltage differential interface is connected between the ZYNQ processing unit and the RF transceiver unit and is used to transmit interactive data between the ZYNQ processing unit and the RF transceiver unit; the parameter configuration interface is connected between the ZYNQ processing unit and the RF transceiver unit and is used to transmit second configuration parameters, which are parameters configured by the ZYNQ processing unit for the RF transceiver unit.

[0011] In some embodiments, the radio frequency transceiver unit includes multiple analog-to-digital converters; the multiple analog-to-digital converters are connected to the ZYNQ processing unit through a low-voltage differential interface and are used to perform analog-to-digital conversion on the radio frequency signal output by the ZYNQ processing unit.

[0012] In some embodiments, the radio frequency transceiver unit further includes a radio frequency input terminal and a radio frequency output terminal; the radio frequency output terminal is used to transmit radio frequency signals; and the radio frequency input terminal is used to receive echo signals corresponding to the radio frequency signals.

[0013] In some embodiments, the wireless radio frequency processing system further includes: a clock unit and a power supply unit; the clock unit is connected to the ZYNQ processing unit and is used to generate a system clock and an input clock; the power supply unit is connected to the ZYNQ processing unit, the radio frequency transceiver unit and the coprocessor unit and is used to supply power to the ZYNQ processing unit, the radio frequency transceiver unit and the coprocessor unit.

[0014] In some embodiments, the clock unit includes a crystal oscillator and a clock buffer; the crystal oscillator is connected to the ZYNQ processing unit and is used to generate a system clock for use by the ZYNQ processing unit; the clock buffer is connected to the ZYNQ processing unit and is used to receive an external clock and generate an input clock.

[0015] As can be seen from the above, in this embodiment of the application, a combination of a ZYNQ processing unit, a coprocessing unit, and a radio frequency transceiver unit is used to process wireless radio frequency data. The ZYNQ processing unit is connected to the coprocessing unit. When a large amount of data needs to be processed and the logic resources of the ZYNQ processing unit are strained, the coprocessing unit processes part of the data (i.e., the first radio frequency data) to reduce the workload of the ZYNQ processing unit, make up for the insufficient computing power of the ZYNQ processing unit, and improve the efficiency of radio frequency data processing.

[0016] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0017] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0018] Figure 1 This is a schematic diagram of the structure of a wireless radio frequency processing system provided in one embodiment of this application;

[0019] Figure 2 This is a schematic diagram of the interface of a DSP with a low-speed interface of EMIF provided in one embodiment of this application;

[0020] Figure 3 This is a detailed structural schematic diagram of a wireless radio frequency processing system provided in one embodiment of this application;

[0021] Figure 4 This is a schematic diagram of the structure of a ZYNQ processing unit provided in one embodiment of this application.

[0022] The reference numerals in the detailed embodiments are as follows:

[0023] 100 - RF transceiver unit; 200 - ZYNQ processing unit; 300 - Coprocessor unit; 400 - Clock unit; 500 - Power supply unit;

[0024] 201 - First interface; 202 - Second interface; 203 - Data management unit; 204 - Logic processing unit;

[0025] 2010 - Low Voltage Differential Interface; 2011 - Parameter Configuration Interface;

[0026] 2021 - Low-speed interface; 2022 - High-speed interface;

[0027] 2031 - Processor; 2032 - Storage unit; 2033 - Interface unit; 2034 - Bus controller; 2035 - Packet capture unit;

[0028] 20331 - Bus interface; 20332 - Packet capture interface; 20333 - Debug network port; 20334 - Debug serial port; 20335 - Joint test workgroup interface;

[0029] 1000 - Analog-to-digital converter; 1001 - RF input terminal; 1002 - RF output terminal. Detailed Implementation

[0030] The embodiments of the technical solution of this application will now be described in detail with reference to the accompanying drawings. These embodiments are only used to more clearly illustrate the technical solution of this application and are therefore merely examples, and should not be used to limit the scope of protection of this application.

[0031] It should be noted that, unless otherwise stated, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by those skilled in the art to which the embodiments of this application pertain.

[0032] In the description of the embodiments of this application, the technical terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the embodiments of this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this application.

[0033] Furthermore, technical terms such as "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. In the description of the embodiments of this application, "a plurality of" means two or more, unless otherwise explicitly defined.

[0034] In the description of the embodiments of this application, unless otherwise expressly specified and limited, the technical terms such as "installation," "connection," "joining," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. For those skilled in the art, the specific meaning of the above terms in the embodiments of this application can be understood according to the specific circumstances.

[0035] In the description of the embodiments of this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0036] To facilitate understanding, before explaining the solution provided in this application, the background of the solution provided in this application will be explained first.

[0037] Radio frequency (RF) signals are widely used in various fields and applications, including communications, broadcasting, and radar systems. In complex RF communication systems, stringent requirements are placed on communication speed and interoperability. On the hardware side, high-performance and reconfigurable RF transceiver modules are needed to achieve RF signal acquisition, playback, and processing functions.

[0038] In related technologies, the hardware architecture typically adopts structures such as "FPGA+DSP" and "FPGA+ARM". The FPGA completes functions such as radio frequency signal acquisition and playback, while the DSP or ARM completes data processing.

[0039] However, both the "FPGA+ARM" and "FPGA+DSP" architectures suffer from cumbersome communication and slow communication speeds between the FPGA and the ARM or DSP. The "FPGA+ARM" architecture has low computing power for radio signal processing and weak interoperability; the ARM's control efficiency over the FPGA is low, and the limited resources of a single FPGA prevent it from achieving the radio's multi-functionality and reconfigurability. The "FPGA+DSP" architecture can achieve signal acquisition, playback, and processing, but its complex structure makes data transmission, storage, and display difficult. Therefore, the JTRS (Joint Tactical Radio System) requires a hardware architecture with high control efficiency, relatively simple structure, and sufficient programmable resources.

[0040] To address the problems existing in related technologies, embodiments of this application provide a wireless radio frequency processing system.

[0041] Figure 1 A schematic diagram of the structure of a wireless radio frequency processing system provided in one embodiment of this application is shown. Figure 1 As shown, Figure 1 As shown, the wireless radio frequency processing system includes a radio frequency transceiver unit 100, a ZYNQ processing unit 200, and a coprocessing unit 300. The ZYNQ processing unit includes a first interface 201 and a second interface 202.

[0042] In one embodiment, the radio frequency transceiver unit 100 can transmit radio frequency signals and receive echo signals. The radio frequency signals can be generated by processing radio frequency data by the ZYNQ processing unit 200 or the co-processing unit 300. In this embodiment, the number of radio frequency transceiver units 100 can be one or more. When there are multiple radio frequency transceiver units 100, they can be positioned in different directions to transmit radio frequency signals in multiple directions and receive echo signals returned from multiple directions. In the scenario where the wireless radio frequency processing system is applied to a vehicle, setting up multiple radio frequency transceiver units 100 can enable the detection of obstacles in multiple directions around the vehicle.

[0043] In one example, the RF transceiver unit 100 can be an AD9361 RF transceiver chip, which can perform analog-to-digital and digital-to-analog conversion of data, transmit RF signals to the outside, receive echo signals, and then transmit the echo signals to the ZYNQ processing unit 200 for data processing. The data processing employs commonly used data processing methods in related technologies, and this application does not specifically limit it. This application mainly focuses on the system architecture as its innovation point, and does not improve or protect specific data processing methods.

[0044] In this embodiment, the ZYNQ processing unit 200 can be a ZYNQ fully programmable system-on-a-chip, possessing the dual characteristics of a processor and an FPGA. While having powerful control capabilities, it also possesses certain programmable resources, enabling flexible implementation of different functions. In this embodiment, the ZYNQ processing unit can process radio frequency (RF) data to generate RF signals. The RF data can be RF data generated by a wireless RF processing system or RF data corresponding to the echo signals received by the RF transceiver unit 100. The data processing employs commonly used data processing methods in related technologies, which are not specifically limited in this application. This application primarily focuses on system architecture innovation and does not improve or protect specific data processing methods.

[0045] like Figure 1 As shown, the ZYNQ processing unit 200 includes a first interface 201 and a second interface 202. The first interface 201 is connected to the radio frequency transceiver unit 100 and is used to send radio frequency signals to the radio frequency transceiver unit 100 so that the radio frequency transceiver unit 100 can transmit radio frequency signals. The second interface 202 is connected to the coprocessing unit 300 and is used to send first radio frequency data from the radio frequency data to the coprocessing unit 300. The first radio frequency data is a portion of the radio frequency data; that is, in this embodiment, the ZYNQ processing unit 200 can send a portion of the radio frequency data to the coprocessing unit 300 for processing, thereby saving the logic resources of the ZYNQ processing unit 200 and improving the processing efficiency of the radio frequency data.

[0046] Since a single ZYNQ processing unit 200 has insufficient programmable resources when facing complex functional requirements, a coprocessor unit 300 is added in this embodiment to compensate for the insufficient computing power of the ZYNQ processing unit 200, thereby easily meeting the complex functional requirements of the radio station.

[0047] In this embodiment, the coprocessing unit 300 can receive and process the first radio frequency data through the second interface 202 to generate a first radio frequency signal, and send the first radio frequency signal to the ZYNQ processing unit 200 through the second interface 202. Thus, the ZYNQ processing unit 200 sends the first radio frequency signal generated by the coprocessing unit 300 to the radio frequency transceiver unit 100, so that the radio frequency transceiver unit 100 transmits the first radio frequency signal.

[0048] In one example, the coprocessor unit 300 can be a DSP, which has high data processing efficiency. When a large amount of data needs to be processed, the logic resources of the ZYNQ processing unit 200 are relatively tight. At this time, the ZYNQ processing unit 200 sends part of the data (i.e., the first RF data) to the coprocessor unit 300 so that the coprocessor unit 300 can process part of the RF data. The second interface 202 between the ZYNQ processing unit 200 and the coprocessing unit 300 includes multiple sub-interfaces, including a low-speed interface 2021 and a high-speed interface 2022. The low-speed interface can be one or more of GPIO (General Purpose Input / Output), UART (Universal Asynchronous Receiver / Transmitter), and EMIF (External Memory Interface) for transmitting parameter information. The high-speed interface can be SRIO (Serial Rapid Input / Output) 4X, with a corresponding transmission rate of up to 20Gbps, meeting the real-time transmission requirements of large data volumes, transmitting data with low latency, and performing related algorithm calculations in the DSP, such as the coprocessing function of the future waveform physical layer.

[0049] As an example, Figure 2 This diagram shows the interface when the low-speed interface of the DSP is EMIF. Figure 2 In this context, EDMA is the DSP's DMA (Direct Memory Access) bus; ELCKIN is the clock input; ECLKOUT is the clock output; ED is the data input / output; EA is the external address output; CE is the external chip select; BE is the byte enable; ARDY is the slave ready signal; AOE is the read enable; ARE is the read / write enable; AWE is the write enable; HLOD is the slave hold signal input; HLODA is the master hold signal output; and BUSEREQ is the bus request signal output.

[0050] In this embodiment, a combination of a ZYNQ processing unit 200, a co-processing unit 300, and a radio frequency transceiver unit 100 is used to process wireless radio frequency data. The ZYNQ processing unit 200 and the co-processing unit 300 are connected. When a large amount of data needs to be processed and the logic resources of the ZYNQ processing unit 200 are strained, the co-processing unit 300 processes a portion of the data (i.e., the first radio frequency data) to reduce the workload of the ZYNQ processing unit 200, compensate for its insufficient computing power, and improve the efficiency of radio frequency data processing. The data processing employs commonly used data processing methods in related technologies, and this application does not specifically limit these methods. The innovation of this application lies primarily in the system architecture, and it does not improve or protect specific data processing methods.

[0051] Figure 3 A detailed structural diagram of the wireless radio frequency processing system is shown, such as... Figure 3 As shown, in addition to the radio frequency transceiver unit 100, the ZYNQ processing unit 200, and the coprocessing unit 300, the wireless radio frequency processing system may also include a clock unit 400 and a power supply unit 500. The following is in conjunction with... Figure 3 The various units in the wireless radio frequency processing system provided in the embodiments of this application will be described.

[0052] like Figure 3 As shown, the ZYNQ processing unit 200 includes a data management unit 203 and a logic processing unit 204. The data management unit 203 can be a PS (Processing System), and the logic processing unit 204 can be a PL (Programmable Logic Unit).

[0053] like Figure 3 As shown, the data management unit 203 is connected to the logic processing unit 204 and is used to manage radio frequency data. For example, the data management unit 203 can perform data management operations such as data storage, data encryption, and data decryption on the radio frequency data. The data processing adopts commonly used data processing methods in related technologies, and this application does not specifically limit it. This application mainly focuses on the system architecture as an innovation point, and does not improve or protect specific data processing methods.

[0054] like Figure 3As shown, the logic processing unit 204 includes a first interface 201 and a second interface 205. The logic processing unit 204 is connected to the radio frequency transceiver unit 100 through the first interface 201, used to read and process radio frequency data, generate radio frequency signals, and send the radio frequency signals to the radio frequency transceiver unit 100 through the first interface 201. The logic processing unit 204 is connected to the coprocessing unit 300 through the second interface 202, used to send first radio frequency data to the coprocessing unit 300 and receive the first radio frequency signals generated by the coprocessing unit 300. The data processing employs commonly used data processing methods in related technologies, which are not specifically limited in this application. This application mainly focuses on the system architecture as an innovation point and does not improve or protect specific data processing methods.

[0055] In one embodiment, Figure 4 A schematic diagram of the ZYNQ processing unit 200 is shown, as follows: Figure 4 As shown, the ZYNQ processing unit 200 includes a data management unit 203 and a logic processing unit 204. The logic processing unit 204 adopts a 28nm process, which reduces the space volume of the logic processing unit 204; the data management unit 203 includes a processor 2031, a storage unit 2032, and an interface unit 2033.

[0056] In this embodiment of the application, the processor 2031 is used to manage radio frequency data. The processor 2031 may include one or more ARM Cortex A9 chips to improve the efficiency of data processing.

[0057] like Figure 4 As shown, storage unit 2032 is connected to processor 2031 and is used to store radio frequency (RF) data. Storage unit 2032 can be a DDR (Double Data Rate) memory, which can process the RF data processed by processor 2031, or cache the RF data to be processed by processor 2031.

[0058] In this embodiment, the processor 2031 interacts with the off-chip storage unit (e.g., off-chip DDR memory, FLASH flash memory) and the logic processing unit 204 through the interface unit 2033.

[0059] In one embodiment, such as Figure 4 As shown, the data management unit 203 also includes a bus controller 2034 and a packet capture unit 2035. The interface unit 2033 includes a bus interface 20331 and a packet capture interface 20332. The bus interface 20331 includes a general-purpose bus interface GP AXI and a high-speed bus interface HP AXI.

[0060] In this embodiment, the bus interface 20331 may be an AXI (Advanced eXtensible Interface) bus to enable high-speed data transmission between the data management unit 203 and the logic processing unit 204, thereby achieving low-latency, high-bandwidth, and simple data transmission.

[0061] In this embodiment, the high-speed bus interface HP AXI is connected between the bus controller 2034 and the logic processing unit 204, and is used to transmit control signals output by the bus controller 2034;

[0062] The general purpose bus interface GP AXI is connected between the storage unit 2032 and the logic processing unit 204, and is used to transmit the radio frequency data stored in the storage unit 2032 to the logic processing unit 204.

[0063] The packet capture interface 20332 is connected between the packet capture unit 2035 and the logic processing unit 204, and is used to transmit the first configuration parameter from the packet capture unit 2035 to the logic processing unit 204. The first configuration parameter is the parameter for configuring the bitstream program of the logic processing unit 204.

[0064] In one example, the aforementioned packet capture unit 2035 can be a PCAP, and its corresponding packet capture interface 20332 can be a PCAP interface. This PCAP interface can configure the bitstream program on the logic processing unit 204 side on the data management unit 203 side, and the designed driver can realize the function of online updating the program of the logic processing unit 204. The program of the logic processing unit 204 can be transmitted from the ZYNQ processing unit to the coprocessing unit 300 through the EMIF interface to realize functions such as program update and loading, and has the function of system reconfigurability.

[0065] In one embodiment, such as Figure 3 As shown, the interface unit 2033 also includes a debug network port 20333, a debug serial port 20334, and a joint test workgroup interface 20335.

[0066] The debug port 20333 is connected between the data management unit 203 and the Ethernet interface chip. The debug port 20333 can be an RGMII, and the Ethernet interface chip can be a Gigabit Ethernet PHY chip to implement the physical layer protocol of Gigabit Ethernet.

[0067] The debug serial port 20334 is connected between the data management unit 203 and the external program debugging device to enable debugging of the external program. The debug serial port can be, but is not limited to, RS232.

[0068] The Joint Test Working Group Interface 20335 connects the data management unit and the external test equipment to enable joint testing of the external test equipment. The Joint Test Working Group Interface 20335 can be, but is not limited to, a JTAG interface.

[0069] In one embodiment, such as Figure 3 As shown, the first interface 201 includes a low-voltage differential interface 2010 and a parameter configuration interface 2011.

[0070] The low-voltage differential interface 2010 is connected between the ZYNQ processing unit 200 and the RF transceiver unit 100, and is used to transmit interactive data between the ZYNQ processing unit 200 and the RF transceiver unit 100. In this embodiment, the low-voltage differential interface 2010 may be an LVDS (Low-Voltage Differential Signaling) interface.

[0071] The parameter configuration interface 2011 is connected between the ZYNQ processing unit 200 and the RF transceiver unit 100, and is used to transmit second configuration parameters. The second configuration parameters are the parameters used by the ZYNQ processing unit 200 to configure the RF transceiver unit 100. The parameter configuration interface 2011 can be SPI (Serial Peripheral Interface).

[0072] In this embodiment of the application, the logic processing unit 204 in the ZYNQ processing unit 200 can be an FPGA, which is connected to the radio frequency transceiver unit 100 (e.g., AD9361) via LVDS to realize the transmission of data after digital-to-analog conversion or analog-to-digital conversion, and to configure the parameters of the radio frequency transceiver unit 100 (e.g., AD9361) via SPI.

[0073] In one embodiment, the radio frequency transceiver unit 100 may include a plurality of analog-to-digital converters 1000, wherein the plurality of analog-to-digital converters are connected to the ZYNQ processing unit 200 via a low-voltage differential interface 2010 for performing analog-to-digital conversion on the radio frequency signals output by the ZYNQ processing unit 200.

[0074] As an example, taking the RF transceiver unit 100 as an AD9361, the AD9361 consists of multiple analog-to-digital converters and has both digital-to-analog and analog-to-digital conversion functions. The ZYNQ processing unit 200 configures the AD9361 parameters via the SPI bus, changing parameters such as the center frequency, sampling rate, down-conversion parameters, and filtering parameters (i.e., the second configuration parameters) of the digital-to-analog or analog-to-digital conversion RF signal to transmit the wireless RF signal to the outside via the analog-to-digital converter. The analog-to-digital converter is used to receive the echo signal, and the received data is transmitted to the DDR memory in the ZYNQ processing unit 200 via LVDS. The logic processing unit 204 in the ZYNQ processing unit 200 then performs data parsing processing on the data.

[0075] In one embodiment, such as Figure 3 As shown, the radio frequency transceiver unit 100 also includes a radio frequency input terminal 1001 and a radio frequency output terminal 1002, wherein the radio frequency output terminal 1002 is used to transmit radio frequency signals, and the radio frequency input terminal 1001 is used to receive echo signals corresponding to the radio frequency signals.

[0076] In one embodiment, the wireless radio frequency processing system further includes a clock unit 400 and a power supply unit 500; wherein the clock unit 400 is connected to the ZYNQ processing unit 200 and is used to generate a system clock and an input clock; the power supply unit 500 is connected to the ZYNQ processing unit 200, the radio frequency transceiver unit 100 and the coprocessor unit 300 and is used to supply power to the ZYNQ processing unit 200, the radio frequency transceiver unit 100 and the coprocessor unit 300.

[0077] Clock unit 400 includes a crystal oscillator and a clock buffer, wherein the crystal oscillator is connected to ZYNQ processing unit 200 and is used to generate a system clock for use by ZYNQ processing unit 200. In one example, the crystal oscillator is an active crystal oscillator.

[0078] The clock buffer is connected to the ZYNQ processing unit 200 and is used to receive an external clock and generate an input clock. This input clock is a clock suitable for the ZYNQ processing unit (e.g., LVDS, LVCMOS, etc.), and the frequency of the external clock can be 100MHz.

[0079] This concludes the introduction to the wireless radio frequency processing system provided in the embodiments of this application.

[0080] In this embodiment, a system architecture combining ZYNQ and DSP is used to process radio station signals. This architecture has advantages such as simple system structure, high control efficiency, and sufficient programmable resources to implement complex functions. Furthermore, the ZYNQ can control the DSP's program configuration and loading, thus meeting the requirements of system reconfigurability.

[0081] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application, and they should all be covered within the scope of the claims and specification of this application. In particular, as long as there is no structural conflict, the various technical features mentioned in the embodiments can be combined in any way. This application is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. A wireless radio frequency processing system, comprising: include: The radio frequency transceiver unit, the ZYNQ processing unit, and the coprocessing unit, wherein the ZYNQ processing unit includes a first interface and a second interface; The ZYNQ processing unit is used to convert radio frequency data into radio frequency signals; The first interface is connected to the radio frequency transceiver unit and is used to send the radio frequency signal to the radio frequency transceiver unit so that the radio frequency transceiver unit can transmit the radio frequency signal; The second interface is connected to the coprocessing unit and is used to send the first radio frequency data in the radio frequency data to the coprocessing unit; The coprocessing unit is used to receive the first radio frequency data through the second interface, convert the first radio frequency data into a first radio frequency signal, and send the first radio frequency signal to the ZYNQ processing unit through the second interface.

2. The wireless radio frequency processing system of claim 1, wherein, The ZYNQ processing unit includes a data management unit and a logic processing unit, and the logic processing unit includes the first interface and the second interface; The data management unit is connected to the logic processing unit and is used to manage the radio frequency data; The logic processing unit is connected to the radio frequency transceiver unit through the first interface, and is used to read and convert the radio frequency data into the radio frequency signal, and send the radio frequency signal to the radio frequency transceiver unit through the first interface; The logic processing unit is connected to the coprocessing unit through the second interface, and is used to send the first radio frequency data to the coprocessing unit and receive the first radio frequency signal generated by the coprocessing unit.

3. The wireless radio frequency processing system according to claim 2, characterized in that, The data management unit includes a processor, a storage unit, and an interface unit; The processor is used for data management of the radio frequency data; The storage unit is connected to the processor and is used to store the radio frequency data; The processor interacts with the off-chip storage unit and the logic processing unit through the interface unit.

4. The wireless radio frequency processing system of claim 3, wherein, The data management unit further includes a bus controller and a data packet capture unit. The interface unit includes a bus interface and a data packet capture interface. The bus interface includes a general-purpose bus interface and a high-speed bus interface. The high-speed bus interface is connected between the bus controller and the logic processing unit and is used to transmit control signals output by the bus controller. The general-purpose bus interface is connected between the storage unit and the logic processing unit, and is used to transmit the radio frequency data stored in the storage unit to the logic processing unit; The packet capture interface is connected between the packet capture unit and the logic processing unit, and is used to transmit a first configuration parameter from the packet capture unit to the logic processing unit. The first configuration parameter is a parameter for configuring the bitstream program of the logic processing unit.

5. The wireless radio frequency processing system of claim 4, wherein, The interface unit also includes a debug network port, a debug serial port, and a joint test workgroup interface; The debugging network port is connected between the data management unit and the Ethernet interface chip; The debugging serial port is connected between the data management unit and the external program debugging device; The joint test working group interface connects the data management unit to the external test equipment.

6. The wireless radio frequency processing system of any of claims 1 to 5, wherein, The first interface includes a low-voltage differential interface and a parameter configuration interface; The low-voltage differential interface is connected between the ZYNQ processing unit and the RF transceiver unit, and is used to transmit interactive data between the ZYNQ processing unit and the RF transceiver unit; The parameter configuration interface is connected between the ZYNQ processing unit and the RF transceiver unit, and is used to transmit a second configuration parameter, which is a parameter configured by the ZYNQ processing unit for the RF transceiver unit.

7. The wireless radio frequency processing system of claim 6, wherein, The radio frequency transceiver unit includes multiple analog-to-digital converters; Multiple analog-to-digital converters are connected to the ZYNQ processing unit via the low-voltage differential interface for performing analog-to-digital conversion on the radio frequency signals output by the ZYNQ processing unit.

8. The wireless radio frequency processing system of claim 7, wherein, The radio frequency transceiver unit also includes a radio frequency input terminal and a radio frequency output terminal; The radio frequency output terminal is used to transmit the radio frequency signal; The radio frequency input terminal is used to receive the echo signal corresponding to the radio frequency signal.

9. The wireless radio frequency processing system of claim 1, wherein, The wireless radio frequency processing system also includes: a clock unit and a power supply unit; The clock unit is connected to the ZYNQ processing unit and is used to generate the system clock and input clock. The power supply unit is connected to the ZYNQ processing unit, the RF transceiver unit, and the coprocessor unit, and is used to supply power to the ZYNQ processing unit, the RF transceiver unit, and the coprocessor unit.

10. The wireless radio frequency processing system of claim 9, wherein, The clock unit includes a crystal oscillator and a clock buffer; The crystal oscillator is connected to the ZYNQ processing unit and is used to generate a system clock for the ZYNQ processing unit. The clock buffer is connected to the ZYNQ processing unit and is used to receive an external clock and generate the input clock.

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