Transmitting and receiving circuit and transmitting and receiving device for clock synchronization

Abstract

A transceiver circuit includes: a clock adjustment module (A), a frequency and phase detector (B), and a first phase-locked loop (C); a first input terminal of A is coupled to the input terminal of the transceiver circuit, a first output terminal of A is connected to the first input terminal of B, the output terminal of B is connected to the input terminal of C, and the output terminal of C is connected to the second input terminal of A and the second input terminal of B; B is used to determine the frequency difference between the current receiving clock signal of the transceiver circuit and the clock signal output by C at the previous moment; C is used to output a first clock signal according to the frequency difference; A is used to determine the phase difference between the clock signal of a first transceiver device and the current clock signal of the transceiver circuit; and adjust the first clock signal according to the phase difference to obtain a second clock signal, the second clock signal being synchronized with the clock signal of the first transceiver device; and update the receiving clock signal of the transceiver circuit to the second clock signal, the second clock signal being used to receive data from the first transceiver device.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and more particularly to a transceiver circuit and transceiver for clock synchronization. Background Technology

[0002] Typically, during data transmission between electronic devices, the data receiving device needs to synchronize its clock signal with the data sending device (also known as clock synchronization) so that the data receiving device and the data sending device can communicate based on the synchronized clock signal.

[0003] One existing method for clock synchronization involves configuring a master clock device that provides a reference clock signal to each of a plurality of transceiver devices. This allows the transceiver devices to transmit data based on the reference clock signal. For example, a second transceiver device sends data to a first transceiver device using the reference clock signal provided by the master clock device, while the first transceiver device receives data from the second transceiver device using the reference clock signal provided by the master clock device. In other words, the master clock device provides the same clock signal to both the first and second transceiver devices, thus synchronizing their clock signals.

[0004] The above clock synchronization method requires a separate master clock device, which also requires a separate physical clock line to connect the master clock device with multiple transceiver devices, thus occupying the interface resources of the transceiver devices. Summary of the Invention

[0005] This application provides a transceiver circuit and transceiver device for clock synchronization, which can achieve clock synchronization between transceiver devices without occupying the interface resources of the transceiver devices.

[0006] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0007] In a first aspect, embodiments of this application provide a transceiver circuit, including: a clock adjustment module, a frequency and phase detector, and a first phase-locked loop; wherein, a first input terminal of the clock adjustment module is coupled to the input terminal of the transceiver circuit, a first output terminal of the clock adjustment module is connected to the first input terminal of the frequency and phase detector, the output terminal of the frequency and phase detector is connected to the input terminal of the first phase-locked loop, and the output terminal of the first phase-locked loop is connected to the second input terminal of the clock adjustment module and the second input terminal of the frequency and phase detector;

[0008] The aforementioned frequency and phase detector is used to determine the frequency difference between the current received clock signal of the transceiver circuit and the clock signal output by the first phase-locked loop at the previous moment.

[0009] The aforementioned first phase-locked loop is used to output a first clock signal based on the aforementioned frequency difference;

[0010] The aforementioned clock adjustment module is used to determine the phase difference between the clock signal of the first transceiver device and the current clock signal of the transceiver circuit; and to adjust the first clock signal according to the phase difference to obtain a second clock signal, which is synchronized with the clock signal of the first transceiver device; and to update the receiving clock signal of the transceiver circuit to the second clock signal, which is used to receive data from the first transceiver device.

[0011] The transceiver circuit for clock synchronization provided in this application embodiment determines the frequency difference between the current received clock signal and the clock signal output by the first phase-locked loop (PLL) in the transceiver circuit at the previous moment using a frequency detector and a phase-locked loop (PLL) in the transceiver circuit. The first PLL outputs a first clock signal based on this frequency difference. Then, a clock adjustment module in the transceiver circuit adjusts the first clock signal based on the phase difference between the clock signal of the first transceiver device and the clock signal output by the first PLL in the transceiver circuit at the previous moment, obtaining a second clock signal that is synchronized with the clock signal of the first transceiver device. Compared to the prior art, the transceiver circuit for clock synchronization provided in this application embodiment does not require a master clock device to provide a reference clock signal. Therefore, it does not occupy the interface resources of the transceiver device during clock synchronization. In other words, the transceiver circuit for clock synchronization provided in this application embodiment can achieve synchronization without occupying the interface resources of the transceiver device.

[0012] In one possible implementation, the clock adjustment module may include: a phase detection module and a first phase interpolator; the first input terminal of the phase detection module is coupled to the first input terminal of the clock adjustment module, the output terminal of the phase detection module is connected to the first input terminal of the first phase interpolator, the second input terminal of the first phase interpolator is coupled to the second input terminal of the clock adjustment module, the output terminal of the first phase interpolator is coupled to the first output terminal of the clock adjustment module, and the output terminal of the first phase interpolator is connected to the second input terminal of the phase detection module;

[0013] The aforementioned phase detection module is used to determine the phase difference between the clock signal of the first transceiver device and the current clock signal of the transceiver circuit.

[0014] The aforementioned first phase interpolator is used to adjust the first clock signal according to the aforementioned phase difference to obtain the second clock signal.

[0015] In one possible implementation, the transceiver circuit further includes an analog-to-digital converter, the input of which is coupled to the input of the transceiver circuit, and the output of which is connected to the input of the clock adjustment module.

[0016] The aforementioned analog-to-digital converter is used to convert the clock signal of the first transceiver device from an analog signal to a digital signal.

[0017] In one possible implementation, the transceiver circuit further includes a second phase interpolator, the first input of which is connected to the output of the first phase-locked loop, the second input of which is connected to the second output of the clock adjustment module, and the output of the phase detection module is coupled to the second output of the clock adjustment module.

[0018] The second phase interpolator is used to adjust the first clock signal according to the phase difference output by the second output terminal of the clock adjustment module to obtain a third clock signal, which is synchronized with the clock signal of the first transceiver device; and to update the transmit clock signal of the transceiver circuit to the third clock signal, which is used to transmit data to the first transceiver device.

[0019] In one possible implementation, the transceiver circuit further includes: a second phase interpolator and a second phase-locked loop, the input of the second phase-locked loop being connected to the output of the frequency and phase detector, the output of the second phase-locked loop being connected to the first input of the second phase interpolator, the second input of the second phase interpolator being connected to the second output of the clock adjustment module, and the output of the phase detector being coupled to the second output of the clock adjustment module.

[0020] The second phase-locked loop described above is used to output a fourth clock signal based on the frequency difference described above;

[0021] The second phase interpolator is used to adjust the fourth clock signal according to the phase difference output by the second output terminal of the clock adjustment module to obtain a fifth clock signal, which is synchronized with the clock signal of the first transceiver device; and to update the transmit clock signal of the transceiver circuit to the fifth clock signal, which is used to transmit data to the first transceiver device.

[0022] Secondly, embodiments of this application provide another transceiver circuit, including: a clock adjustment module, a low-pass filter, and a first phase-locked loop; wherein, a first input terminal of the clock adjustment module is coupled to the input terminal of the transceiver circuit, a first output terminal of the clock adjustment module is connected to the input terminal of the low-pass filter, the output terminal of the low-pass filter is connected to the input terminal of the first phase-locked loop, and the output terminal of the first phase-locked loop is connected to the second input terminal of the clock adjustment module.

[0023] The aforementioned low-pass filter is used to determine the frequency difference between the current receiving clock signal of the transceiver circuit and the receiving clock signal of the transceiver circuit at the previous moment.

[0024] The aforementioned first phase-locked loop is used to output a first clock signal based on the aforementioned frequency difference;

[0025] The aforementioned clock adjustment module is used to determine a first phase difference based on the clock signal of the first transceiver device and the current receiving clock signal of the transceiver circuit; and to adjust the first clock signal based on the first phase difference to obtain a second clock signal, the second clock signal being synchronized with the clock signal of the first transceiver device; and to update the receiving clock signal of the transceiver circuit to the second clock signal, the second clock signal being used to receive data from the first transceiver device.

[0026] The transceiver circuit for clock synchronization provided in this application embodiment determines the frequency difference between the current received clock signal of the transceiver circuit and the received clock signal of the transceiver circuit at the previous moment using a low-pass filter. This frequency difference is then sent to a first phase-locked loop (PLL). The first PLL adjusts the received clock signal of the transceiver circuit at the previous moment based on this frequency difference, outputting a first clock signal. This achieves frequency synchronization between the clock signal output by the first PLL at the previous moment and the current received clock signal of the transceiver circuit. Then, a clock adjustment module determines a first phase difference based on the clock signal of the first transceiver device and the current received clock signal of the transceiver circuit. The first clock signal is then adjusted based on this first phase difference to obtain a second clock signal, which is synchronized with the clock signal of the first transceiver device. Compared to existing technologies, the transceiver circuit for clock synchronization provided in this application embodiment does not require a master clock device to provide a reference clock signal. Therefore, it does not occupy the interface resources of the transceiver device during clock synchronization. In other words, the transceiver circuit for clock synchronization provided in this application embodiment can achieve clock synchronization between transceiver devices without occupying the interface resources of the transceiver device.

[0027] In one possible implementation, the low-pass filter is specifically used to determine the frequency difference between the current receiving clock signal of the transceiver circuit and the receiving clock signal of the transceiver circuit at the previous moment, based on the phase difference between the current receiving clock signal of the transceiver circuit output by the clock adjustment module and the receiving clock signal of the transceiver circuit at the previous moment.

[0028] In one possible implementation, the clock adjustment module includes a phase detection module and a first phase interpolator; the first input terminal of the phase detection module is coupled to the first input terminal of the clock adjustment module, the first output terminal of the phase detection module is coupled to the first output terminal of the clock adjustment module, the second output terminal of the phase detection module is connected to the first input terminal of the first phase interpolator, the second input terminal of the first phase interpolator is coupled to the second input terminal of the clock adjustment module, and the output terminal of the first phase interpolator is connected to the second input module of the phase detection module.

[0029] The aforementioned phase detection module is used to determine the first phase difference based on the clock signal of the first transceiver device and the current receiving clock signal of the transceiver circuit.

[0030] The aforementioned first phase interpolator is used to adjust the first clock signal according to the aforementioned first phase difference to obtain the second clock signal.

[0031] In one possible implementation, the transceiver circuit further includes an analog-to-digital converter (ADC), the input of which is coupled to the input of the transceiver circuit, and the output of which is connected to the input of the clock adjustment module.

[0032] The aforementioned analog-to-digital converter is used to convert the clock signal of the first transceiver device from an analog signal to a digital signal.

[0033] In one possible implementation, the transceiver circuit further includes a second phase interpolator, the first input of which is connected to the output of the first phase-locked loop, the second input of which is connected to the second output of the clock adjustment module, and the output of the phase detection module is also coupled to the second output of the clock adjustment module.

[0034] The second phase interpolator is used to adjust the first clock signal according to the second phase difference output by the second output terminal of the clock adjustment module to obtain the third clock signal, which is synchronized with the clock signal of the first transceiver device; and to update the transmit clock signal of the transceiver circuit to the third clock signal, which is used to transmit data to the first transceiver device.

[0035] In one possible implementation, the transceiver circuit further includes a second phase interpolator and a second phase-locked loop. The input of the second phase-locked loop is connected to the output of the low-pass filter, and the output of the second phase-locked loop is connected to the first input of the second phase interpolator. The second input of the second phase interpolator is connected to the second output of the clock adjustment module, and the output of the phase detection module is also coupled to the second output of the clock adjustment module.

[0036] The second phase-locked loop described above is used to output a fourth clock signal based on the frequency difference described above;

[0037] The second phase interpolator is used to adjust the fourth clock signal according to the phase difference output by the second output terminal of the clock adjustment module to obtain the fifth clock signal, which is synchronized with the clock signal of the first transceiver device; and to update the transmit clock signal of the transceiver circuit to the fifth clock signal, which is used to transmit data to the first transceiver device.

[0038] Thirdly, embodiments of this application provide a transceiver device, which includes the transceiver circuit described in any one of the first aspect and its possible implementations, or the transceiver circuit described in any one of the second aspect and its possible implementations. Attached Figure Description

[0039] Figure 1 A schematic diagram of a circuit system for clock synchronization provided in an embodiment of this application. Figure 1 ;

[0040] Figure 2 A schematic diagram of a phase shift provided for an embodiment of this application;

[0041] Figure 3 A schematic diagram of a transceiver circuit for clock synchronization provided in an embodiment of this application. Figure 1 ;

[0042] Figure 4 A schematic diagram of a transceiver circuit for clock synchronization provided in an embodiment of this application. Figure 2 ;

[0043] Figure 5 A schematic diagram of a transceiver circuit for clock synchronization provided in an embodiment of this application. Figure 3 ;

[0044] Figure 6 A schematic diagram of a transceiver circuit for clock synchronization provided in an embodiment of this application. Figure 4 ;

[0045] Figure 7 A schematic diagram of a transceiver circuit for clock synchronization provided in an embodiment of this application. Figure 5 ;

[0046] Figure 8 A schematic diagram of a communication system provided in this application embodiment. Figure 1 ;

[0047] Figure 9 A schematic diagram of a transceiver circuit for clock synchronization provided in an embodiment of this application. Figure 6 ;

[0048] Figure 10 A schematic diagram of a transceiver circuit for clock synchronization provided in an embodiment of this application. Figure 7 ;

[0049] Figure 11 A schematic diagram of a transceiver circuit for clock synchronization provided in an embodiment of this application. Figure 8 ;

[0050] Figure 12 A schematic diagram of a transceiver circuit for clock synchronization provided in an embodiment of this application. Figure 9 ;

[0051] Figure 13 A schematic diagram of a transceiver circuit for clock synchronization provided in an embodiment of this application. Figure 10 ;

[0052] Figure 14 A schematic diagram of a communication system provided in this application embodiment. Figure 2 ;

[0053] Figure 15 A schematic diagram of a synchronous clock signal flow provided in an embodiment of this application. Figure 1 . Detailed Implementation

[0054] In this article, the term "and / or" is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0055] The terms "first" and "second," etc., used in the specification and claims of this application are used to distinguish different objects, not to describe a specific order of objects. For example, "first clock signal" and "second clock signal," etc., are used to distinguish different clock signals, not to describe a specific order of clock signals.

[0056] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0057] In the description of the embodiments in this application, unless otherwise stated, "multiple" means two or more. For example, multiple processing units means two or more processing units; multiple systems means two or more systems.

[0058] Clock synchronization is fundamental to communication between devices; clock signal synchronization is required during data transmission between different devices. Figure 1 This is a schematic diagram of an existing clock synchronization circuit, which includes device A, device B, device C, and a master clock device. Devices A, B, and C are all transceiver devices with similar structures. Typically, a transceiver device includes a transmitting unit, a receiving unit, and a phase buffer. The transmitting unit transmits data, the receiving unit receives data, and the phase buffer stores the phase offset.

[0059] The clock signals used for sending or receiving data on devices A, B, and C are different. Therefore, the master clock device provides reference clock signals to devices A, B, and C respectively. In other words, the master clock device synchronizes the same reference clock signal to devices A, B, and C respectively, so that devices A, B, and C all use the reference clock signal provided by the master clock device to send or receive data. That is, the reference clock signal is the clock signal after the three devices have synchronized their clocks.

[0060] During data transmission based on the reference clock signal, the phase of the reference clock signal may shift due to external factors such as ambient temperature or noise. Therefore, the data transmission device needs to compensate for the phase of the reference clock signal to reduce the error between the clock signals of the three devices and ensure that the clock signals of the three devices remain synchronized. Figure 2 As shown, before device A sends data to device B, device A first obtains a phase offset 1 from the phase buffer. Then, device A adjusts the reference clock signal according to the phase offset 1 to obtain clock signal 1, and then sends data to device B according to clock signal 1. After device B obtains the actual clock signal used by device A to send data (this clock signal may be clock signal 1, or it may be a clock signal with a certain phase deviation from clock signal 1, which is caused by the influence of external factors such as ambient temperature or noise), device B calculates the phase offset 2 according to the actual clock signal and its reference clock signal. Then, device B adjusts the reference clock signal according to the phase offset 2 to obtain clock signal 2. Subsequently, device B receives the data sent by device A based on clock signal 2, and device B also sends the aforementioned phase offset 2 to device A based on clock signal 2 (it should be understood that at this time, phase offset 2 is sent to device A as a kind of data). Similarly, device A calculates phase offset 3 based on the actual clock signal used by device B to send data (which is phase offset 2) and the reference clock signal of device A. Then, device A adjusts its reference clock signal according to phase offset 3 to obtain clock signal 3. Then, device A receives phase offset 2 sent by device B based on clock signal 3, and updates the phase offset stored in the phase buffer of device A from phase offset 1 to phase offset 2 for subsequent data transmission to device B.

[0061] However, the above clock synchronization method requires a separate master clock device, which also requires a separate physical clock line to connect the master clock device with the data sending and receiving devices, thus occupying the interface resources of the data sending and receiving devices.

[0062] To address the problem in the prior art where transceiver devices occupy interface resources during clock synchronization, this application provides a transceiver circuit and transceiver device for clock synchronization, which can achieve clock synchronization between transceiver devices without occupying their interface resources.

[0063] like Figure 3 As shown, the transceiver circuit provided in this embodiment includes: a clock adjustment module 13, a frequency and phase detector 11, and a first phase-locked loop 12; the first input terminal 131 of the clock adjustment module 13 is coupled to the input terminal of the transceiver circuit, the first output terminal 132 of the clock adjustment module 13 is connected to the first input terminal 111 of the frequency and phase detector 11, the output terminal 113 of the frequency and phase detector 11 is connected to the input terminal 121 of the first phase-locked loop 12, and the output terminal 122 of the first phase-locked loop 12 is connected to the second input terminal 133 of the clock adjustment module 13 and the second input terminal 112 of the frequency and phase detector 11.

[0064] The frequency and phase detector 11 is used to determine the frequency difference between the current receiving clock signal of the transceiver circuit and the clock signal output by the first phase-locked loop 12 at the previous moment; the first phase-locked loop 12 is used to output a first clock signal according to the frequency difference; the clock adjustment module 13 is used to determine the phase difference between the clock signal of the first transceiver device and the current clock signal of the transceiver circuit; and adjust the first clock signal according to the phase difference to obtain a second clock signal; and update the receiving clock signal of the transceiver circuit to the second clock signal, which is synchronized with the clock signal of the first transceiver device, and the second clock signal is used to receive data from the first transceiver device.

[0065] In this embodiment of the application, the current receiving clock signal of the transceiver circuit (denoted as clock signal a) is used as the reference clock signal of the frequency and phase detector 11, and the clock signal output by the first phase-locked loop 12 at the previous moment (denoted as clock signal b) is used as the feedback clock signal of the frequency and phase detector 11. The frequency and phase detector 11 performs frequency discrimination on the reference clock signal and the feedback clock signal and outputs the frequency difference between the reference clock signal and the feedback clock signal.

[0066] It should be noted that, for ease of description, the application will be... Figure 3 The transceiver device in the transceiver circuit shown is called the second transceiver device.

[0067] Optionally, the frequency difference between the reference clock signal and the feedback clock signal can be represented by a frequency control word, which is used to indicate the frequency difference between clock signal a and clock signal b.

[0068] In this embodiment of the application, after the frequency difference output by the frequency and phase detector 11 is input to the first phase-locked loop 12, the first phase-locked loop 12 adjusts the frequency of the clock signal b according to the frequency difference to obtain the first clock signal, wherein the frequency of the first clock signal is the same as the frequency of the clock signal b.

[0069] The transceiver circuit for clock synchronization provided in this application embodiment determines the frequency difference between the current received clock signal and the clock signal output by the first phase-locked loop (PLL) in the transceiver circuit at the previous moment using a frequency detector and a phase-locked loop (PLL) in the transceiver circuit. The first PLL outputs a first clock signal based on this frequency difference. Then, a clock adjustment module in the transceiver circuit adjusts the first clock signal based on the phase difference between the clock signal of the first transceiver device and the clock signal output by the first PLL in the transceiver circuit at the previous moment, obtaining a second clock signal synchronized with the clock signal of the first transceiver device. Compared to the prior art, the transceiver circuit for clock synchronization provided in this application embodiment does not require a separate master clock device for providing a reference clock signal. Therefore, it does not occupy the interface resources of the transceiver device during clock synchronization. In other words, the transceiver circuit for clock synchronization provided in this application embodiment can achieve clock synchronization between transceiver devices without occupying the interface resources of the transceiver device.

[0070] Optional, combined Figure 3 ,like Figure 4 As shown, the clock adjustment module 13 includes a phase detection module 14 and a first phase interpolator 15. The first input terminal 141 of the phase detection module 14 is coupled to the first input terminal 131 of the clock adjustment module 13. The output terminal 142 of the phase detection module 14 is connected to the first input terminal 151 of the first phase interpolator 15. The second input terminal 152 of the first phase interpolator 15 is coupled to the second input terminal 133 of the clock adjustment module 13. The output terminal 153 of the first phase interpolator 15 is coupled to the first output terminal 132 of the clock adjustment module 13. The output terminal 153 of the first phase interpolator 15 is connected to the second input terminal 143 of the phase detection module 14.

[0071] The phase detection module 14 is used to determine the phase difference between the clock signal of the first transceiver device and the current clock signal of the transceiver circuit; the first phase interpolator 15 is used to adjust the first clock signal according to the phase difference to obtain the second clock signal.

[0072] It should be understood that the first phase interpolator 15 is used to adjust the first clock signal according to the phase difference to obtain the second clock signal. The adjustment of the first clock signal may include any one of the following adjustment methods A or B.

[0073] Adjustment Method A: When the frequency of the clock signal of the first transceiver device differs significantly from the frequency of the first clock signal, both the frequency and phase of the first clock signal need to be adjusted to obtain the second clock signal. Specifically, the phase of the first clock signal is shifted according to the phase difference. For example, when the phase difference is positive, the phase of the first clock signal is shifted forward (e.g., to the right along the X-axis of the coordinate system), and the shift amount is the phase difference; when the phase difference is negative, the phase of the first clock signal is shifted backward, and the shift amount is the phase difference. Since the phase difference is the integral of the frequency difference, the frequency difference between the clock signal of the first transceiver device and the first clock signal is calculated based on the phase difference. Then, the frequency of the first clock signal is adjusted according to this frequency difference. For example, when the phase difference is positive, the frequency of the first clock signal is decreased, where the decrease amount is the frequency difference; when the phase difference is negative, the frequency of the first clock signal is increased, where the increase amount is the frequency difference.

[0074] Adjustment Method B: When the frequency difference between the clock signal of the first transceiver device and the frequency of the second clock signal is small, the frequency of the first clock signal can be left unchanged (the frequency difference between the first clock signal and the clock signal of the first transceiver device is very small and negligible, i.e., the frequency of the first clock signal is considered to be approximately equal to the frequency of the first transceiver device). Only the phase of the first clock signal is adjusted to obtain the second clock signal. Specifically, the phase of the first clock signal is shifted according to the phase difference. For example, when the phase difference is positive, the phase of the first clock signal is shifted forward by the phase difference; when the phase difference is negative, the phase of the first clock signal is shifted backward by the phase difference.

[0075] Optional, combined Figure 4 ,like Figure 5 As shown, the transceiver circuit for clock synchronization provided in this application embodiment may further include: an analog-to-digital converter 16, the input terminal 161 of the analog-to-digital converter 16 being coupled to the input terminal of the transceiver circuit, and the output terminal 162 of the analog-to-digital converter 16 being connected to the input terminal 131 of the clock adjustment module 13.

[0076] The analog-to-digital converter 16 is used to convert the clock signal of the first transceiver device from an analog signal to a digital signal.

[0077] It should be understood that clock signals are usually processed in digital form. Therefore, after the transceiver circuit obtains the clock signal of the first transceiver device (which is an analog signal), the analog-to-digital converter 16 converts the clock signal of the first transceiver device from an analog signal to a digital signal, and then inputs the digital clock signal to the clock adjustment module 13.

[0078] Optionally, the transceiver circuit for clock synchronization provided in the embodiments of this application may further include a component or module for synchronizing the transmitting clock signal of the transceiver circuit. That is, during the process of the transceiver circuit receiving data sent by the first transceiver device, not only is the receiving clock signal of the transceiver circuit synchronized with the clock signal of the first transceiver device, but the transmitting clock signal of the transceiver circuit is also synchronized with the clock signal of the first transceiver circuit.

[0079] In one implementation, combining Figure 5 ,like Figure 6 As shown, the transceiver circuit for clock synchronization provided in this application embodiment further includes a second phase interpolator 17. The first input terminal 171 of the second phase interpolator 17 is connected to the output terminal 122 of the first phase-locked loop, and the second input terminal 172 of the second phase interpolator 17 is connected to the second output terminal 134 of the clock adjustment module 13. The output terminal 142 of the phase detection module 14 is coupled to the second output terminal 134 of the clock adjustment module 13.

[0080] The second phase interpolator 17 is used to adjust the first clock signal according to the phase difference output by the second output terminal 134 of the clock adjustment module 13 to obtain a third clock signal, which is synchronized with the clock signal of the first transceiver device; and to update the transmit clock signal of the transceiver circuit to the third clock signal, which is used to transmit data to the first transceiver device.

[0081] It should be understood that, similar to the process by which the first phase interpolator 15 adjusts the first clock signal according to the phase difference to obtain the second clock signal, the process by which the second phase interpolator 17 adjusts the first clock signal according to the phase difference to obtain the third clock signal may include any one of the following adjustment methods C and D.

[0082] Adjustment Method C: When the frequency of the clock signal of the first transceiver device differs significantly from the frequency of the first clock signal, both the frequency and phase of the first clock signal need to be adjusted to obtain the third clock signal. Specifically, the phase of the first clock signal is shifted according to this phase difference. Since the phase difference is the integral of the frequency difference, the frequency difference between the clock signal of the first transceiver device and the first clock signal is calculated based on this phase difference. Then, the frequency of the first clock signal is adjusted according to this frequency difference to obtain the adjusted first clock signal, i.e., the third clock signal.

[0083] It should be understood that the above adjustment method C is similar to the above adjustment method A, and for details, please refer to the relevant description of adjustment method A in the above embodiments.

[0084] Adjustment Method D: When the frequency of the clock signal of the first transceiver device and the frequency of the first clock signal are relatively close, only the phase of the first clock signal is adjusted to obtain the third clock signal. Specifically, the phase of the first clock signal is shifted according to this phase difference to obtain the adjusted first clock signal, i.e., the third clock signal.

[0085] It should be understood that the above adjustment method D is similar to the above adjustment method B, and the specific details can be found in the relevant description of adjustment method B in the above embodiments.

[0086] Optionally, the second transceiver device using the transceiver circuit provided in the embodiments of this application includes a transmitting unit and a receiving unit. It should be understood that the clock adjustment module 13 in the transceiver circuit is disposed on the receiving unit, and the second phase interpolator 17 is disposed on the transmitting unit.

[0087] It should be noted that after the second phase interpolator 17 obtains the phase difference between the clock signal of the first transceiver device and the first clock signal, it can store the phase difference in the cache table (e.g., look-up table, LUT) corresponding to the second phase interpolator 17. When the second transceiver device sends data to the first transceiver device, the second phase interpolator 17 reads the phase difference from the LUT table and adjusts the first clock signal according to the phase difference to obtain the third clock signal. Thus, the second transceiver device sends data to the first transceiver device according to the third clock signal.

[0088] Optionally, before the phase difference between the clock signal of the first transceiver device and the first clock signal is input to the second phase interpolator 17, the phase detection module 14 in the clock adjustment module 13 filters the phase difference (i.e., the phase detection module 14 includes a filter), and then the first phase interpolator 15 adjusts the first clock signal according to the filtered phase difference (i.e., a more accurate phase difference); at the same time, the phase difference stored in the cache table corresponding to the second phase interpolator 17 is also the filtered phase difference.

[0089] In another implementation, combining Figure 5 ,like Figure 7 As shown, the transceiver circuit for clock synchronization provided in this application embodiment may further include: a second phase interpolator 17 and a second phase-locked loop 18. The input terminal 181 of the second phase-locked loop 18 is connected to the output terminal 113 of the frequency and phase detector 11. The output terminal 182 of the second phase-locked loop 18 is connected to the first input terminal 171 of the second phase interpolator 17. The second input terminal 172 of the second phase interpolator 17 is connected to the second output terminal 134 of the clock adjustment module 13. The output terminal 142 of the phase detector module 14 is coupled to the second output terminal 134 of the clock adjustment module 13.

[0090] The second phase-locked loop 18 is used to output a fourth clock signal based on the frequency difference between the current receiving clock signal of the transceiver circuit and the receiving clock signal of the transceiver circuit at the previous moment; the second phase interpolator 17 is used to adjust the fourth clock signal based on the phase difference output by the second output terminal 134 of the clock adjustment module 13 to obtain a fifth clock signal, which is synchronized with the clock signal of the first transceiver device; and to update the transmitting clock signal of the transceiver circuit to the fifth clock signal, which is used to send data to the first transceiver device.

[0091] It should be noted that the fourth clock signal and the first clock signal mentioned above are both clock signals output based on the frequency difference between the current receiving clock signal of the transceiver circuit and the clock signal output by the first phase-locked loop 12 at the previous moment. Therefore, the fourth clock signal and the first clock signal mentioned above are completely identical clock signals.

[0092] It should be understood that the second phase interpolator 17 is used to adjust the fourth clock signal according to the phase difference to obtain the fifth clock signal. The adjustment of the fourth clock signal may include any one of the following adjustment methods E and F.

[0093] Adjustment method E: When the frequency of the clock signal of the first transceiver device differs significantly from the frequency of the fourth clock signal, both the frequency and phase of the fourth clock signal need to be adjusted to obtain the fifth clock signal. Adjustment method E is similar to adjustment method A; please refer to the relevant description of adjustment method A in the above embodiments for details.

[0094] Adjustment method F: When the frequency difference between the clock signal of the first transceiver device and the frequency of the fourth clock signal is small, only the phase of the fourth clock signal is adjusted to obtain the fifth clock signal. Adjustment method F is similar to adjustment method B, and the specific details can be found in the description of adjustment method B in the above embodiments.

[0095] Accordingly, embodiments of this application provide a transceiver device, which includes, as follows: Figures 3-7 Any of the transceiver circuits shown can enable clock synchronization between transceiver devices with this structural feature.

[0096] The following describes in detail the process of synchronizing clock signals when transmitting data between the above-mentioned transceivers, taking a communication system consisting of multiple transceivers (e.g., a first transceiver and a second transceiver) including the transceiver circuit provided in the embodiments of this application as an example.

[0097] like Figure 8As shown, when the first transceiver sends first data to the second transceiver based on its own clock signal, the specific process by which the transceiver circuit corresponding to the second transceiver synchronizes the clock signal of the first transceiver is as follows: The clock adjustment module in the second transceiver determines the phase difference 1 between the clock signal corresponding to the first data and the current receiving clock signal of the second transceiver; the clock adjustment module adjusts the phase and frequency of the clock signal output by the first phase-locked loop at the previous moment based on the phase difference 1 to obtain clock signal 1, wherein clock signal 1 is synchronized with the clock signal of the first transceiver; at this time, the clock adjustment module updates the current receiving clock signal of the second transceiver to clock signal 1. Furthermore, the clock adjustment module of the second transceiver sends the phase difference 1 to the second phase difference unit of the second transceiver; simultaneously, the clock adjustment module of the second transceiver sends the clock signal 1 to the frequency and phase detector. The frequency and phase detector determines the frequency difference 1 between the two clock signals based on the clock signal 1 and the clock signal output by the first phase-locked loop at the previous moment. The frequency and phase detector sends the frequency difference 1 to the first phase-locked loop. The first phase-locked loop adjusts the frequency of the clock signal output by the first phase-locked loop at the previous moment based on the frequency difference 1 to obtain clock signal 2. The frequency of clock signal 2 is synchronized with that of clock signal 1. The first phase-locked loop sends clock signal 2 to the transmitting and receiving units of the second transceiver so that when the first transceiver sends the second data to the second transceiver, the clock adjustment module adjusts clock signal 2 based on the phase difference 2 to recover the clock signal corresponding to the second data.

[0098] When the first transceiver sends second data to the second transceiver, the phase of the clock signal for the transmitted data may shift due to external factors. Therefore, when the first transceiver sends the second data to the second transceiver, the second transceiver needs to continue to synchronously send the clock signal corresponding to the second data. The synchronization process of the clock signal is as follows: the clock adjustment module in the second transceiver determines the phase difference 2 between the clock signal corresponding to the second data and the current receiving clock signal of the second transceiver (i.e., clock signal 1). The clock adjustment module adjusts the phase and frequency of the clock signal 2 output by the first phase-locked loop at the previous moment according to the phase difference 2 to obtain the clock signal 3. It should be noted that the frequency of the clock signal 3 is synchronized with that of the first transceiver. Therefore, the frequency adjustment of the clock signal 3 by the clock adjustment module according to the phase difference 2 is very small and can be ignored. Then, the clock adjustment module updates the current receiving clock signal (i.e., clock signal 1) of the second transceiver to clock signal 3. Furthermore, the clock adjustment module sends the phase difference 2 to the transmitting unit of the second transceiver. Simultaneously, the clock adjustment module sends clock signal 3 to the frequency and phase detector. The frequency and phase detector determines the frequency difference 2 between clock signal 3 and clock signal 2 output by the first phase-locked loop (PLL) at the previous moment. The frequency detector sends the frequency difference 2 to the first PLL. The first PLL adjusts the frequency of clock signal 2 output by the first PLL at the previous moment according to the frequency difference 2 to obtain clock signal 4, wherein clock signal 4 is synchronized with the frequency of clock signal 3. The first PLL sends clock signal 4 to the transmitting and receiving units of the second transceiver.

[0099] When the transmitting unit of the second transceiver receives clock signal 2 and phase difference 1, it synchronizes clock signal 2 and stores the phase difference in its corresponding buffer table. When the transmitting unit of the second transceiver receives clock signal 4 and phase difference 2, it synchronizes clock signal 4 and updates the phase difference 1 corresponding to the first transceiver in the buffer table to phase difference 2. When the second transceiver sends data to the first transceiver, the second phase interpolator in the transmitting unit of the second transceiver adjusts clock signal 4 according to phase difference 2 to obtain clock signal 5, and uses clock signal 5 to send data to the first transceiver, wherein clock signal 5 is synchronized with the clock signal of the first transceiver.

[0100] To address the problem in the prior art where transceiver devices occupy interface resources during clock synchronization, this application provides another transceiver circuit and transceiver device for clock synchronization, which can achieve clock synchronization between transceiver devices without occupying interface resources.

[0101] like Figure 9As shown, the transceiver circuit provided in this embodiment includes: a clock adjustment module 23, a low-pass filter 21, and a first phase-locked loop 22; wherein, the first input terminal 231 of the clock adjustment module 23 is coupled to the input terminal of the transceiver circuit, the first output terminal 232 of the clock adjustment module 23 is connected to the input terminal 211 of the low-pass filter 21, the output terminal 212 of the low-pass filter 21 is connected to the input terminal 221 of the first phase-locked loop 22, and the output terminal 222 of the first phase-locked loop 22 is connected to the second input terminal 233 of the clock adjustment module 23.

[0102] The low-pass filter 21 is used to determine the frequency difference between the current receiving clock signal of the transceiver circuit and the receiving clock signal of the transceiver circuit at the previous moment; the first phase-locked loop 22 is used to output a first clock signal according to the frequency difference; the clock adjustment module 23 is used to determine a first phase difference according to the clock signal of the first transceiver device and the current receiving clock signal of the transceiver circuit; and adjust the first clock signal according to the first phase difference to obtain a second clock signal, which is synchronized with the clock signal of the first transceiver device; and update the receiving clock signal of the transceiver circuit to the second clock signal, which is used to receive data from the first transceiver device.

[0103] In this embodiment, the low-pass filter 21 is specifically used to determine the frequency difference between the current received clock signal of the transceiver circuit and the received clock signal of the transceiver circuit at the previous moment, based on the phase difference between the current received clock signal of the transceiver circuit output by the clock adjustment module 23 and the received clock signal of the transceiver circuit at the previous moment. The method for determining this frequency difference specifically includes: calculating the frequency difference between the current received clock signal of the transceiver circuit and the received clock signal of the transceiver circuit at the previous moment based on the relationship that the phase difference is the integral of the frequency difference.

[0104] It should be understood that the aforementioned first phase-locked loop 22 is specifically used to adjust the frequency of the clock signal output by the first phase-locked loop 22 at the previous moment based on the frequency difference between the current receiving clock of the transceiver circuit and the receiving clock signal of the transceiver circuit at the previous moment. For example, when the phase difference is positive, the frequency of the clock signal output by the first phase-locked loop 22 at the previous moment is decreased, where the decrease is the frequency difference; when the phase difference is negative, the frequency of the clock signal output by the first phase-locked loop 22 at the previous moment is increased, where the increase is the frequency difference; thereby obtaining a first clock signal. This first clock signal is synchronized with the frequency of the current receiving clock of the transceiver circuit.

[0105] Optionally, the frequency difference can be represented by a frequency control word, which indicates the frequency difference between the current receiving clock of the transceiver circuit and the receiving clock signal of the transceiver circuit at the previous moment.

[0106] It should be understood that the above-described method of adjusting the first clock signal according to the phase difference to obtain the second clock signal, wherein the specific method of adjusting the first clock signal can be referred to the relevant description of the above embodiment, and will not be repeated here.

[0107] The transceiver circuit for clock synchronization provided in this application embodiment determines the frequency difference between the current received clock signal of the transceiver circuit and the received clock signal of the transceiver circuit at the previous moment using a low-pass filter. This frequency difference is then sent to a first phase-locked loop (PLL). The first PLL adjusts the received clock signal of the transceiver circuit at the previous moment based on this frequency difference, outputting a first clock signal. This achieves frequency synchronization between the clock signal output by the first PLL at the previous moment and the current received clock signal of the transceiver circuit. Then, a clock adjustment module determines a first phase difference based on the clock signal of the first transceiver device and the current received clock signal of the transceiver circuit. The first clock signal is then adjusted based on this first phase difference to obtain a second clock signal, which is synchronized with the clock signal of the first transceiver device. Compared to existing technologies, the transceiver circuit for clock synchronization provided in this application embodiment does not require a master clock device to provide a reference clock signal. Therefore, it does not occupy the interface resources of the transceiver device during clock synchronization. In other words, the transceiver circuit for clock synchronization provided in this application embodiment can achieve clock synchronization between transceiver devices without occupying the interface resources of the transceiver device.

[0108] Optional, combined Figure 9 ,like Figure 10 As shown, the clock adjustment module 23 specifically includes: a phase detection module 30 and a first phase interpolator 31; the first input terminal 301 of the phase detection module 30 is coupled to the first input terminal 231 of the clock adjustment module, the first output terminal 302 of the phase detection module 30 is coupled to the first output terminal 232 of the clock adjustment module 23, the second output terminal 303 of the phase detection module 30 is connected to the first input terminal 311 of the first phase interpolator 31, the second input terminal 312 of the first phase interpolator 31 is coupled to the second input terminal 233 of the clock adjustment module 23, and the output terminal 313 of the first phase interpolator 31 is connected to the second input module 304 of the phase detection module 30.

[0109] The phase detection module 30 is used to determine the first phase difference based on the clock signal of the first transceiver device and the current receiving clock signal of the transceiver circuit; the first phase interpolator 31 is used to adjust the first clock signal according to the first phase difference to obtain the second clock signal.

[0110] Optionally, both the first output terminal 302 and the second output terminal 303 of the phase detection module 30 are used to output the phase difference. The phase difference output by the first output terminal 302 of the phase detection module 30 can be represented by a phase code word, which is used to indicate the phase difference between the clock signal of the first transceiver device and the current receiving clock signal of the transceiver circuit.

[0111] Optional, combined Figure 10 ,like Figure 11 As shown, the transceiver circuit for clock synchronization provided in this application embodiment may further include: an analog-to-digital converter 24, the input terminal 241 of the analog-to-digital converter 24 being coupled to the input terminal of the transceiver circuit, and the output terminal 242 of the analog-to-digital converter being connected to the input terminal 231 of the clock adjustment module 23.

[0112] The analog-to-digital converter 24 is used to convert the clock signal of the first transceiver device from an analog signal to a digital signal.

[0113] It should be understood that clock signals are usually processed in digital form. Therefore, after the transceiver circuit obtains the clock signal of the first transceiver device (which is an analog signal), the analog-to-digital converter 24 converts the clock signal of the first transceiver device from an analog signal to a digital signal, and then inputs the digital clock signal to the clock adjustment module 23.

[0114] Optionally, the transceiver circuit for clock synchronization provided in the embodiments of this application may further include a component or module for synchronizing the transmitting clock signal of the transceiver circuit. That is, during the process of the transceiver circuit receiving data sent by the first transceiver device, not only is the receiving clock signal of the transceiver circuit synchronized with the clock signal of the first transceiver device, but the transmitting clock signal of the transceiver circuit is also synchronized with the clock signal of the first transceiver circuit.

[0115] In one implementation, combined with Figure 11 ,like Figure 12 As shown, the transceiver circuit for clock synchronization provided in this application embodiment may further include: a second phase interpolator 25, the first input terminal 251 of the second phase interpolator 25 being connected to the output terminal 222 of the first phase-locked loop 22, the second input terminal 252 of the second phase interpolator 25 being connected to the second output terminal 234 of the clock adjustment module 23, and the output terminal 303 of the phase detection module 30 being coupled to the second output terminal 234 of the clock adjustment module 23.

[0116] The second phase interpolator 25 is used to adjust the first clock signal according to the second phase difference output by the second output terminal 234 of the clock adjustment module 23 to obtain a third clock signal, which is synchronized with the clock signal of the first transceiver device; and to update the transmitting clock signal of the transceiver circuit to the third clock signal, which is used to transmit data to the first transceiver device.

[0117] It should be understood that the above-mentioned method of adjusting the first clock signal according to the second phase difference to obtain the third clock signal, wherein the specific method of adjusting the first clock signal can be referred to the relevant description of the above embodiment, and will not be repeated here.

[0118] Optionally, the transceiver device corresponding to the transceiver circuit provided in this application embodiment includes a transmitting unit and a receiving unit. It should be understood that the clock adjustment module 23 in the above transceiver circuit is disposed on the receiving unit, and the second phase interpolator 25 is disposed on the transmitting unit.

[0119] It should be noted that after the second phase interpolator 25 obtains the first clock signal and the second phase difference, it will synchronize the first clock signal and store the second phase difference in the cache table corresponding to the second phase interpolator 25. Whenever the transceiver circuit sends data to the first transceiver device, the second phase interpolator 25 adjusts the first clock signal according to the second phase difference to obtain the third clock signal, which is used to send data to the first transceiver device.

[0120] Optionally, before the second phase difference is input to the second phase interpolator 25, the phase detection module 30 in the clock adjustment module 23 (which includes a filter) filters the phase difference, and then the first phase interpolator 31 adjusts the first clock signal according to the filtered second phase difference (i.e., a more accurate phase difference); at the same time, the phase difference stored in the cache table corresponding to the second phase interpolator 25 is also the filtered second phase difference.

[0121] In another implementation, combining Figure 11 ,like Figure 13 As shown; the transceiver circuit for clock synchronization provided in this application embodiment may further include: a second phase interpolator 25 and a second phase-locked loop 26, the input terminal 261 of the second phase-locked loop 26 is connected to the output terminal 212 of the low-pass filter 21, the output terminal 262 of the second phase-locked loop 26 is connected to the first input terminal 251 of the second phase interpolator 25, the second input terminal 252 of the second phase interpolator 25 is connected to the second output terminal 234 of the clock adjustment module 23, and the output terminal 303 of the phase detection module 30 is also coupled to the second output terminal 234 of the clock adjustment module 23.

[0122] The second phase-locked loop 26 is used to output a fourth clock signal based on the frequency difference between the current receiving clock signal of the transmitting circuit and the receiving clock signal of the transmitting circuit at the previous moment; the second phase interpolator 25 is used to adjust the fourth clock signal based on the phase difference output by the second output terminal 234 of the clock adjustment module 23 to obtain a fifth clock signal, which is synchronized with the clock signal of the first transceiver device; and to update the transmitting clock signal of the transceiver circuit to the fifth clock signal, which is used to send data to the first transceiver device.

[0123] It should be understood that the aforementioned fourth clock signal and the first clock signal are both output clock signals based on the frequency difference between the current receiving clock signal of the transmitting circuit and the receiving clock signal of the transmitting circuit at the previous moment. Therefore, the aforementioned fourth clock signal and the first clock signal are exactly the same clock signals.

[0124] Accordingly, embodiments of this application provide a transceiver device, which includes, as follows: Figures 9-13 Any of the transceiver circuits shown can enable clock synchronization between transceiver devices with this structural feature.

[0125] The following describes in detail the process of clocking signals during data transmission between the aforementioned transceivers, taking a communication system consisting of multiple transceiver devices (e.g., a first transceiver device and a second transceiver device) including the transceiver circuit provided in the embodiments of this application as an example.

[0126] like Figure 14As shown, when the first transceiver sends first data to the second transceiver, the clock adjustment module in the second transceiver determines the phase difference 1 between the clock signal corresponding to the first data and the current receiving clock signal of the second transceiver. The clock adjustment module adjusts the phase and frequency of the clock signal output by the first phase-locked loop (PLL) at the previous moment based on the phase difference 1 to obtain clock signal 1, which is synchronized with the clock signal of the first transceiver. At this time, the clock adjustment module updates the current receiving clock signal of the second transceiver to clock signal 1. Furthermore, the clock adjustment module sends the phase difference 1 to the transmitting unit and low-pass filter of the second transceiver. The low-pass filter determines the frequency difference 1 between the clock signal corresponding to the first data and the current receiving clock signal (the receiving clock signal before the update) of the second transceiver based on the phase difference 1, and sends the frequency difference 1 to the first PLL. The first phase-locked loop adjusts the frequency of the clock signal output by the first phase-locked loop at the previous moment according to the frequency difference 1 to obtain clock signal 2. The frequency of clock signal 2 is synchronized with that of clock signal 1. The first phase-locked loop sends clock signal 2 to the transmitting and receiving units of the second transceiver device so that when the first transceiver device sends the second data to the second transceiver device, the clock adjustment module adjusts clock signal 2 according to the phase difference 2 to recover the clock signal corresponding to the second data.

[0127] When the first transceiver sends second data to the second transceiver, the phase of the clock signal for this data may shift due to external factors. Therefore, when the first transceiver sends the second data, the second transceiver needs to continue synchronizing the clock signal corresponding to the second data. The synchronization process is as follows: the clock adjustment module in the second transceiver determines the phase difference 2 between the clock signal corresponding to the second data and the current receiving clock signal (i.e., clock signal 1) of the second transceiver; the clock adjustment module adjusts the phase of the clock signal 2 output by the first phase-locked loop at the previous moment based on the phase difference 2. The clock signal 3 is obtained by adjusting the frequency of the clock signal 3. It should be noted that clock signal 3 is synchronized with the frequency of the first transceiver device; therefore, the frequency adjustment of clock signal 3 by the clock adjustment module based on the phase difference 2 is negligible. Then, the clock adjustment module updates the current received clock signal of the second transceiver device (i.e., clock signal 1) to clock signal 3. Furthermore, the clock adjustment module sends the phase difference 2 to the transmitting unit and low-pass filter of the second transceiver device. The low-pass filter determines the frequency difference 2 between the clock signal corresponding to the second data and the clock signal 2 output by the first phase-locked loop at the previous moment, and sends the frequency difference 2 to the first phase-locked loop. The first phase-locked loop adjusts the frequency of the clock signal 2 output by the first phase-locked loop at the previous moment based on the frequency difference 2, obtaining clock signal 4, which is synchronized with the frequency of clock signal 3. The first phase-locked loop then sends clock signal 4 to the transmitting and receiving units of the second transceiver device.

[0128] When the transmitting unit of the second transceiver receives clock signal 2 and phase difference 1, it synchronizes clock signal 2 and stores the phase difference in its corresponding buffer table. When the transmitting unit of the second transceiver receives clock signal 4 and phase difference 2, it synchronizes clock signal 4 and updates the phase difference 1 corresponding to the first transceiver in the buffer table to phase difference 2. When the second transceiver sends data to the first transceiver, the second phase interpolator in the transmitting unit of the second transceiver adjusts clock signal 4 according to phase difference 2 to obtain clock signal 5, and uses clock signal 5 to send data to the first transceiver, wherein clock signal 5 is synchronized with the clock signal of the first transceiver.

[0129] like Figure 15This is a flowchart illustrating the transceiver circuit provided in this application embodiment during synchronization of the peer's clock signal. When a first transceiver device is added to the transceiver system, the second transceiver device periodically sends a random code to the first transceiver device. This random code can be the first data or the second data described in the above embodiment, or it can be other non-service data, thereby synchronizing the receiving clock signal of the first transceiver device with the transmitting clock signal of the second transceiver device. When the second transceiver device sends service data to the first transceiver device, since the receiving clock signal of the first transceiver device is already synchronized with the transmitting clock signal of the second transceiver device, and since external factors such as ambient temperature and ambient noise have a greater impact on the clock signal than on the phase, the first transceiver device adjusts the phase of its current receiving clock signal based on the phase difference between the receiving clock signal and the clock signal corresponding to the service data, thus synchronizing the receiving clock signal of the first transceiver device with the clock signal corresponding to the service data. The first transceiver device then obtains the service data sent by the second transceiver device based on this synchronized receiving clock signal.

[0130] Through the above description of the embodiments, those skilled in the art will clearly understand that, for the sake of convenience and brevity, only the division of the above functional modules is used as an example. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. The specific working process of the system, device, and unit described above can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0131] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, or indirect coupling or communication connection between apparatuses or units, and may be electrical, mechanical, or other forms.

[0132] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0133] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0134] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as flash memory, portable hard disk, read-only memory, random access memory, magnetic disk, or optical disk.

[0135] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A transceiver circuit, characterized in that, include: The system includes a clock adjustment module, a frequency and phase detector, and a first phase-locked loop (PLL). The first input terminal of the clock adjustment module is coupled to the input terminal of the transceiver circuit. The first output terminal of the clock adjustment module is connected to the first input terminal of the frequency and phase detector. The output terminal of the frequency and phase detector is connected to the input terminal of the first PLL. The output terminal of the first PLL is connected to the second input terminal of the clock adjustment module and the second input terminal of the frequency and phase detector. The frequency and phase detector is used to determine the frequency difference between the current received clock signal of the transceiver circuit and the clock signal output by the first phase-locked loop at the previous moment. The first phase-locked loop is used to output a first clock signal according to the frequency difference; The clock adjustment module is used to determine the phase difference between the clock signal of the first transceiver device and the current clock signal of the transceiver circuit; and to adjust the first clock signal according to the phase difference to obtain a second clock signal, the second clock signal being synchronized with the clock signal of the first transceiver device; and to update the receiving clock signal of the transceiver circuit to the second clock signal, the second clock signal being used to receive data from the first transceiver device; the clock adjustment module includes a phase detection module and a first phase interpolator, the output terminal of the first phase interpolator being connected to the second input terminal of the phase detection module, so that the second clock signal is sent to the phase detection module, the second clock signal being used to compare and determine the phase difference with the subsequently received clock signal of the first transceiver device, so as to achieve continuous synchronization between the receiving clock signal of the transceiver circuit and the clock signal of the first transceiver device.

2. The transceiver circuit according to claim 1, characterized in that, The first input terminal of the phase detection module is coupled to the first input terminal of the clock adjustment module, the output terminal of the phase detection module is connected to the first input terminal of the first phase interpolator, the second input terminal of the first phase interpolator is coupled to the second input terminal of the clock adjustment module, and the output terminal of the first phase interpolator is coupled to the first output terminal of the clock adjustment module. The phase detection module is used to determine the phase difference between the clock signal of the first transceiver device and the current clock signal of the transceiver circuit; The first phase interpolator is used to adjust the first clock signal according to the phase difference to obtain the second clock signal.

3. The transceiver circuit according to claim 1 or 2, characterized in that, The transceiver circuit also includes an analog-to-digital converter (ADC), the input of which is coupled to the input of the transceiver circuit, and the output of which is connected to the first input of the clock adjustment module. The analog-to-digital converter is used to convert the clock signal of the first transceiver device from an analog signal to a digital signal.

4. The transceiver circuit according to claim 3, characterized in that, The transceiver circuit further includes a second phase interpolator, the first input terminal of which is connected to the output terminal of the first phase-locked loop, the second input terminal of which is connected to the second output terminal of the clock adjustment module, and the output terminal of the phase detection module is coupled to the second output terminal of the clock adjustment module. The second phase interpolator is used to adjust the first clock signal according to the phase difference output by the second output terminal of the clock adjustment module to obtain a third clock signal, wherein the third clock signal is synchronized with the clock signal of the first transceiver device. And update the transmit clock signal of the transceiver circuit to the third clock signal, which is used to send data to the first transceiver device.

5. The transceiver circuit according to claim 3, characterized in that, The transceiver circuit further includes: a second phase interpolator and a second phase-locked loop, the input terminal of the second phase-locked loop is connected to the output terminal of the frequency and phase detector, the output terminal of the second phase-locked loop is connected to the first input terminal of the second phase interpolator, the second input terminal of the second phase interpolator is connected to the second output terminal of the clock adjustment module, and the output terminal of the phase detector is coupled to the second output terminal of the clock adjustment module. The second phase-locked loop is used to output a fourth clock signal based on the frequency difference; The second phase interpolator is used to adjust the fourth clock signal according to the phase difference output by the second output terminal of the clock adjustment module to obtain a fifth clock signal, the fifth clock signal being synchronized with the clock signal of the first transceiver device; and to update the transmit clock signal of the transceiver circuit to the fifth clock signal, the fifth clock signal being used to transmit data to the first transceiver device.

6. A transceiver circuit, characterized in that, include: The system includes a clock adjustment module, a low-pass filter, and a first phase-locked loop (PLL). The first input terminal of the clock adjustment module is coupled to the input terminal of the transceiver circuit. The first output terminal of the clock adjustment module is connected to the input terminal of the low-pass filter. The output terminal of the low-pass filter is connected to the input terminal of the first PLL. The output terminal of the first PLL is connected to the second input terminal of the clock adjustment module. The low-pass filter is used to determine the frequency difference between the current receiving clock signal of the transceiver circuit and the receiving clock signal of the transceiver circuit at the previous moment. The first phase-locked loop is used to output a first clock signal according to the frequency difference; The clock adjustment module is used to determine a first phase difference based on the clock signal of the first transceiver device and the current receiving clock signal of the transceiver circuit; adjust the first clock signal according to the first phase difference to obtain a second clock signal, the second clock signal being synchronized with the clock signal of the first transceiver device; and update the receiving clock signal of the transceiver circuit to the second clock signal, the second clock signal being used to receive data from the first transceiver device; the clock adjustment module includes a phase detection module and a first phase interpolator, the output terminal of the first phase interpolator being connected to the second input terminal of the phase detection module, so that the second clock signal is sent to the phase detection module, the second clock signal being used to compare and determine the phase difference with the subsequently received clock signal of the first transceiver device, so as to achieve continuous synchronization between the receiving clock signal of the transceiver circuit and the clock signal of the first transceiver device.

7. The transceiver circuit according to claim 6, characterized in that, The low-pass filter is specifically used to determine the frequency difference between the current receiving clock signal of the transceiver circuit and the receiving clock signal of the transceiver circuit at the previous moment, based on the phase difference between the current receiving clock signal of the transceiver circuit output by the clock adjustment module and the receiving clock signal of the transceiver circuit at the previous moment.

8. The transceiver circuit according to claim 6 or 7, characterized in that, The first input terminal of the phase detection module is coupled to the first input terminal of the clock adjustment module, the first output terminal of the phase detection module is coupled to the first output terminal of the clock adjustment module, the second output terminal of the phase detection module is connected to the first input terminal of the first phase interpolator, and the second input terminal of the first phase interpolator is coupled to the second input terminal of the clock adjustment module. The phase detection module is used to determine the first phase difference based on the clock signal of the first transceiver device and the current receiving clock signal of the transceiver circuit. The first phase interpolator is used to adjust the first clock signal according to the first phase difference to obtain the second clock signal.

9. The transceiver circuit according to claim 8, characterized in that, The transceiver circuit also includes an analog-to-digital converter (ADC), the input of which is coupled to the input of the transceiver circuit, and the output of which is connected to the first input of the clock adjustment module. The analog-to-digital converter is used to convert the clock signal of the first transceiver device from an analog signal to a digital signal.

10. The transceiver circuit according to claim 9, characterized in that, The transceiver circuit further includes a second phase interpolator, the first input terminal of which is connected to the output terminal of the first phase-locked loop, the second input terminal of which is connected to the second output terminal of the clock adjustment module, and the second output terminal of the phase detection module is also coupled to the second output terminal of the clock adjustment module. The second phase interpolator is used to adjust the first clock signal according to the second phase difference output by the second output terminal of the clock adjustment module to obtain a third clock signal, wherein the third clock signal is synchronized with the clock signal of the first transceiver device. And update the transmit clock signal of the transceiver circuit to the third clock signal, which is used to send data to the first transceiver device.

11. The transceiver circuit according to claim 9, characterized in that, The transceiver circuit further includes a second phase interpolator and a second phase-locked loop. The input terminal of the second phase-locked loop is connected to the output terminal of the low-pass filter, the output terminal of the second phase-locked loop is connected to the first input terminal of the second phase interpolator, the second input terminal of the second phase interpolator is connected to the second output terminal of the clock adjustment module, and the second output terminal of the phase detection module is also coupled to the second output terminal of the clock adjustment module. The second phase-locked loop is used to output a fourth clock signal based on the frequency difference; The second phase interpolator is used to adjust the fourth clock signal according to the phase difference output by the second output terminal of the clock adjustment module to obtain a fifth clock signal, which is synchronized with the clock signal of the first transceiver device. And update the transmit clock signal of the transceiver circuit to the fifth clock signal, which is used to send data to the first transceiver device.

12. A transceiver device, characterized in that, The transceiver device includes the transceiver circuit according to any one of claims 1 to 5 or the transceiver circuit according to any one of claims 6 to 11.

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