A phased array ultrasonic detection circuit and a detection module comprising the same

Abstract

The utility model provides a kind of phased array ultrasonic detection circuit and the detection module comprising it, solve the technical problem that current control array ultrasonic detection cannot realize modularization, integration, its main scheme includes the chip of 8 channel transmission, its pin includes power supply voltage, driver voltage output, high voltage power input, pulse generator output, digital signal input, internal power generator control input and CMOS control input, the power supply voltage is grounded by 0.1 μF capacitor, the driver voltage output is connected respectively by 1 μF capacitor with the high voltage power input positive and negative end, the high voltage power input is grounded by 0.1 μF capacitor, the pulse generator output at least includes 8, the digital signal input positive and negative end is a group and includes multiple groups, and each group digital signal input is sequentially connected each pulse generator output, and the CMOS control input includes clock same direction input and clock reverse input.

Description

Technical Field

[0001] This utility model relates to the technical field of tube sheet weld inspection equipment, and in particular to a phased array ultrasonic inspection circuit and a detection module containing the same. Background Technology

[0002] Non-destructive testing of welds refers to the inspection of weld quality to determine whether it meets the specified requirements and design intent without damaging the performance and integrity of the weld being inspected, using methods such as ultrasonic testing, radiographic testing, magnetic particle testing, or penetrant testing.

[0003] However, existing ultrasonic testing equipment is cumbersome to assemble, and phased array ultrasonic testing cannot be modularized or integrated, resulting in low testing efficiency. To address these issues, we propose a phased array ultrasonic testing circuit and a testing module containing it. Utility Model Content

[0004] The technical problem to be solved by this utility model is to overcome the defects of the existing technology. This utility model proposes a phased array ultrasonic detection circuit and a detection module containing it, which can flexibly complete different modes of digital ultrasonic phased array control and digital signal processing to meet various different detection needs.

[0005] To solve the above-mentioned technical problems, the technical solution adopted by this utility model is: a phased array ultrasonic detection circuit, comprising: at least two electrically connected integrated chips, each of which has 8 transmission channels, and its corresponding integrated pins include power supply voltage, driver voltage output, high voltage power input, pulse generator output, digital signal input, internal power generator control input, and CMOS control input. The power supply voltage is grounded through a 0.1μF capacitor. The driver voltage output is connected to the positive and negative terminals of the high voltage power input through 1μF capacitors respectively. The high voltage power input is grounded through a 0.1μF capacitor. The pulse generator output includes at least 8 outputs. The positive and negative terminals of the digital signal input are in one group and include multiple groups. Each group of digital signal inputs is sequentially connected to each pulse generator output. The internal power generator control input is grounded through a pull-down resistor. The CMOS control input includes a clock in-direction input and a clock inverse input. Both the internal power generator control input and the CMOS control input are connected to a low-voltage switch output.

[0006] Furthermore, the integrated pin also includes a thermally protected open-drain output that triggers a THP alarm and simultaneously draws 3mA of current to GND when the junction temperature exceeds +150°C.

[0007] Furthermore, the internal power generator control input is connected to an external power source via a driver voltage output, and the internal power source is disabled when the input is high.

[0008] Furthermore, the CMOS control inputs include SYNC, CLK, and Setting the SYNC driver to high corresponds to clock input mode, while setting it to low operates in transparent transmission mode.

[0009] A detection module includes the phased array ultrasonic detection circuit described above:

[0010] The detection module includes a SOC system, a phased array ultrasonic front-end, and a power supply. The power supply is electrically connected to the SOC system and the phased array ultrasonic front-end to provide power. The phased array ultrasonic front-end includes an ADC, an integrated analog receiving circuit, and an integrated transmitting circuit. The SOC system is electrically connected to the integrated analog receiving circuit. After receiving the transmission control signal, the integrated analog receiving circuit generates a corresponding excitation signal according to the signal requirements to excite the phased array probe. The phased array probe generates an ultrasonic signal under excitation and emits it toward the workpiece being inspected. When the ultrasonic signal encounters a defect inside the workpiece or an interface between different media, it is reflected. The phased array probe synchronously receives the signal and converts it into an electrical signal, which is then transmitted to the integrated analog receiving circuit. The integrated analog receiving circuit processes the analog signal and transmits it to the ADC. After digital conversion, the signal is transmitted to the SOC system. The SOC system can interact with a host computer through a data interface.

[0011] The detection module also includes peripheral circuitry, which includes various memory devices to store the operating data of the SOC system.

[0012] The detection module also includes a system interface circuit, which includes various types of interfaces, including encoder interfaces and I / O interfaces.

[0013] Compared with existing technologies, the beneficial effects of this invention include: the SoC system generates precise transmission control signals according to preset programs and instructions, providing a foundation for subsequent ultrasonic transmission. In the receiving phase, it is responsible for receiving processed ultrasonic data and performing in-depth analysis and processing. After processing, the SoC system quickly and stably transmits the processed ultrasonic data to the host computer via the data interface (h) for higher-level analysis, storage, and display. Simultaneously, the SoC system also has the function of receiving commands from the host computer. Based on these commands, it can flexibly complete different modes of digital ultrasonic phased array control and digital signal processing, meeting various detection needs. Attached Figure Description

[0014] The disclosure of this utility model is illustrated with reference to the accompanying drawings. It should be understood that the drawings are for illustrative purposes only and are not intended to limit the scope of protection of this utility model. In the drawings, the same reference numerals are used to refer to the same parts. Wherein:

[0015] Figure 1 The schematic diagram illustrates the configuration of a detection module according to one embodiment of the present invention.

[0016] Figure 2 The schematic diagram shows an integrated chip 8-channel transmitter circuit diagram according to one embodiment of the present invention;

[0017] Figure 3 The diagram schematically shows an isometric view of a detection module according to one embodiment of the present invention.

[0018] Figure 4 The schematic diagram shows a top view of a detection module according to one embodiment of the present invention;

[0019] Figure 5 The diagram schematically shows a left view of a detection module according to one embodiment of the present invention;

[0020] Figure 6 The diagram schematically shows a right view of a detection module according to one embodiment of the present invention. Detailed Implementation

[0021] It is readily understood that, based on the technical solution of this utility model, those skilled in the art can propose various interchangeable structural methods and implementations without altering the essential spirit of this utility model. Therefore, the following detailed embodiments and accompanying drawings are merely illustrative descriptions of the technical solution of this utility model and should not be considered as the entirety of this utility model or as limitations or restrictions on the technical solution of this utility model.

[0022] According to one embodiment of the present invention, in conjunction with Figures 1-6 As shown.

[0023] like Figure 1As shown, the detection module comprises a SOC system, a phased array ultrasonic front-end, and a power supply. The power supply is electrically connected to the SOC system and the phased array ultrasonic front-end to provide power. The phased array ultrasonic front-end includes an ADC, an integrated analog receiving circuit, and an integrated transmitting circuit. The SOC system is electrically connected to the integrated analog receiving circuit. After receiving the transmission control signal, the integrated analog receiving circuit generates a corresponding excitation signal to excite the phased array probe according to the signal requirements. The phased array probe generates an ultrasonic signal under excitation and emits it towards the workpiece being inspected. When the ultrasonic signal encounters a defect inside the workpiece or an interface between different media, it is reflected. The phased array probe synchronously receives the signal and converts it into an electrical signal, which is then transmitted to the integrated analog receiving circuit. The integrated analog receiving circuit processes the analog signal and transmits it to the ADC. After digital conversion, the signal is transmitted to the SOC system. The SOC system can interact with a host computer through a data interface.

[0024] The following combination Figure 1 as well as Figure 2 Each component of the module is explained in detail.

[0025] The SoC system (a) is the core hub of the entire module, responsible for several crucial tasks. It not only precisely controls the transmission and reception of the front-end ultrasound signal but also performs complex digital signal processing. During transmission, the SoC generates precise transmission control signals based on preset programs and instructions, providing the foundation for subsequent ultrasound transmission. During reception, it receives processed ultrasound data and performs in-depth analysis and processing. After processing, the SoC transmits the processed ultrasound data quickly and stably to the host computer via the data interface (h) for higher-level analysis, storage, and display. Simultaneously, the SoC also has the function of receiving commands from the host computer. Based on these commands, it can flexibly complete different modes of digital ultrasound phased array control and digital signal processing to meet various detection needs.

[0026] The phased array ultrasonic front-end is the key area for ultrasonic signal transmission and reception in the entire module, mainly composed of an ADC (b), an integrated analog receiving circuit (c), and an integrated transmitting circuit (d). The SoC system (a) transmits the generated transmission control signal to the integrated transmitting circuit (d). Upon receiving the transmission control signal, the integrated transmitting circuit (d) generates an excitation signal with specific frequency, amplitude, and phase according to the signal requirements. This excitation signal effectively excites the phased array probe (e). Under the action of the excitation signal, the phased array probe (e) generates ultrasonic signals and emits them towards the workpiece being inspected. When the ultrasonic signal encounters defects inside the workpiece or interfaces between different media, it is reflected. After receiving these reflected ultrasonic signals, the phased array probe (e) converts them into electrical signals and transmits them to the integrated analog receiving circuit (c). The integrated analog receiving circuit (c) acts like a sophisticated signal conditioner, amplifying and filtering these electrical signals reflecting ultrasonic information to remove noise and interference, enhance signal quality, and make the signal more suitable for subsequent processing. The processed analog signal is then transmitted to the ADC(b), whose main responsibility is to convert the analog signal into a digital signal, as digital signals are easier for the SoC system (a) to process and analyze. Finally, the ADC(b) transmits the converted digital signal to the SoC system (a), completing the entire signal reception and preliminary processing flow.

[0027] The peripheral circuitry (f) plays an indispensable supporting role in the stable operation of the SoC system (a). It includes various types of memory, one of which is program memory. This program memory stores the various program codes required for the entire module to run; these codes act as the "brain instructions" of the module, guiding the coordinated work of its various parts. Another type of memory stores temporary data generated during computation. When the SoC system performs complex digital signal processing and control operations, a large amount of temporary data is generated. This data needs to be temporarily stored for subsequent computation and processing. This type of memory provides storage space for this temporary data, ensuring the continuity and accuracy of the computation process.

[0028] The data interface (h) serves as a bridge for data and command transmission between the SoC system (a) and the host computer. It possesses high-speed and stable data transmission capabilities, ensuring that ultrasonic data is not lost or damaged during transmission, while also quickly and accurately transmitting commands from the host computer to the SoC system (a). Whether it's transmitting large amounts of ultrasonic detection data from the module to the host computer for analysis and storage, or transmitting various control commands from the host computer to the module, the data interface (h) efficiently completes the task, guaranteeing smooth communication between the module and the host computer.

[0029] The system interface circuit (g) further expands the module's application scope, encompassing various interface types such as encoder interfaces and I / O interfaces. The encoder interface connects to encoder devices to acquire encoder signals, which is extremely useful in detection scenarios requiring precise position or angle measurements. For example, when performing ultrasonic testing on rotating parts, the encoder can obtain the part's rotation angle information, which, combined with ultrasonic testing data, enables more accurate defect localization. The I / O interface connects to various external devices, such as sensors and actuators, allowing the module to interact with more devices, further enriching its functionality and meeting the diverse needs of different application scenarios.

[0030] The power supply system (i) is the "power source" of the entire module, providing stable and suitable power to all parts of the module. Different components have different power requirements; some require high voltage, some require low voltage, and some have extremely high requirements for power stability. The power supply system (i) can precisely adjust the output voltage and current according to the needs of each component, ensuring that every part of the module can operate stably under normal operating voltage, thereby guaranteeing the performance and reliability of the entire module.

[0031] The most crucial function of the SOC system is achieved through two 8-channel integrated chips. Each chip transmits through 8 channels, and its corresponding integrated pins include power supply voltage, driver voltage output, high-voltage power input, pulse generator output, digital signal input, internal power generator control input, and CMOS control input. The power supply voltage is grounded through a 0.1μF capacitor. The driver voltage output is connected to the positive and negative terminals of the high-voltage power input through 1μF capacitors. The high-voltage power input is grounded through a 0.1μF capacitor. The pulse generator output includes at least 8 outputs. The digital signal input has multiple sets of positive and negative terminals, with each set of digital signal inputs sequentially connected to each pulse generator output. The internal power generator control input is grounded through a pull-down resistor. The CMOS control input includes a clock inverse input and a clock inverse input. Both the internal power generator control input and the CMOS control input are connected to a low-voltage switch output.

[0032] For the corresponding pin names and circuit connections, please refer to [reference needed]. Figure 2 The specific details are as follows: Vcc and V EE Both are power supply voltages, and both are connected to Vcc and V through a 0.1μF capacitor. EE (Both pins) Bypass to GND, V NNB and V PPB The positive and negative terminals of the high-voltage power supply input are also bypassed to GND through a 0.1μF capacitor. The aforementioned capacitors should be placed as close as possible to the device. GNB and V GPBThe driver voltage output is connected to V through a 1μF capacitor. NNB and V PPB OUT1-OUT8 are eight independent pulse generator outputs, with corresponding digital signal inputs DINP1-DINP8, and the internal power generator control input... Using V GPA V GPB V GNA and V GNB When using an external power source, if If the drive is high, the internal power supply is disabled. It has a 10kΩ internal pull-down resistor, pulled down to GND. For CMOS control inputs, for CLK, in differential clock mode, at CLK and... Data is shifted on the rising edge. In single-ended clock mode, data is shifted in on the rising edge of CLK. The maximum clock frequency is 160MHz. In differential clock mode, in CLK and The rising edge shifts the data, and the maximum clock frequency is 160 MHz. If the rising edge shifts the data, the maximum clock frequency is 160 MHz. Connected to GND, the CLK input is a single-ended logic clock input; otherwise, CLK and... This is the self-biased differential clock input. Correspondingly, CC0 and CC1 are current control inputs used to control the current drive, and MODE0 and MODE1 are mode control inputs used to control the operating mode. SYNC, CLK, CC0, CC1, MODE0, and MODE1 are all connected to low-voltage switch outputs LVOUT1-8.

[0033] like Figure 3 and Figure 4 As shown, the terminal for the detection module equipped with the aforementioned integrated chip adopts a series of strip-shaped U-shaped grooves and ring-shaped U-shaped grooves. The U-shaped grooves are used for heat dissipation. In addition, a recess composed of a combination of circles and rectangles is designed for attaching the device's logo, model number, and name, such as... Figure 5 As shown, the left side of the terminal, from bottom to top, features a power interface, a USB interface, an encoder interface, and an I / O interface. The power interface supplies power to the phased array module; the USB interface is used for data communication with the phased array module; the encoder interface is used for the positioning encoder of the external pipe plate weld seam inspection scanner; and the I / O interfaces are used for alarm output and input / output of control array signals. Figure 6As shown, the right side of the terminal, from bottom to top, features a power button switch, a power indicator, and a phased array probe interface. The power button switch is used to turn the phased array ultrasonic module on and off, the power indicator is used to indicate the working status of the phased array ultrasonic module, and the phased array probe interface is used to connect the phased array probe of the external tube plate weld inspection scanner.

[0034] The technical scope of this utility model is not limited to the content described above. Those skilled in the art can make various modifications and variations to the above embodiments without departing from the technical concept of this utility model, and all such modifications and variations should fall within the protection scope of this utility model.

Claims

1. A phased array ultrasonic testing circuit, characterized by: It comprises: At least two pieces of electrically connected integrated chips, each of which is an 8-channel emitter, and its corresponding integrated pins include power voltage, driver voltage output, high-voltage power input, pulse generator output, digital signal input, internal power generator control input, and CMOS control input, the power voltage is grounded through a 0.1 μF capacitor, the driver voltage output is respectively connected to the positive and negative terminals of the high-voltage power input through a 1 μF capacitor, the high-voltage power input is grounded through a 0.1 μF capacitor, the pulse generator output includes at least 8, the positive and negative terminals of the digital signal input are a group and include multiple groups, each group of digital signal input is connected to each pulse generator output in turn, the internal power generator control input is pulled down to ground through a pull-down resistor, and the CMOS control input includes clock same direction input and clock reverse input, and the internal power generator control input and the CMOS control input are both connected to a low-voltage switch output.

2. A phased array ultrasonic inspection circuit according to claim 1, wherein: The integrated pins further include A hot protection open-drain output, which triggers a THP alarm when the junction temperature exceeds +150℃, and synchronously absorbs 3mA current to GND.

3. A phased array ultrasonic testing circuit according to claim 2, wherein: The internal power generator The control input is connected to an external power supply through the driver voltage output, and when it is high, the internal power supply is disabled.

4. A phased array ultrasonic inspection circuit according to claim 1, wherein: The CMOS control input The input includes SYNC, CLK, and When the SYNC is driven to high level, it corresponds to the clock input mode, and is driven to low Usually works in transparent transmission mode.

5. A detection module comprising the phased array ultrasonic detection circuit of any of claims 1-4, characterized in that: The detection module includes a SOC system, a phased array ultrasonic front end, and a power supply, the power supply is electrically connected to the SOC system and the phased array ultrasonic front end for power supply, the phased array ultrasonic front end includes an ADC, an integrated analog receiving circuit, and an integrated transmitting circuit, the SOC system is electrically connected to the integrated analog receiving circuit, the integrated analog receiving circuit generates a corresponding excitation signal according to signal requirements after receiving a transmitting control signal to excite a phased array probe, the phased array probe generates an ultrasonic signal after being excited, and transmits the ultrasonic signal to a detected workpiece, the ultrasonic signal is reflected when encountering a defect or different medium interface inside the workpiece, the phased array probe synchronously receives and converts it into an electric signal, and then transmits it to the integrated analog receiving circuit, the analog signal processed by the integrated analog receiving circuit is transmitted to the ADC, and after digital conversion, it is transmitted to the SOC system, the SOC system can interact with the upper computer through a data interface. The detection module further includes a system peripheral circuit, and the system peripheral circuit includes a plurality of memories to store the running data of the SOC system.

6. The detection module of claim 5, wherein: The detection module further includes a system interface circuit, and the system interface circuit includes a plurality of types of interfaces, including an encoder interface and an IO interface. ​ 7. The detection module of claim 5, wherein: ​

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