A chip testing apparatus

Abstract

The utility model application discloses a kind of chip testing device, belong to chip test technical field.Chip testing device includes: chip;Chip VDD pin is connected VSS pin by first capacitor;One end of first resistance connects PIRIN pin, and the other end of first resistance is grounded;First switch is located between first resistance, PIRIN pin, and one end of first switch connects PIRIN pin, and the other end of first switch connects one end of third resistance, and the other end of third resistance is grounded;One end of second resistance connects NPIRIN pin, and the other end of second resistance is grounded;Second switch is located between second resistance, NPIRIN pin, and one end of second switch connects NPIRIN pin, and the other end of second switch connects one end of fourth resistance, and the other end of fourth resistance is grounded;PIRIN pin is connected with NPIRIN pin by second capacitor.The utility model application improves the flexibility of chip test.

Description

Technical Field

[0001] This utility model application belongs to the field of chip testing technology, and specifically relates to a chip testing device. Background Technology

[0002] In chip design and development, for the convenience of testing, an automatic detection function pin was originally designed: after the chip has completed its heat dissipation and stabilized (single-line data output pin level reset), the internal test bit register is configured with 0 successively and then immediately configured with 1, thereby generating a low-to-high level transition in the test bit register. The rising edge triggers the chip to enter the functional self-test mode.

[0003] However, the testing method faces many problems: chip testing equipment is complex and costly, chip testing equipment is difficult to dynamically adjust test conditions, chip testing lacks flexibility, chip warm-up takes about 0.5 seconds, and after entering self-test mode, the chip needs 2.2-2.5 seconds to complete a self-test process. In addition, the microcontroller needs about 0.3 seconds to complete the algorithm and determine whether the data read from the self-test mode is qualified (Pass), resulting in the entire test process taking more than 3 seconds to complete the test of a single chip.

[0004] Currently, the standard configuration of commercially available testing and sorting machines, even if the chip testing machine can be fully staffed (i.e., 4 test positions working simultaneously), only has a UPH (units per hour, the number of ICs tested per hour) of about 3,000, which is difficult to meet the capacity requirements for large-scale chip delivery and seriously restricts the efficiency of chip mass production and delivery. Summary of the Invention

[0005] This utility model application provides a chip testing device, aiming to partially or completely solve the technical problems of existing chip testing devices, such as high complexity and cost; difficulty in dynamically adjusting test conditions, resulting in insufficient flexibility in chip testing; and long testing time for single chips, making it difficult to meet the production capacity requirements for large-volume chip delivery. To achieve the above objectives, this utility model application adopts the following technical solution:

[0006] A chip testing apparatus, comprising: a chip;

[0007] The chip includes VSS pin, INT / DOCI pin, SERIN pin, VDD pin, NC pin, PIRIN pin, NPIRIN pin, and VPIR pin;

[0008] The VDD pin is connected to the positive terminal of the external power supply, the VSS pin is connected to the negative terminal of the external power supply, and the VDD pin is connected to the VSS pin through the first capacitor.

[0009] One end of the first resistor is connected to the PIRIN pin, and the other end of the first resistor is grounded.

[0010] The first switch is located between the first resistor and the PIRIN pin. One end of the first switch is connected to the PIRIN pin, and the other end of the first switch is connected to one end of the third resistor. The other end of the third resistor is grounded.

[0011] One end of the second resistor is connected to the NPIRIN pin, and the other end of the second resistor is grounded.

[0012] The second switch is located between the second resistor and the NPIRIN pin. One end of the second switch is connected to the NPIRIN pin, and the other end of the second switch is connected to one end of the fourth resistor. The other end of the fourth resistor is grounded.

[0013] The PIRIN pin is connected to the NPIRIN pin via a second capacitor.

[0014] Optionally, the chip is an NY86 chip; and / or, the SERIN pin is connected to a signal generator or microcontroller to input serial test data; and / or, the INT / DOCI pin is connected to a test device to monitor the chip's interrupt signals or data output.

[0015] Optionally, the VPIR pin is left floating, the NC pin is left floating; and / or, the first resistor is 75GΩ, the second resistor is 75GΩ; and / or, the third resistor R3 is 0Ω, the fourth resistor R4 is 0Ω.

[0016] Optionally, the chip testing device tests the chip's current parameters, VPIR parameters, CONFO parameters, and DATA_BPF parameters.

[0017] (1) In this utility model application, the signal input of the PIRIN and NPIRIN pins is controlled by the first switch and the second switch respectively. Combined with the configuration of resistors (first, second, third, and fourth resistors) and second capacitors, the test conditions can be dynamically adjusted. The chip test device can test one or more of the following combinations: chip current parameters, chip VPIR parameters, chip CONFO parameters, chip DATA_BPF parameters, chip CONF1 parameters, chip DATA_LPF parameters, chip CONF2 parameters, chip DATA_T parameters, chip CONF3 parameters, and chip DATA_V parameters, which improves the flexibility of chip testing. The VDD and VSS pins are connected through the first capacitor, and the PIRIN and NPIRIN pins are coupled through the second capacitor, which effectively filters out noise, enhances signal stability, and ensures the accuracy of test results. The chip test device is reasonably designed and uses a small number of components (capacitors, resistors, and switches) to achieve efficient and comprehensive chip testing functions, reduce costs, and facilitate large-scale production and application.

[0018] (2) In this utility model application, after the chip is powered on, it warms up for 0.5 seconds, and then the current parameters and VPIR parameters of the chip are tested. Then, steps S400, S500, S600, S700, S800, S900, S1000, and S1100 are performed. The total test time for steps S400, S500, S600, S700, S800, S900, S1000, and S1100 is only about 0.55 seconds. That is, the chip testing device tests the CONFO parameters of the chip and tests... The combined testing time for the chip's DATA_BPF parameters, CONF1 and DATA_LPF parameters, CONF2 and DATA_T parameters, and CONF3 and DATA_V parameters is only about 0.55 seconds. Under the same conditions, the total testing time for a single chip is only about 1.1 seconds, improving chip testing efficiency by more than 70%. This allows the same testing equipment to produce 8,000-10,000 chips per month, overcoming the bottleneck that restricts the production efficiency of this type of chip and making it possible to deliver millions of chips per month at a reasonable testing cost. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this utility model application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the appearance of the chip to be tested according to this utility model application. Figure 1 ;

[0021] Figure 2 This is a schematic diagram of the appearance of the chip to be tested according to this utility model application. Figure 2 ;

[0022] Figure 3 This is a pin diagram of the chip to be tested according to this utility model application;

[0023] Figure 4 This is a schematic diagram of the chip testing device according to this utility model application;

[0024] Figure 5 This is a flowchart illustrating steps S100 to S600 in the operation of the chip testing device of this utility model application.

[0025] Figure 6 This is a flowchart illustrating steps S700 to S1100 in the operation of the chip testing device of this utility model application.

[0026] The accompanying drawings are provided to further understand the present utility model application and form part of the specification. They are used together with the embodiments of the present utility model application to explain the present utility model application and do not constitute a limitation thereof. Detailed Implementation

[0027] The technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this utility model without creative effort are within the scope of protection of this utility model.

[0028] In the description of this utility model application, it should be understood that the terms "upper," "lower," "front," "rear," "left," "right," "top," "bottom," "inner," and "outer," etc., indicating orientation or positional relationships, are based on the orientation or positional relationships shown in the accompanying drawings and are only for the convenience of describing this utility model application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model application. To make the purpose, technical solution, and advantages of this utility model application clearer, the embodiments of this utility model application will be further described in detail below with reference to the accompanying drawings.

[0029] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means one, two, or more than two, unless otherwise explicitly specified.

[0030] To make the purpose, technical solution, and advantages of this utility model application clearer, the technical solutions in the embodiments of this utility model application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this utility model application without creative effort are within the scope of protection of this utility model application.

[0031] Chip testing equipment

[0032] like Figures 1 to 4 As shown, a chip testing apparatus includes:

[0033] The chip includes VSS pin, INT / DOCI pin, SERIN pin, VDD pin, NC pin, PIRIN pin, NPIRIN pin, and VPIR pin. The VDD pin is connected to the positive terminal of the external power supply, and the VSS pin is connected to the negative terminal of the external power supply. The VDD pin is connected to the VSS pin through the first capacitor C1.

[0034] One end of the first resistor R1 is connected to the PIRIN pin, and the other end of the first resistor R1 is grounded.

[0035] The first switch K1 is located between the first resistor R1 and the PIRIN pin. One end of the first switch K1 is connected to the PIRIN pin, and the other end of the first switch K1 is connected to one end of the third resistor R3. The other end of the third resistor R3 is grounded.

[0036] One end of the second resistor R2 is connected to the NPIRIN pin, and the other end of the second resistor R2 is grounded.

[0037] The second switch K2 is located between the second resistor R2 and the NPIRIN pin. One end of the second switch K2 is connected to the NPIRIN pin, and the other end of the second switch K2 is connected to one end of the fourth resistor R4. The other end of the fourth resistor R4 is grounded.

[0038] The PIRIN pin is connected to the NPIRIN pin via the second capacitor C2.

[0039] In some embodiments, the chip is an NY86 chip, which is used in security or automation systems related to PIR sensors.

[0040] In some embodiments, the VSS pin (pin 1) is a ground pin, providing a reference potential for the chip and ensuring a return path for current in the circuit. It is an important component of the chip's power supply system. By connecting the VSS pin to the system ground, the chip can maintain a stable potential difference, thereby ensuring normal operation.

[0041] In some embodiments, the VDD pin is connected to the VSS pin via a first capacitor C1, which is 0.1μF, to achieve power supply decoupling. The VDD pin is connected to the positive terminal of an external power supply (e.g., +5V, +3.3V, or 3V), and the VSS pin is connected to the negative terminal (ground) of the external power supply. Together, they provide a stable operating voltage for the chip. The function of the first capacitor C1 is to reduce power supply noise, stabilize the voltage supply, and ensure that the chip's performance is not affected by power fluctuations during testing, thus providing a suitable temperature environment for chip testing.

[0042] In some embodiments, the INT / DOCI pin (pin 2) can be used for interrupt (INT) or data output / clock input (DOCI), depending on the application scenario. When used as an interrupt pin (denoted as INT pin), external events (such as signal changes) can trigger the chip to perform specific operations through this pin, such as pausing the current task or jumping to a specific program; when used as a data output or clock input (denoted as DOCI pin), this pin is used to communicate with external test equipment, and can output data or receive clock signals.

[0043] In some embodiments, the SERIN pin (pin 3) is a serial input pin used to receive serial data, allowing the chip to receive data from external devices such as sensors, controllers, or other chips. Serial data input is typically transmitted as a bit stream, and the chip reads the data sequentially through this pin for processing.

[0044] In some embodiments, the VDD pin (pin 4) is a power supply pin that provides the operating voltage to the chip. It is connected to an external power source to power the chip's internal circuitry, ensuring that the chip has sufficient power to perform its functions. The VDD pin and the VSS pin together constitute the chip's power system.

[0045] In some embodiments, the VPIR pin (pin 5) is a PIR voltage pin that can provide operating voltage to the PIR sensor or serve as a reference voltage. It can ensure that the PIR sensor can work properly and generate accurate signals, and can support the operation of the sensor by providing a stable voltage, or serve as a reference point for signal processing.

[0046] In some embodiments, the NPIRIN pin (pin 6) is a negative PIR input pin, used in conjunction with the PIRIN pin. The NPIRIN pin can form a differential input with the PIRIN pin, improving signal accuracy and noise immunity by comparing positive and negative signals. This design is commonly used in PIR sensor applications to enhance detection reliability.

[0047] In some embodiments, the PIRIN pin (pin 7) is a positive PIR (passive infrared) input pin, used to connect to the positive output of the PIR sensor. When the PIR sensor detects motion or temperature changes, it generates an electrical signal, which is input to the chip through the PIRIN pin. The chip uses this signal for subsequent processing, such as triggering an alarm or recording an event.

[0048] In some embodiments, the NC pin (pin 8) is an unconnected pin and is generally not used in chip design. These pins are typically not connected to any circuitry, possibly to maintain pin layout compatibility or to reserve space for future functional expansion. In practice, the NC pin should be left floating or handled as required by the datasheet.

[0049] In some embodiments, the VDD pin is connected to an external voltage source (e.g., +5V, +3.3V, or +3V) to power the chip, and the VSS pin is connected to ground. Thus, powering the chip through the VDD and VSS pins ensures normal startup within the specified voltage range.

[0050] In some embodiments, the PIRIN and NPIRIN pins can be connected to the positive and negative inputs of an analog PIR (passive infrared) sensor signal. The design of the first switch K1 and the second switch K2 provides testing flexibility. The first switch K1 is located between the PIRIN pin and the third resistor R3, connecting the circuit between the PIRIN pin and the third resistor R3. The second switch K2 is located between the NPIRIN pin and the fourth resistor R4, connecting the circuit between the NPIRIN pin and the fourth resistor R4. By closing and opening the switches, the circuit configuration can be dynamically changed to simulate different states or signal strengths of the PIR sensor. For example, closing K1 can change the input state of the PIRIN pin, and opening the second switch K2 can change the input state of the NPIRIN pin. This flexibility allows testers to simulate various operating conditions, ensuring the stability and reliability of the chip in different scenarios.

[0051] In some embodiments, the PIRIN pin is connected to the NPIRIN pin via a second capacitor C2, forming a filtering or coupling circuit. The second capacitor C2 is 22pF and filters out noise in the input signal, ensuring the chip receives a clean and accurate PIR sensor signal. This design improves the signal's immunity to interference, especially in PIR sensor applications where the signal quality of the differential inputs (PIRIN and NPIRIN) is crucial to detection accuracy. By ensuring signal quality, the accuracy of test results is improved.

[0052] In some embodiments, simulated PIR sensor signals (positive and negative differential signals) can be input through the PIRIN and NPIRIN pins to observe whether the VPIR pin or INT / DOCI pin produces the expected output. Specifically, the output signals of INT / DOCI and VPIR can be recorded using a measuring device and compared with the chip specifications or expected values ​​to determine whether its logic function is normal and to verify the chip's PIR signal processing capability.

[0053] In some embodiments, potential chip manufacturing problems, such as open circuits, short circuits, or pin malfunctions, can be identified by testing the response of each pin; key chip parameters, such as response time, signal integrity, and power consumption, can be measured to ensure that the chip meets design specifications and guarantees the reliability of the chip upon delivery.

[0054] In some embodiments, the NY86 chip can correctly process serial data (SERIN) and PIR sensor signals (PIRIN, NPIRIN), and output corresponding interrupt or voltage signals (INT / DOCI, VPIR), indicating that the chip is functioning normally and can be used in security systems or motion detection equipment.

[0055] In this utility model application, the PIRIN pin receives a positive signal and the NPIRIN pin receives a negative signal, forming a differential input. This design can verify the logic function of the chip when processing actual sensor signals. By inputting simulated PIR (passive infrared) sensor signals to the PIRIN and NPIRIN pins and monitoring the outputs of the VPIR and INT / DOCI pins, the chip's PIR signal processing capability can be comprehensively tested. It also allows for the measurement of key chip parameters such as response time, signal integrity, and power consumption, ensuring that the chip can meet design requirements in practical applications and improving the quality of the chips shipped from the factory.

[0056] Optionally, the SERIN pin is connected to a signal generator or microcontroller to input serial test data; the INT / DOCI pin is connected to a test device to monitor the chip's interrupt signals or data output.

[0057] In some embodiments, the SERIN pin is used to receive serial data sent by an external device, such as a signal generator or microcontroller. During testing, the external device applies predefined serial test data to the SERIN pin, and the chip reads the data stream sequentially through this pin and processes it according to its internal design. The processed result is typically output as a response signal through other pins, such as the INT / DOCI pin. By checking these output signals, it can be determined whether the chip has correctly received and processed the input data.

[0058] In some embodiments, the INT / DOCI pin is connected to a test device (including an oscilloscope or logic analyzer) to monitor the chip's output signals. When the chip receives a specific input (such as serial data on the SERIN pin) or completes a task, it outputs an interrupt signal or clock signal through this pin. Testers observe the waveforms, timing, and logic state of these signals using the test device to determine whether the chip correctly responds to the input and performs the expected operation.

[0059] In this utility model application, the testing principle of the SERIN pin and the INT / DOCI pin is based on the monitoring of serial data input and output signals, which can effectively verify the chip's data communication capability and logic response capability. The testing of the SERIN pin (serial input) and the NC pin (not connected) can also verify the integrity of the chip's pins, which helps to detect and remove unqualified chips early in the production process, ensure the quality of the chips leaving the factory, remove unqualified chips in the early stage of production, and reduce the failure rate and cost.

[0060] Optionally, the VPIR pin is left floating, and the NC pin is left floating.

[0061] In some embodiments, the NC pin is not assigned a function in the chip design and is typically left floating or handled as required. During testing, the state of the NC pin (which should have no signal output or exhibit a high impedance state) is checked to confirm that it has not been incorrectly connected or interfered with.

[0062] In some embodiments, the SERIN (serial input) pin and the INT / DOCI (interrupt / data output) pin are both connected via an OR logic gate. When either the SERIN or INT / DOCI pin outputs a high-level signal, the output of the OR logic gate is high.

[0063] Optionally, the first resistor R1 is 75GΩ, the second resistor R2 is 75GΩ, the third resistor R3 is 0Ω, and the fourth resistor R4 is 0Ω; and / or, the chip testing device tests the chip's current parameters, the chip's VPIR parameters, the chip's CONFO parameters, and the chip's DATA_BPF parameters.

[0064] In some embodiments, a first resistor R1 = 75 GΩ and a second resistor R2 = 75 GΩ are connected between the PIRIN and NPIRIN pins and ground. The extremely large resistance value of 75 GΩ is close to an open circuit state, used to simulate high-impedance inputs or provide a weak reference level to prevent the pins from floating.

[0065] In some embodiments, when the third resistor R3 = 0Ω and the fourth resistor R4 = 0Ω, the 0Ω resistor is equivalent to a short circuit. The PIRIN and NPIRIN pins are directly grounded through the first switch K1 and the second switch K2 to simulate different test conditions (such as zero input).

[0066] In this utility model application, 75GΩ R1 and R2 simulate the high impedance output characteristics of the PIR sensor, reducing current flow and signal interference, and ensuring pin stability. 0Ω R3 and R4 are grounded through a switch, which facilitates testing the chip response under different input conditions.

[0067] In this utility model application, the signal inputs of the PIRIN and NPIRIN pins are controlled by the first and second switches respectively. Combined with the configuration of resistors (first, second, third, and fourth resistors) and a second capacitor, the test conditions can be dynamically adjusted. The chip testing device can test one or more combinations of chip current parameters, VPIR parameters, CONFO parameters, DATA_BPF parameters, CONF1 parameters, DATA_LPF parameters, CONF2 parameters, DATA_T parameters, CONF3 parameters, and DATA_V parameters, improving the flexibility of chip testing. The DD and VSS pins are connected through the first capacitor, and the PIRIN and NPIRIN pins are coupled through the second capacitor, effectively filtering out noise, enhancing signal stability, and ensuring the accuracy of test results. The chip testing device is rationally designed, utilizing a small number of components (capacitors, resistors, and switches) to achieve efficient testing functions, reducing costs and facilitating large-scale production and application.

[0068] The chip testing device of this utility model application operates as follows:

[0069] Step S100: Obtain the chip, power on and warm up the chip, wait 50ms to start the test;

[0070] In this utility model application, after the chip is acquired, its internal circuitry and transistors require a certain amount of time to reach thermal equilibrium. A 50ms warm-up period ensures the stability of the chip's internal temperature and electrical characteristics, preventing test result deviations due to initial instability.

[0071] Step S200: Test chip current parameters: VDD=3V, VPIR pin is floating, SERIN pin is low, INT / DOCI pin is floating, test whether the current is qualified. If yes, the chip is qualified; if no, the chip is unqualified.

[0072] In some embodiments, VDD=3V: provides a 3V operating voltage to the chip to simulate its common operating conditions; VPIR pin is left floating: simulates no external load being applied and tests the chip's quiescent current when there is no PIR signal input; SERIN pin is given a low level: simulates a state without data input; INT / DOCI pin is left floating: ensures that the chip does not output signals.

[0073] In some embodiments, during testing, an ammeter or similar device can be used to measure the current between the VDD pin (pin 4) and the VSS pin (pin 1), and the current value of the chip under the above test conditions can be recorded. It can be determined whether the current value is between 4μA and 8.5μA. If the current value is greater than 8.5μA or less than 4μA, the chip may have problems such as leakage or short circuit, and the chip is judged to be unqualified. If the current value is greater than or equal to 4μA and less than or equal to 8.5μA, the chip is judged to be qualified.

[0074] Step S300: Test the VPIR parameters of the chip: Connect a 440KΩ resistor to the VPIR pin and then ground it. After measuring the voltage, disconnect the resistor and leave the VPIR pin floating.

[0075] In some embodiments, the VPIR pin is grounded after being connected to an external 440KΩ resistor: the VPIR pin is the PIR voltage pin, which can be used to provide voltage to the PIR sensor or as a reference voltage. The external 440KΩ resistor forms a voltage divider circuit to simulate the working load of the PIR sensor and test the chip's voltage output capability under this load.

[0076] In some embodiments, one end of a 440KΩ resistor can be connected to the VPIR pin, and the other end grounded. A voltmeter is used to measure the voltage at the VPIR pin, and the voltage value of the chip under the above test conditions is recorded. After the voltage measurement is completed, the 440KΩ resistor is disconnected, and the VPIR pin is left floating. The voltage value is then checked to see if it is between 2.1V and 2.4V. If the voltage value is greater than 2.1V or less than 2.4V, the chip is considered unqualified; if the voltage value is greater than or equal to 2.1V and less than or equal to 2.4V, the chip is considered qualified. Voltage measurement can determine whether the chip's voltage output is stable and detect potential voltage drift or drive capability problems.

[0077] Step S400: Test the chip's CONF0 parameter: Read the internal configuration data of the chip when it is reset from the INT / DOCI pin, and determine whether the data is all "0". If yes, the chip is qualified; if no, the chip is unqualified.

[0078] In some embodiments, the CONF0 (full name configuration 0, abbreviated as CONF0) parameter is used to test whether the chip can be reset normally, that is, to test the chip's reset parameters. The internal configuration data of the chip is read directly from the INT / DOCI pin. During reset, the data should be all "0"s. The data specification value is 25'H0000000 (i.e., all 0s). "25" indicates the data width, that is, there are a total of 25 bits. "H" indicates that the subsequent numbers are represented in hexadecimal format.

[0079] In some embodiments, when the chip is reset, its internal configuration register is initialized to the default value (which should be all 0 according to the design). In this scenario, the INT / DOCI pin is used as a data output pin. The configuration data after the chip is reset is read by a test device (such as a logic analyzer) to check whether the data is all 0. If the data is all 0, the chip is qualified; if there are non-zero bits in the data, it is unqualified.

[0080] In this utility model application, by checking whether the configuration data after reset is all 0, it can be confirmed whether the chip's reset function is normal. If the data is not all 0, it may indicate that there is a problem with the chip's internal register, reset circuit or storage unit. Potential defects can be detected in time. The test method is direct (only reading and comparing data is required), which improves test efficiency.

[0081] Step S500: Test the chip's DATA_BPF parameters:

[0082] Read the data from bits 39 to 25 of the chip directly from the INT / DOCI pin 10 times, convert it to decimal data using two's complement, and determine whether the absolute value of the 10 data is within 512. If it is, the chip is qualified; otherwise, the chip is unqualified.

[0083] Alternatively, after closing the first switch K1 and keeping the second switch K2 open, wait 0.3 seconds, continuously read 10 data from the INT / DOCI pin, take the absolute value of the 10 numbers, then open the first switch K1, and determine whether the absolute value of the 10 data is within 512; if yes, the chip is qualified; if no, the chip is unqualified.

[0084] Alternatively, after disconnecting the first switch K1 and closing the second switch K2, wait 0.3 seconds, continuously read 10 times from the INT / DOCI pin, take the absolute values ​​of the 10 numbers, then disconnect the second switch K2, and determine whether the absolute values ​​of the 10 data are within 512. If they are, the chip is qualified; if not, the chip is unqualified.

[0085] In some embodiments, the DATA_BPF parameter of the test chip is the data of the test chip after band-pass filtering. DATA_BPF (DATA Band-Pass Filter, i.e., DATA_BPF) is the band-pass filtered data. The DATA_BPF parameter includes the output data of the chip after passing through the band-pass filter (BPF). The data of bits 39-bit25 inside the chip can be read directly from the INT / DOCI pin, a total of 15 bits (39-25+1=15), and read 10 times in a row to obtain 10 sets of 15-bit data.

[0086] In some embodiments, bit 39 is an indicator of whether the signal amplitude has overflowed and is discarded; bit 38 is the sign bit, 0 for positive and 1 for negative; bit 38 and the following bits 37 to 25 are data, each group of 14 bits is stored in two's complement format (two's complement is a binary format for representing signed integers); each group of data is converted to decimal: if the highest bit (bit 38) is 0, the data is positive and is directly converted from binary to decimal; if the highest bit is 1, the data is negative, first inverted (every bit except the sign bit is inverted), 1 is added, the absolute value is calculated, and then a negative sign is added.

[0087] In this utility model application, data is directly read and converted without additional circuit adjustments. The testing process is simple. Data is read 10 times continuously to detect the stability and consistency of chip data output. The method is simple, easy to automate, and suitable for rapid chip screening on the production line.

[0088] In some embodiments, the first switch K1 (connected to the PIRIN pin) is closed, while the second switch K2 (connected to the NPIRIN pin) remains open. The PIRIN pin is grounded through the first switch K1 (R3=0Ω, equivalent to direct grounding), simulating a low-level PIR positive input. Because K2 is open, the NPIRIN pin is grounded through a high-impedance resistor R2 (75GΩ), nearly floating, and waits for 0.3 seconds to ensure the internal circuitry responds to the switch state change and reaches a stable state. Data (bits 39-25, 15 bits) is continuously read 10 times from the INT / DOCI pin, converted to decimal using two's complement, and the absolute values ​​of the 10 data points are calculated. After the test, K1 is opened, the PIRIN pin state is restored, and it is determined whether the absolute values ​​of the 10 data points are all ≤512. If so, the chip is qualified; otherwise, the chip is unqualified.

[0089] In this utility model application, a PIR sensor input state (positive low level, negative high impedance) is simulated by controlling the first switch K1 and the second switch K2. The data output of the test chip under specific PIR signal conditions is close to the actual application scenario. After waiting for 0.3s and reading the data 10 times, the stability of the chip's response to input changes is verified. After the test, K1 is disconnected to avoid affecting other test steps.

[0090] In some embodiments, the first switch K1 is opened and the second switch K2 is closed. The PIRIN pin is grounded through a high impedance R1 (75GΩ), almost floating; the NPIRIN pin is grounded through K2 (R4=0Ω, equivalent to direct grounding), simulating a low level for the negative input. After waiting 0.3 seconds to allow the internal circuitry of the chip to stabilize, data from bit 39 to bit 25 (15 bits) is read continuously 10 times from the INT / DOCI pin, converted to decimal using two's complement, and the absolute value is calculated. After the test is completed, the second switch K2 is opened, the NPIRIN pin state is restored, and it is determined whether the absolute values ​​of the 10 data are all ≤512. If so, the chip is qualified; otherwise, the chip is unqualified.

[0091] In this utility model application, another PIR input state (positive high impedance, negative low level) is simulated by controlling the first switch K1 and the second switch K2 to verify the chip's performance under different conditions. The above-mentioned simulation of an input state of the PIR sensor (positive low level, negative high impedance) by controlling the first switch K1 and the second switch K2 can be combined. The two switch combinations cover multiple input scenarios of PIR signals. After the test, the second switch K2 is disconnected to avoid interference with subsequent tests.

[0092] This utility model application provides three testing methods, which can be selected to read directly or through switch control according to testing needs, adapting to different testing scenarios. It continuously reads data 10 times and judges the absolute value, reducing the random error of a single reading and enhancing the reliability of the test results. By simulating different connection methods of PIR sensitive elements, i.e. signal input methods, through switches, it closely matches actual applications. The judgment standard of absolute value ≤ 512 is simple and clear, easy to automate, and suitable for rapid chip screening in mass production.

[0093] Step S600 includes: testing the CONF1 parameters of the chip: after writing the first configuration data from the SERIN pin, reading the first configuration data inside the chip from the INT / DOCI pin to obtain the first output data, and determining whether the first data and the first output data are consistent. If they are, the chip is qualified; if not, the chip is unqualified.

[0094] In some embodiments, the CONF1 (configuration 1) parameter is tested, which is the first data configured by the chip. The first data includes B0. The first data can be configured by inputting the SERIN pin using a single-wire communication protocol, normally kept low. During configuration, the DOCI pin is kept low. The input format for one bit of data is: clock low for 2µs, clock high for 2µs, and data value for approximately 100µs. The configuration value is 25 bits, with the most significant bit input first. After writing all 25 bits of data, the SERIN pin needs to be pulled low and held for more than 1ms before the data can be read from the DOCI pin. The configuration value is 25'H00000B0, which is also 25'B0 0000 0000 0000 0000 1011 0000.

[0095] In some embodiments, the first configuration data of the chip is read from the INT / DOCI pin (specifically denoted as the DOCI pin). A single-wire communication protocol is used, and the DOCI pin should be pulled low when the configuration is written to the SERIN pin. Different bit values ​​are read bit by bit according to the communication timing; otherwise, it remains in a high-impedance state. The format for reading one bit of data is: a low clock level for 2µs, a high clock level for 2µs, and a high-impedance state for the data value for 10µs. During the middle of this 10µs period, the output state of the DOCI pin is read (high for 1, low for 0).

[0096] In some embodiments, the DOCI pin is normally in a high-impedance state. When the DOCI pin actively outputs a high level, the first data configured inside the chip can be read from the INT / DOCI pin. At this time, the high level is held for about 120us, and then repeated 40 times according to the bit data format. After reading 40 bits of data, the high level is held for more than 1ms, and finally it becomes a high-impedance state, thereby obtaining the first output data.

[0097] In some embodiments, the data consists of 40 bits, read sequentially from the most significant bit to the least significant bit: Bit 39-Bit 25 are ADC signal data (15 bits, 1 bit status indicator + 14 bits data), and Bit 24-Bit 0 are configuration information bits (25 bits). The time interval between data readings between two adjacent frames (times) should be set to 16ms.

[0098] Step S700 includes: testing the chip's DATA_LPF parameter: waiting 100ms, and reading 5 values ​​from the INT / DOCI pin whenever the INT / DOCI pin is high, determining whether the 5 data are within the preset range. If yes, the chip is qualified; otherwise, the chip is unqualified.

[0099] In some embodiments, the DATA_LPF parameter of the test chip is the data after low-pass filtering (LPF) of the test chip. DATA_LPF (DATA Low-Pass Filter, that is, DATA_LPF) is the low-pass filtered data. The DATA_LPF parameter includes the output data of the chip passing through a low-pass filter (Low-Pass Filter, LPF), and is used to evaluate signal smoothing and / or noise suppression performance.

[0100] The test device can be connected to the INT / DOCI pin. The preset range of the data output from the INT / DOCI pin is: 14’H1E00 to 14’H2200. Read the data once when triggered by a high level every 16 ms, continuously for 5 times (about 80 ms), and record the data. If the data for all 5 times is within the range of 14’H1E00 to 14’H2200, the chip is qualified; if the data for a certain time is not within the range of 14’H1E00 to 14’H22B0, the chip is unqualified.

[0101] Step S800 includes: testing the CONF2 parameter of the test chip: after writing the configuration second data from the SERIN pin, then reading the second data configured inside the chip from the INT / DOCI pin to obtain the second output data, and judging whether the second data and the second output data are consistent. If so, the chip is qualified; if not, the chip is unqualified.

[0102] In some embodiments, based on the CONF1 parameter of the above-mentioned test chip, the principle of the CONF2 parameter of the test chip is similar to that of the CONF1 parameter of the test chip, and includes:

[0103] Testing the CONF2 (full name configuration 2, abbreviated as CONF2) parameter, that is, the second data configured by the test chip. The second data includes F0. After writing the configuration second data from the SERIN pin, for example, the configuration value of the second data is 25’H00000F0, then reading the second data configured inside the chip from the INT / DOCI pin to obtain the second output data, and judging whether the second data and the second output data are consistent. If so, the chip is qualified; if not, the chip is unqualified. For example, compare the written second data with the second output data. If they are consistent (such as 25’H00000F0 = 25’H00000F0), the chip is qualified; if they are inconsistent (such as 25’H00000F0 ≠ 25’H00000B0), the chip is unqualified.

[0104] Step S900 includes: testing the DATA_T parameter of the test chip: reading a value once from the INT / DOCI pin, and judging whether Bit24 - Bit0 is the same as the configured number and whether Bit38 - Bit25 is within the set range after conversion. If so, the chip is qualified; if not, the chip is unqualified.

[0105] In some embodiments, the DATA_T parameter (i.e., the DATA_Temp parameter) includes the temperature output data of the chip. Read the value once through the INT / DOCI pin, extract Bit24 - Bit0 and compare it with the configured number. Convert the Bit38 - Bit25 part into a target value, and check whether it is within the set range (such as 14’H1900 to 14’H2200). If Bit24 - Bit0 matches the configured number and the converted value of Bit38 - Bit25 is within the set range, the chip is qualified; otherwise, the chip is unqualified.

[0106] Step S1000 includes: testing the CONF3 parameter of the chip: after writing the third configuration data from the SERIN pin, then read the third internal configuration output data of the chip from the INT / DOCI pin, and determine whether the third data and the third output data are the same. If so, the chip is qualified; if not, the chip is unqualified.

[0107] In some embodiments, based on the above testing of the CONF1 parameter of the chip, the principle of testing the CONF3 parameter of the chip is similar to that of testing the CONF1 parameter of the chip, including:

[0108] Test the CONF3 (full name: configuration 3, abbreviation: CONF3) parameter, that is, test the third configuration data of the chip. The third data includes D0. After writing the third configuration data from the SERIN pin, for example, the configured value of the third data is 25’H00000D0, and then read the third internal configuration data of the chip from the INT / DOCI pin to obtain the third output data, and determine whether the third data and the third output data are the same. If so, the chip is qualified; if not, the chip is unqualified. For example, compare the written third data with the third output data. If they are the same (such as 25’H00000D0 = 25’H00000D0), the chip is qualified; if they are different (such as 25’H00000D0 ≠ 25’H00000F0), the chip is unqualified.

[0109] Step S1100 includes: testing the DATA_V parameter of the chip: read the value once from the INT / DOCI pin, and determine whether Bit24 - Bit0 is the same as the configured number and whether the converted Bit38 - Bit25 is within the set range. If so, the chip is qualified; if not, the chip is unqualified.

[0110] In some embodiments, the DATA_V parameter includes the chip's voltage output data (e.g., voltage VDD). The value is read once via the INT / DOCI pin, Bits 24-Bit0 are extracted and compared with the configuration number, Bits 38-Bit25 are converted to the target value, and it is checked whether they are within the set range (e.g., 14'H3000 to 14'H3400). If Bits 24-Bit0 match the configuration number and the converted value of Bits 38-Bit25 is within the set range, the chip is qualified; otherwise, the chip is unqualified.

[0111] In some embodiments, the chip testing apparatus may perform only steps S100, S200, S300, S400, and S500, and then selectively perform one or more of steps S600, S700, S800, S900, S1000, and S1100 to provide different test conditions for chip testing. If the chip fails in at least one step, the overall chip test result is considered unqualified.

[0112] In some embodiments, steps S400, S500, S600, S700, S800, S900, S1000, and S1100 may also be performed sequentially.

[0113] In this utility model application, after the chip is powered on, it warms up for 0.5 seconds, then the current and VPIR parameters of the chip are tested. Next, steps S400, S500, S600, S700, S800, S900, S1000, and S1100 are performed. The total testing time for steps S400, S500, S600, S700, S800, S900, S1000, and S1100 is only about 0.55 seconds. That is, the chip testing device tests the CONFO parameters of the chip and tests the chip... The combined testing time for the DATA_BPF parameters, CONF1 and DATA_LPF parameters, CONF2 and DATA_T parameters, and CONF3 and DATA_V parameters of the test chip is only about 0.55 seconds. Under the same conditions, the total test time for a single chip is only about 1.1 seconds, improving chip testing efficiency by more than 70%. This allows the same testing machine to produce 8,000-10,000 chips per UPH, completely overcoming the bottleneck that restricts the production efficiency of this type of chip and making it possible to deliver millions of chips per month at a reasonable testing cost.

[0114] The technical features of the above embodiments can be combined in any way. In order to make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0115] Those skilled in the art will understand that the steps, measures, and schemes in the various operations, methods, and processes discussed in this utility model application can be alternated, modified, combined, or deleted; furthermore, other steps, measures, and schemes in the various operations, methods, and processes discussed in this utility model application can also be alternated, modified, rearranged, decomposed, combined, or deleted; furthermore, the steps, measures, and schemes in the prior art that are similar to those disclosed in this utility model application can also be alternated, modified, rearranged, decomposed, combined, or deleted.

[0116] The above-described embodiments are merely examples of several implementation methods of the present disclosure, and their descriptions are relatively specific and detailed. However, they should not be construed as limiting the scope of the patent for the present disclosure. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of the present disclosure, and these all fall within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be determined by the appended claims.

Claims

1. A chip testing device, characterized in that, include: chip; The chip includes VSS pin, INT / DOC I pin, SERIN pin, VDD pin, NC pin, PIRIN pin, NPIRIN pin, and VPIR pin; The VDD pin is connected to the positive terminal of the external power supply, the VSS pin is connected to the negative terminal of the external power supply, and the VDD pin is connected to the VSS pin through the first capacitor. One end of the first resistor is connected to the PIRIN pin, and the other end of the first resistor is grounded. The first switch is located between the first resistor and the PIRIN pin. One end of the first switch is connected to the PIRIN pin, and the other end of the first switch is connected to one end of the third resistor. The other end of the third resistor is grounded. One end of the second resistor is connected to the NPIRIN pin, and the other end of the second resistor is grounded. The second switch is located between the second resistor and the NPIRIN pin. One end of the second switch is connected to the NPIRIN pin, and the other end of the second switch is connected to one end of the fourth resistor. The other end of the fourth resistor is grounded. The PIRIN pin is connected to the NPIRIN pin via a second capacitor.

2. The chip testing device according to claim 1, characterized in that, The chip is an NY86 chip; and / or, the SERIN pin is connected to a signal generator or microcontroller to input serial test data; and / or, the INT / DOC I pin is connected to a test device to monitor the chip's interrupt signals or data output.

3. The chip testing device according to claim 1, characterized in that, The VPIR pin remains floating, the NC pin remains floating; and / or, the first resistor is 75GΩ, the second resistor is 75GΩ; and / or, the third resistor R3 is 0Ω, the fourth resistor R4 is 0Ω.

4. A chip testing apparatus according to claim 1 or 3, characterized in that, The chip testing device tests the chip's current parameters, VPIR parameters, CONFO parameters, and DATA_BPF parameters.

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